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Searched refs:PORT_CONFIG (Results 1 – 2 of 2) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/
Dsl_si91x_peripheral_gpio.h343 ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_SET_REG = (pins); in sl_gpio_set_port_output()
345 GPIO->PORT_CONFIG[port].PORT_SET_REG = (pins); in sl_gpio_set_port_output()
369 …ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_SET_REG = (ULP_GPIO->PORT_CONFIG[port].PORT_SET_REG & ~… in sl_gpio_set_port_output_value()
372 …GPIO->PORT_CONFIG[port].PORT_SET_REG = (GPIO->PORT_CONFIG[port].PORT_SET_REG & ~mask) | (val & mas… in sl_gpio_set_port_output_value()
445 ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_CLEAR_REG = (pins); in sl_gpio_clear_port_output()
447 GPIO->PORT_CONFIG[port].PORT_CLEAR_REG = (pins); in sl_gpio_clear_port_output()
534 return ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_READ_REG & PORT_MASK; in sl_gpio_get_port_input()
536 return GPIO->PORT_CONFIG[port].PORT_READ_REG & PORT_MASK; in sl_gpio_get_port_input()
558 return (ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_READ_REG & PORT_MASK); in sl_gpio_get_port_output()
560 return (GPIO->PORT_CONFIG[port].PORT_READ_REG & PORT_MASK); in sl_gpio_get_port_output()
[all …]
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/
Dsi91x_device.h8814 __IOM EGPIO_PORT_CONFIG_Type PORT_CONFIG[6]; /*!< (@ 0x00001000) [0..5] */ member