Searched refs:PLL_500_CLK_ENABLE (Results 1 – 2 of 2) sorted by relevance
78 SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) |= PLL_500_CLK_ENABLE; in clk_soc_pll_clk_enable()81 SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) &= (uint16_t)(~(PLL_500_CLK_ENABLE)); in clk_soc_pll_clk_enable()164 socreg1 |= (uint16_t)((socPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ in clk_set_soc_pll_freq()237 socreg1 |= (uint16_t)((socPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ in clk_set_soc_pll_freq()249 socreg1 |= (uint16_t)((socPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ in clk_set_soc_pll_freq()263 socreg1 |= (uint16_t)((socPllMulFac << 6) | PLL_500_CLK_ENABLE); // m factor in clk_set_soc_pll_freq()324 socreg1 |= PLL_500_CLK_ENABLE; in clk_soc_pll_set_freq_div()327 socreg1 |= (uint16_t)(mFactor << 6 | PLL_500_CLK_ENABLE); in clk_soc_pll_set_freq_div()330 socreg1 &= (uint16_t)(~PLL_500_CLK_ENABLE); /*soc_pll_clk o/p disable */ in clk_soc_pll_set_freq_div()364 socreg1 |= PLL_500_CLK_ENABLE; in clk_soc_pll_set_freq_div()[all …]
256 #define PLL_500_CLK_ENABLE BIT(3) /* Enables PLL_500_CLK_ENABLE */ macro
