Searched refs:NPSS_INT_BASE (Results 1 – 1 of 1) sorted by relevance
49 #define NPSS_INT_BASE 0x12080000UL ///< UULP INTR base address macro72 (*(volatile uint32_t *)(NPSS_INT_BASE + 0x00)) ///< NPSS mask set register base address74 (*(volatile uint32_t *)(NPSS_INT_BASE + 0x04)) ///< NPSS mask clear register base address76 (*(volatile uint32_t *)(NPSS_INT_BASE + 0x08)) ///< NPSS clear register base address78 (*(volatile uint32_t *)(NPSS_INT_BASE + 0x0C)) ///< NPSS status register base address80 (*(volatile uint32_t *)(NPSS_INT_BASE + 0x10)) ///< NPSS GPIO configuration register base address81 #define UULP_GPIO_STATUS (*(volatile uint32_t *)(NPSS_INT_BASE + 0x14)) ///< UULP GPIO status …
