Searched refs:NPSS_INTR_BASE (Results 1 – 2 of 2) sorted by relevance
44 #define NPSS_GPIO_STATUS (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x14))45 #define NPSS_GPIO_CONFIG_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x10))46 #define NPSS_GPIO_CONFIG_CLR_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x8))
205 #ifndef NPSS_INTR_BASE206 #define NPSS_INTR_BASE 0x12080000 macro209 #define NPSS_INTR_MASK_SET_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x00))212 #define NPSS_INTR_MASK_CLR_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x04))215 #define NPSS_INTR_CLEAR_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x08))218 #define NPSS_INTR_STATUS_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x0C))220 #define M4_ULP_SLP_STATUS_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x1C))
