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Searched refs:NPSS_GPIO_CTRLS_b (Results 1 – 6 of 6) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/
Drsi_retention.h105 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = (unsigned int)(mux & 0x07); in RSI_NPSSGPIO_SetPinMux()
119 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = (unsigned int)(enable & 0x01); in RSI_NPSSGPIO_InputBufferEn()
132 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN = (unsigned int)(dir & 0x01); in RSI_NPSSGPIO_SetDir()
142 return MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN; in RSI_NPSSGPIO_GetDir()
153 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = (unsigned int)(val & 0x01); in RSI_NPSSGPIO_SetPin()
176 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_POLARITY = (unsigned int)(level & 0x01); in RSI_NPSSGPIO_SetPolarity()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/
Dsl_si91x_peripheral_gpio.c225 UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN = direction; in sl_si91x_gpio_set_pin_direction()
990 UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = mode; in sl_si91x_gpio_set_uulp_npss_pin_mux()
1004 UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = receiver; in sl_si91x_gpio_select_uulp_npss_receiver()
1021 UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN = direction; in sl_si91x_gpio_set_uulp_npss_direction()
1038 return UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN; in sl_si91x_gpio_get_uulp_npss_direction()
1056 UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = pin_value; in sl_si91x_gpio_set_uulp_npss_pin_value()
1073 UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT ^= SET; in sl_si91x_gpio_toggle_uulp_npss_pin()
1102 UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_POLARITY = polarity; in sl_si91x_gpio_select_uulp_npss_polarity()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/
Dsl_si91x_peripheral_gpio.h320 UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = SET; in sl_gpio_set_pin_output()
422 UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = CLR; in sl_gpio_clear_pin_output()
594 UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT ^= SET; in sl_gpio_toggle_pin_output()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_pll.c2282 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 3; in clk_xtal_clk_config()
2283 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; in clk_xtal_clk_config()
2287 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 4; in clk_xtal_clk_config()
2288 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; in clk_xtal_clk_config()
2292 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 5; in clk_xtal_clk_config()
2293 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; in clk_xtal_clk_config()
2297 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 6; in clk_xtal_clk_config()
2298 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; in clk_xtal_clk_config()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/
Dsystem_si91x.c135 MCU_RET->NPSS_GPIO_CNTRL[0].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 0; in SystemCoreClockUpdate()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/
Dsi91x_device.h950 } NPSS_GPIO_CTRLS_b; member