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Searched refs:MSC_CACHECMD_INVCACHE (Results 1 – 25 of 73) sorted by relevance

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/hal_silabs-latest/gecko/emlib/inc/
Dem_chip.h70 #if defined(MSC_CACHECMD_INVCACHE) in CHIP_Init()
71 MSC->CACHECMD = MSC_CACHECMD_INVCACHE; in CHIP_Init()
Dem_msc.h753 MSC->CACHECMD = MSC_CACHECMD_INVCACHE; in MSC_FlushCache()
/hal_silabs-latest/simplicity_sdk/platform/emlib/inc/
Dem_chip.h74 #if defined(MSC_CACHECMD_INVCACHE) in CHIP_Init()
75 MSC->CACHECMD = MSC_CACHECMD_INVCACHE; in CHIP_Init()
Dem_msc.h760 MSC->CACHECMD = MSC_CACHECMD_INVCACHE; in MSC_FlushCache()
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p_msc.h418 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalida… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b_msc.h418 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalida… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_msc.h480 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< In… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_msc.h480 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< In… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_msc.h499 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_msc.h499 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_msc.h499 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_msc.h611 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_msc.h652 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
Defm32gg12b530f512il120.h2792 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
Defm32gg12b530f512im64.h2792 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
Defm32gg12b530f512iq100.h2792 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
Defm32gg12b530f512iq64.h2792 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
Defm32gg12b530f512gq100.h2792 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
Defm32gg12b530f512gq64.h2792 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
Defm32gg12b530f512il112.h2792 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
Defm32gg12b110f1024gm64.h2784 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
Defm32gg12b110f1024gq64.h2784 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
Defm32gg12b530f512gl112.h2792 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
Defm32gg12b530f512gl120.h2792 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro
Defm32gg12b530f512gm64.h2792 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**… macro

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