Searched refs:MODE_SET (Results 1 – 18 of 18) sorted by relevance
212 basePointer->MODE_SET = input << SI32_CMP_A_MODE_NMUX_SHIFT; in _SI32_CMP_A_select_negative_input()229 basePointer->MODE_SET = input << SI32_CMP_A_MODE_PMUX_SHIFT; in _SI32_CMP_A_select_positive_input()253 basePointer->MODE_SET = mux << SI32_CMP_A_MODE_INMUX_SHIFT; in _SI32_CMP_A_select_mux()271 basePointer->MODE_SET = mode << SI32_CMP_A_MODE_CMPMD_SHIFT; in _SI32_CMP_A_select_response_power_mode()284 basePointer->MODE_SET = SI32_CMP_A_MODE_FIEN_MASK; in _SI32_CMP_A_enable_falling_edge_interrupt()323 basePointer->MODE_SET = SI32_CMP_A_MODE_RIEN_MASK; in _SI32_CMP_A_enable_rising_edge_interrupt()367 basePointer->MODE_SET = value << SI32_CMP_A_MODE_DACLVL_SHIFT; in _SI32_CMP_A_write_dac_level_setting()395 basePointer->MODE_SET = SI32_CMP_A_MODE_NWPUEN_MASK; in _SI32_CMP_A_enable_negative_weak_pullup()421 basePointer->MODE_SET = SI32_CMP_A_MODE_PWPUEN_MASK; in _SI32_CMP_A_enable_positive_weak_pullup()461 basePointer->MODE_SET = SI32_CMP_A_MODE_CMPHYN_NEG_5_MV_U32; in _SI32_CMP_A_select_negative_hysteresis_5mv()[all …]
261 basePointer->MODE_SET = input << SI32_CMP_A_MODE_NMUX_SHIFT;\283 basePointer->MODE_SET = input << SI32_CMP_A_MODE_PMUX_SHIFT;\312 basePointer->MODE_SET = mux << SI32_CMP_A_MODE_INMUX_SHIFT;\335 basePointer->MODE_SET = mode << SI32_CMP_A_MODE_CMPMD_SHIFT;\349 (basePointer->MODE_SET = SI32_CMP_A_MODE_FIEN_MASK)388 (basePointer->MODE_SET = SI32_CMP_A_MODE_RIEN_MASK)438 basePointer->MODE_SET = value << SI32_CMP_A_MODE_DACLVL_SHIFT;\469 (basePointer->MODE_SET = SI32_CMP_A_MODE_NWPUEN_MASK)495 (basePointer->MODE_SET = SI32_CMP_A_MODE_PWPUEN_MASK)535 basePointer->MODE_SET = SI32_CMP_A_MODE_CMPHYN_NEG_5_MV_U32;\[all …]
604 basePointer->MODE_SET = SI32_USART_B_MODE_DBGMD_HALT_U32; in _SI32_USART_B_enable_stall_in_debug_mode()644 basePointer->MODE_SET = SI32_USART_B_MODE_LBMD_RXONLY_U32; in _SI32_USART_B_enter_receive_loopback_mode()658 basePointer->MODE_SET = SI32_USART_B_MODE_LBMD_TXONLY_U32; in _SI32_USART_B_enter_transmit_loopback_mode()671 basePointer->MODE_SET = SI32_USART_B_MODE_LBMD_BOTH_U32; in _SI32_USART_B_enter_full_loopback_mode()684 basePointer->MODE_SET = SI32_USART_B_MODE_STPSTCLK_ENABLED_U32; in _SI32_USART_B_enable_master_generate_clock_during_stop()710 basePointer->MODE_SET = SI32_USART_B_MODE_STRTSTCLK_ENABLED_U32; in _SI32_USART_B_enable_master_generate_clock_during_start()736 basePointer->MODE_SET = SI32_USART_B_MODE_ISTCLK_ENABLED_U32; in _SI32_USART_B_enable_master_generate_clock_between_transfers()762 basePointer->MODE_SET = SI32_USART_B_MODE_DUPLEXMD_HALF_DUPLEX_U32; in _SI32_USART_B_enter_half_duplex_mode()801 basePointer->MODE_SET = SI32_USART_B_MODE_CLKIDLE_IDLE_HIGH_U32; in _SI32_USART_B_select_sync_clock_high_during_idle()827 basePointer->MODE_SET = SI32_USART_B_MODE_CLKESEL_RISING_U32; in _SI32_USART_B_select_clock_edge_rising()[all …]
603 basePointer->MODE_SET = SI32_USART_A_MODE_DBGMD_HALT_U32; in _SI32_USART_A_enable_stall_in_debug_mode()643 basePointer->MODE_SET = SI32_USART_A_MODE_LBMD_RXONLY_U32; in _SI32_USART_A_enter_receive_loopback_mode()657 basePointer->MODE_SET = SI32_USART_A_MODE_LBMD_TXONLY_U32; in _SI32_USART_A_enter_transmit_loopback_mode()670 basePointer->MODE_SET = SI32_USART_A_MODE_LBMD_BOTH_U32; in _SI32_USART_A_enter_full_loopback_mode()683 basePointer->MODE_SET = SI32_USART_A_MODE_STPSTCLK_ENABLED_U32; in _SI32_USART_A_enable_master_generate_clock_during_stop()709 basePointer->MODE_SET = SI32_USART_A_MODE_STRTSTCLK_ENABLED_U32; in _SI32_USART_A_enable_master_generate_clock_during_start()735 basePointer->MODE_SET = SI32_USART_A_MODE_ISTCLK_ENABLED_U32; in _SI32_USART_A_enable_master_generate_clock_between_transfers()761 basePointer->MODE_SET = SI32_USART_A_MODE_DUPLEXMD_HALF_DUPLEX_U32; in _SI32_USART_A_enter_half_duplex_mode()800 basePointer->MODE_SET = SI32_USART_A_MODE_CLKIDLE_IDLE_HIGH_U32; in _SI32_USART_A_select_sync_clock_high_during_idle()826 basePointer->MODE_SET = SI32_USART_A_MODE_CLKESEL_RISING_U32; in _SI32_USART_A_select_clock_edge_rising()[all …]
503 basePointer->MODE_SET = SI32_UART_B_MODE_RTCCKMD_RTC0TCLK_U32; in _SI32_UART_B_select_rtc_clock_mode()529 basePointer->MODE_SET = SI32_UART_B_MODE_RTCBDMD_ENABLED_U32; in _SI32_UART_B_enter_rtc_baud_rate_mode()568 basePointer->MODE_SET = SI32_UART_B_MODE_FORCECLK_ENABLED_U32; in _SI32_UART_B_select_internal_clock_always_on()594 basePointer->MODE_SET = SI32_UART_B_MODE_RXCLKSW_ENABLED_U32; in _SI32_UART_B_enable_rx_clock_switch()620 basePointer->MODE_SET = SI32_UART_B_MODE_TXCLKSW_ENABLED_U32; in _SI32_UART_B_enable_tx_clock_switch()646 basePointer->MODE_SET = SI32_UART_B_MODE_DBGMD_HALT_U32; in _SI32_UART_B_enable_stall_in_debug_mode()686 basePointer->MODE_SET = SI32_UART_B_MODE_LBMD_RXONLY_U32; in _SI32_UART_B_enter_receive_loopback_mode()700 basePointer->MODE_SET = SI32_UART_B_MODE_LBMD_TXONLY_U32; in _SI32_UART_B_enter_transmit_loopback_mode()713 basePointer->MODE_SET = SI32_UART_B_MODE_LBMD_BOTH_U32; in _SI32_UART_B_enter_full_loopback_mode()726 basePointer->MODE_SET = SI32_UART_B_MODE_DUPLEXMD_HALF_DUPLEX_U32; in _SI32_UART_B_enter_half_duplex_mode()[all …]
704 (basePointer->MODE_SET = SI32_USART_A_MODE_DBGMD_HALT_U32)744 basePointer->MODE_SET = SI32_USART_A_MODE_LBMD_RXONLY_U32;\759 basePointer->MODE_SET = SI32_USART_A_MODE_LBMD_TXONLY_U32;\773 (basePointer->MODE_SET = SI32_USART_A_MODE_LBMD_BOTH_U32)786 (basePointer->MODE_SET = SI32_USART_A_MODE_STPSTCLK_ENABLED_U32)812 (basePointer->MODE_SET = SI32_USART_A_MODE_STRTSTCLK_ENABLED_U32)838 (basePointer->MODE_SET = SI32_USART_A_MODE_ISTCLK_ENABLED_U32)864 (basePointer->MODE_SET = SI32_USART_A_MODE_DUPLEXMD_HALF_DUPLEX_U32)903 (basePointer->MODE_SET = SI32_USART_A_MODE_CLKIDLE_IDLE_HIGH_U32)929 (basePointer->MODE_SET = SI32_USART_A_MODE_CLKESEL_RISING_U32)[all …]
704 (basePointer->MODE_SET = SI32_USART_B_MODE_DBGMD_HALT_U32)744 basePointer->MODE_SET = SI32_USART_B_MODE_LBMD_RXONLY_U32;\759 basePointer->MODE_SET = SI32_USART_B_MODE_LBMD_TXONLY_U32;\773 (basePointer->MODE_SET = SI32_USART_B_MODE_LBMD_BOTH_U32)786 (basePointer->MODE_SET = SI32_USART_B_MODE_STPSTCLK_ENABLED_U32)812 (basePointer->MODE_SET = SI32_USART_B_MODE_STRTSTCLK_ENABLED_U32)838 (basePointer->MODE_SET = SI32_USART_B_MODE_ISTCLK_ENABLED_U32)864 (basePointer->MODE_SET = SI32_USART_B_MODE_DUPLEXMD_HALF_DUPLEX_U32)903 (basePointer->MODE_SET = SI32_USART_B_MODE_CLKIDLE_IDLE_HIGH_U32)929 (basePointer->MODE_SET = SI32_USART_B_MODE_CLKESEL_RISING_U32)[all …]
607 basePointer->MODE_SET = SI32_UART_B_MODE_RTCCKMD_RTC0TCLK_U32;\634 (basePointer->MODE_SET = SI32_UART_B_MODE_RTCBDMD_ENABLED_U32)673 (basePointer->MODE_SET = SI32_UART_B_MODE_FORCECLK_ENABLED_U32)699 (basePointer->MODE_SET = SI32_UART_B_MODE_RXCLKSW_ENABLED_U32)725 (basePointer->MODE_SET = SI32_UART_B_MODE_TXCLKSW_ENABLED_U32)751 (basePointer->MODE_SET = SI32_UART_B_MODE_DBGMD_HALT_U32)791 basePointer->MODE_SET = SI32_UART_B_MODE_LBMD_RXONLY_U32;\806 basePointer->MODE_SET = SI32_UART_B_MODE_LBMD_TXONLY_U32;\820 (basePointer->MODE_SET = SI32_UART_B_MODE_LBMD_BOTH_U32)833 (basePointer->MODE_SET = SI32_UART_B_MODE_DUPLEXMD_HALF_DUPLEX_U32)[all …]
592 basePointer->MODE_SET = gain << SI32_CAPSENSE_A_MODE_CGSEL_SHIFT; in _SI32_CAPSENSE_A_set_gain()613 basePointer->MODE_SET = ramp << SI32_CAPSENSE_A_MODE_RAMPSEL_SHIFT; in _SI32_CAPSENSE_A_set_ramp_selection()633 basePointer->MODE_SET = current << SI32_CAPSENSE_A_MODE_IASEL_SHIFT; in _SI32_CAPSENSE_A_set_output_current()652 basePointer->MODE_SET = time << SI32_CAPSENSE_A_MODE_DTSEL_SHIFT; in _SI32_CAPSENSE_A_set_discharge_time()
703 basePointer->MODE_SET = gain << SI32_CAPSENSE_A_MODE_CGSEL_SHIFT;\731 basePointer->MODE_SET = ramp << SI32_CAPSENSE_A_MODE_RAMPSEL_SHIFT;\758 basePointer->MODE_SET = current << SI32_CAPSENSE_A_MODE_IASEL_SHIFT;\784 basePointer->MODE_SET = time << SI32_CAPSENSE_A_MODE_DTSEL_SHIFT;\
551 basePointer->MODE_SET = SI32_UART_A_MODE_DBGMD_HALT_U32; in _SI32_UART_A_enable_stall_in_debug_mode()591 basePointer->MODE_SET = SI32_UART_A_MODE_LBMD_RX_ONLY_U32; in _SI32_UART_A_enter_receive_loopback_mode()605 basePointer->MODE_SET = SI32_UART_A_MODE_LBMD_TX_ONLY_U32; in _SI32_UART_A_enter_transmit_loopback_mode()618 basePointer->MODE_SET = SI32_UART_A_MODE_LBMD_BOTH_U32; in _SI32_UART_A_enter_full_loopback_mode()631 basePointer->MODE_SET = SI32_UART_A_MODE_DUPLEXMD_HALF_DUPLEX_U32; in _SI32_UART_A_enter_half_duplex_mode()657 basePointer->MODE_SET = SI32_UART_A_MODE_ITSEN_ENABLED_U32; in _SI32_UART_A_enable_idle_tx_tristate()
652 (basePointer->MODE_SET = SI32_UART_A_MODE_DBGMD_HALT_U32)692 basePointer->MODE_SET = SI32_UART_A_MODE_LBMD_RX_ONLY_U32;\707 basePointer->MODE_SET = SI32_UART_A_MODE_LBMD_TX_ONLY_U32;\721 (basePointer->MODE_SET = SI32_UART_A_MODE_LBMD_BOTH_U32)734 (basePointer->MODE_SET = SI32_UART_A_MODE_DUPLEXMD_HALF_DUPLEX_U32)760 (basePointer->MODE_SET = SI32_UART_A_MODE_ITSEN_ENABLED_U32)
420 volatile uint32_t MODE_SET; member
578 volatile uint32_t MODE_SET; member
1154 volatile uint32_t MODE_SET; member
1166 volatile uint32_t MODE_SET; member
1328 volatile uint32_t MODE_SET; member
1345 volatile uint32_t MODE_SET; member
