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Searched refs:MCU_RET (Results 1 – 4 of 4) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/
Drsi_retention.h105 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = (unsigned int)(mux & 0x07); in RSI_NPSSGPIO_SetPinMux()
119 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = (unsigned int)(enable & 0x01); in RSI_NPSSGPIO_InputBufferEn()
132 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN = (unsigned int)(dir & 0x01); in RSI_NPSSGPIO_SetDir()
142 return MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN; in RSI_NPSSGPIO_GetDir()
153 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = (unsigned int)(val & 0x01); in RSI_NPSSGPIO_SetPin()
176 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_POLARITY = (unsigned int)(level & 0x01); in RSI_NPSSGPIO_SetPolarity()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_pll.c115 …if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10)))… in clk_set_soc_pll_freq()
312 …if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10)))… in clk_soc_pll_set_freq_div()
839 …if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10)))… in clk_set_intf_pll_freq()
1039 …if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10)))… in clk_intf_pll_set_freq_div()
2282 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 3; in clk_xtal_clk_config()
2283 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; in clk_xtal_clk_config()
2287 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 4; in clk_xtal_clk_config()
2288 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; in clk_xtal_clk_config()
2292 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 5; in clk_xtal_clk_config()
2293 MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; in clk_xtal_clk_config()
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/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/
Dsystem_si91x.c135 MCU_RET->NPSS_GPIO_CNTRL[0].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 0; in SystemCoreClockUpdate()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/
Dsi91x_device.h15990 #define MCU_RET ((MCU_RET_Type *)MCU_RET_BASE) macro