Searched refs:M4_BBFF_STORAGE1 (Results 1 – 3 of 3) sorted by relevance
195 if (MCURET_BOOTSTATUS_REG & BIT(13) || (M4_BBFF_STORAGE1 & PSRAM_SEC_EN)) { in RSI_PS_RetentionSleepConfig_bypass()198 M4_BBFF_STORAGE1 |= KEY_LENGTH; in RSI_PS_RetentionSleepConfig_bypass()201 M4_BBFF_STORAGE1 &= ~(0xffUL << STACK_AND_CB_ADDR_BIT_NO); in RSI_PS_RetentionSleepConfig_bypass()203 M4_BBFF_STORAGE1 |= (((stack_address >> 11) & 0xFF) << STACK_AND_CB_ADDR_BIT_NO); in RSI_PS_RetentionSleepConfig_bypass()205 M4_BBFF_STORAGE1 |= STACK_AND_CB_ADDR_PRESENT_IN_BBFF; in RSI_PS_RetentionSleepConfig_bypass()
115 …if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10)))… in clk_set_soc_pll_freq()177 if (socPllTvRead <= (M4_BBFF_STORAGE1 & 0x001F)) { in clk_set_soc_pll_freq()312 …if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10)))… in clk_soc_pll_set_freq_div()344 if ((socPllTvRead <= (M4_BBFF_STORAGE1 & 0x001F)) && (divFactor == 0)) { in clk_soc_pll_set_freq_div()839 …if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10)))… in clk_set_intf_pll_freq()900 if (intfPllTvRead <= ((M4_BBFF_STORAGE1 & 0x03E0) >> 5)) { in clk_set_intf_pll_freq()1039 …if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10)))… in clk_intf_pll_set_freq_div()1070 if ((intfPllTvRead <= ((M4_BBFF_STORAGE1 & 0x03E0) >> 5)) && (divFactor == 0)) { in clk_intf_pll_set_freq_div()
54 #define M4_BBFF_STORAGE1 *(volatile uint32_t *)(MCU_NPSS_BASE_ADDR + 0x0580) macro
