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Searched refs:LFACLKEN0 (Results 1 – 25 of 152) sorted by relevance

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/hal_silabs-latest/gecko/emlib/inc/
Dem_chip.h294 CMU->LFACLKEN0 |= CMU_LFACLKEN0_LCD; in CHIP_Init()
296 CMU->LFACLKEN0 &= ~CMU_LFACLKEN0_LCD; in CHIP_Init()
/hal_silabs-latest/simplicity_sdk/platform/emlib/inc/
Dem_chip.h298 CMU->LFACLKEN0 |= CMU_LFACLKEN0_LCD; in CHIP_Init()
300 CMU->LFACLKEN0 &= ~CMU_LFACLKEN0_LCD; in CHIP_Init()
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32HG/Include/
Defm32hg_cmu.h68 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32hg210f32.h273 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32hg210f64.h273 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32hg222f32.h273 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32hg222f64.h273 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32hg110f32.h273 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32hg110f64.h273 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32WG/Include/
Defm32wg_cmu.h68 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32wg380f128.h325 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32wg380f256.h325 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32wg380f64.h325 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32wg390f128.h325 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32wg390f256.h325 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32wg390f64.h325 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32wg395f128.h325 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32wg395f256.h325 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32wg395f64.h325 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32wg280f128.h316 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32wg280f256.h316 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
Defm32wg280f64.h316 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ member
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p_cmu.h95 __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ member
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b_cmu.h95 __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ member
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_cmu.h98 __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ member

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