1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // Script: 0.57 24 // Version: 1 25 26 #ifndef __SI32_USBEP_A_REGISTERS_H__ 27 #define __SI32_USBEP_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_USBEP_A_EPMPSIZE_Struct 36 { 37 union 38 { 39 struct 40 { 41 // IN Maximum Packet Size 42 volatile uint8_t IMAXP; 43 uint32_t reserved0: 8; 44 // OUT Maximum Packet Size 45 volatile uint8_t OMAXP; 46 uint32_t reserved1: 8; 47 }; 48 volatile uint32_t U32; 49 }; 50 }; 51 52 #define SI32_USBEP_A_EPMPSIZE_IMAXP_MASK 0x000000FF 53 #define SI32_USBEP_A_EPMPSIZE_IMAXP_SHIFT 0 54 55 #define SI32_USBEP_A_EPMPSIZE_OMAXP_MASK 0x00FF0000 56 #define SI32_USBEP_A_EPMPSIZE_OMAXP_SHIFT 16 57 58 59 60 struct SI32_USBEP_A_EPCONTROL_Struct 61 { 62 union 63 { 64 struct 65 { 66 // IN Packet Ready Indicator 67 volatile uint32_t IPRDYI: 1; 68 // IN FIFO Not Empty Flag 69 volatile uint32_t IFIFONEF: 1; 70 // IN FIFO Underrun Flag 71 volatile uint32_t IURF: 1; 72 // IN FIFO Flush 73 volatile uint32_t IFIFOFL: 1; 74 // IN Send Stall 75 volatile uint32_t ISDSTL: 1; 76 // IN Sent Stall Interrupt Flag 77 volatile uint32_t ISTSTLI: 1; 78 // IN Clear Data Toggle 79 volatile uint32_t ICLRDT: 1; 80 uint32_t reserved0: 3; 81 // FIFO Split Enable 82 volatile uint32_t SPLITEN: 1; 83 // Force Data Toggle Enable 84 volatile uint32_t FDTEN: 1; 85 // IN Endpoint DMA Enable 86 volatile uint32_t IDMAEN: 1; 87 // Endpoint Direction Select 88 volatile uint32_t DIRSEL: 1; 89 // IN Isochronous Transfer Enable 90 volatile uint32_t IISOEN: 1; 91 // IN Endpoint IPRDYI Automatic Set Enable 92 volatile uint32_t AUTOSETEN: 1; 93 // OUT Packet Ready 94 volatile uint32_t OPRDYI: 1; 95 // OUT FIFO Full 96 volatile uint32_t OFIFOFF: 1; 97 // OUT FIFO Overrun Flag 98 volatile uint32_t OORF: 1; 99 // OUT Data Error Flag 100 volatile uint32_t ODERRF: 1; 101 // OUT FIFO Flush 102 volatile uint32_t OFIFOFL: 1; 103 // OUT Send Stall 104 volatile uint32_t OSDSTL: 1; 105 // OUT Sent Stall Interrupt Flag 106 volatile uint32_t OSTSTLI: 1; 107 // OUT Clear Data Toggle 108 volatile uint32_t OCLRDT: 1; 109 uint32_t reserved1: 4; 110 // OUT Endpoint DMA Mode 111 volatile uint32_t ODMAMD: 1; 112 // OUT Endpoint DMA Enable 113 volatile uint32_t ODMAEN: 1; 114 // OUT Isochronous Transfer Enable 115 volatile uint32_t OISOEN: 1; 116 // OUT Endpoint OPRDYI Auto-Clear Enable 117 volatile uint32_t AUTOCLREN: 1; 118 }; 119 volatile uint32_t U32; 120 }; 121 }; 122 123 #define SI32_USBEP_A_EPCONTROL_IPRDYI_MASK 0x00000001 124 #define SI32_USBEP_A_EPCONTROL_IPRDYI_SHIFT 0 125 // The packet has been sent or there is an open FIFO slot. 126 #define SI32_USBEP_A_EPCONTROL_IPRDYI_NOT_SET_VALUE 0 127 #define SI32_USBEP_A_EPCONTROL_IPRDYI_NOT_SET_U32 \ 128 (SI32_USBEP_A_EPCONTROL_IPRDYI_NOT_SET_VALUE << SI32_USBEP_A_EPCONTROL_IPRDYI_SHIFT) 129 // A packet is loaded in the FIFO. 130 #define SI32_USBEP_A_EPCONTROL_IPRDYI_SET_VALUE 1 131 #define SI32_USBEP_A_EPCONTROL_IPRDYI_SET_U32 \ 132 (SI32_USBEP_A_EPCONTROL_IPRDYI_SET_VALUE << SI32_USBEP_A_EPCONTROL_IPRDYI_SHIFT) 133 134 #define SI32_USBEP_A_EPCONTROL_IFIFONEF_MASK 0x00000002 135 #define SI32_USBEP_A_EPCONTROL_IFIFONEF_SHIFT 1 136 // The IN Endpoint FIFO is empty. 137 #define SI32_USBEP_A_EPCONTROL_IFIFONEF_NOT_SET_VALUE 0 138 #define SI32_USBEP_A_EPCONTROL_IFIFONEF_NOT_SET_U32 \ 139 (SI32_USBEP_A_EPCONTROL_IFIFONEF_NOT_SET_VALUE << SI32_USBEP_A_EPCONTROL_IFIFONEF_SHIFT) 140 // The IN Endpoint FIFO contains one or more packets. 141 #define SI32_USBEP_A_EPCONTROL_IFIFONEF_SET_VALUE 1 142 #define SI32_USBEP_A_EPCONTROL_IFIFONEF_SET_U32 \ 143 (SI32_USBEP_A_EPCONTROL_IFIFONEF_SET_VALUE << SI32_USBEP_A_EPCONTROL_IFIFONEF_SHIFT) 144 145 #define SI32_USBEP_A_EPCONTROL_IURF_MASK 0x00000004 146 #define SI32_USBEP_A_EPCONTROL_IURF_SHIFT 2 147 // Underrun has not occurred. 148 #define SI32_USBEP_A_EPCONTROL_IURF_NOT_SET_VALUE 0 149 #define SI32_USBEP_A_EPCONTROL_IURF_NOT_SET_U32 \ 150 (SI32_USBEP_A_EPCONTROL_IURF_NOT_SET_VALUE << SI32_USBEP_A_EPCONTROL_IURF_SHIFT) 151 // Underrun occurred. 152 #define SI32_USBEP_A_EPCONTROL_IURF_SET_VALUE 1 153 #define SI32_USBEP_A_EPCONTROL_IURF_SET_U32 \ 154 (SI32_USBEP_A_EPCONTROL_IURF_SET_VALUE << SI32_USBEP_A_EPCONTROL_IURF_SHIFT) 155 156 #define SI32_USBEP_A_EPCONTROL_IFIFOFL_MASK 0x00000008 157 #define SI32_USBEP_A_EPCONTROL_IFIFOFL_SHIFT 3 158 // Flush the IN FIFO. 159 #define SI32_USBEP_A_EPCONTROL_IFIFOFL_SET_VALUE 1 160 #define SI32_USBEP_A_EPCONTROL_IFIFOFL_SET_U32 \ 161 (SI32_USBEP_A_EPCONTROL_IFIFOFL_SET_VALUE << SI32_USBEP_A_EPCONTROL_IFIFOFL_SHIFT) 162 163 #define SI32_USBEP_A_EPCONTROL_ISDSTL_MASK 0x00000010 164 #define SI32_USBEP_A_EPCONTROL_ISDSTL_SHIFT 4 165 // Stop sending a stall. 166 #define SI32_USBEP_A_EPCONTROL_ISDSTL_NOT_SET_VALUE 0 167 #define SI32_USBEP_A_EPCONTROL_ISDSTL_NOT_SET_U32 \ 168 (SI32_USBEP_A_EPCONTROL_ISDSTL_NOT_SET_VALUE << SI32_USBEP_A_EPCONTROL_ISDSTL_SHIFT) 169 // Generate a stall. 170 #define SI32_USBEP_A_EPCONTROL_ISDSTL_SET_VALUE 1 171 #define SI32_USBEP_A_EPCONTROL_ISDSTL_SET_U32 \ 172 (SI32_USBEP_A_EPCONTROL_ISDSTL_SET_VALUE << SI32_USBEP_A_EPCONTROL_ISDSTL_SHIFT) 173 174 #define SI32_USBEP_A_EPCONTROL_ISTSTLI_MASK 0x00000020 175 #define SI32_USBEP_A_EPCONTROL_ISTSTLI_SHIFT 5 176 // Read: A stall condition has not been sent since this bit was last cleared. 177 // Write: Clear the interrupt. 178 #define SI32_USBEP_A_EPCONTROL_ISTSTLI_NOT_SET_VALUE 0 179 #define SI32_USBEP_A_EPCONTROL_ISTSTLI_NOT_SET_U32 \ 180 (SI32_USBEP_A_EPCONTROL_ISTSTLI_NOT_SET_VALUE << SI32_USBEP_A_EPCONTROL_ISTSTLI_SHIFT) 181 // Read: A stall condition has been sent since this bit was last cleared. Write: No 182 // effect. 183 #define SI32_USBEP_A_EPCONTROL_ISTSTLI_SET_VALUE 1 184 #define SI32_USBEP_A_EPCONTROL_ISTSTLI_SET_U32 \ 185 (SI32_USBEP_A_EPCONTROL_ISTSTLI_SET_VALUE << SI32_USBEP_A_EPCONTROL_ISTSTLI_SHIFT) 186 187 #define SI32_USBEP_A_EPCONTROL_ICLRDT_MASK 0x00000040 188 #define SI32_USBEP_A_EPCONTROL_ICLRDT_SHIFT 6 189 // Do not reset the IN data toggle. 190 #define SI32_USBEP_A_EPCONTROL_ICLRDT_NO_RESET_VALUE 0 191 #define SI32_USBEP_A_EPCONTROL_ICLRDT_NO_RESET_U32 \ 192 (SI32_USBEP_A_EPCONTROL_ICLRDT_NO_RESET_VALUE << SI32_USBEP_A_EPCONTROL_ICLRDT_SHIFT) 193 // Reset the IN data toggle. 194 #define SI32_USBEP_A_EPCONTROL_ICLRDT_RESET_VALUE 1 195 #define SI32_USBEP_A_EPCONTROL_ICLRDT_RESET_U32 \ 196 (SI32_USBEP_A_EPCONTROL_ICLRDT_RESET_VALUE << SI32_USBEP_A_EPCONTROL_ICLRDT_SHIFT) 197 198 #define SI32_USBEP_A_EPCONTROL_SPLITEN_MASK 0x00000400 199 #define SI32_USBEP_A_EPCONTROL_SPLITEN_SHIFT 10 200 // Do not split the endpoint FIFO. 201 #define SI32_USBEP_A_EPCONTROL_SPLITEN_DISABLED_VALUE 0 202 #define SI32_USBEP_A_EPCONTROL_SPLITEN_DISABLED_U32 \ 203 (SI32_USBEP_A_EPCONTROL_SPLITEN_DISABLED_VALUE << SI32_USBEP_A_EPCONTROL_SPLITEN_SHIFT) 204 // Split the endpoint FIFO. 205 #define SI32_USBEP_A_EPCONTROL_SPLITEN_ENABLED_VALUE 1 206 #define SI32_USBEP_A_EPCONTROL_SPLITEN_ENABLED_U32 \ 207 (SI32_USBEP_A_EPCONTROL_SPLITEN_ENABLED_VALUE << SI32_USBEP_A_EPCONTROL_SPLITEN_SHIFT) 208 209 #define SI32_USBEP_A_EPCONTROL_FDTEN_MASK 0x00000800 210 #define SI32_USBEP_A_EPCONTROL_FDTEN_SHIFT 11 211 // The endpoint data toggle switches only when an ACK is received following a data 212 // packet transmission. 213 #define SI32_USBEP_A_EPCONTROL_FDTEN_DISABLED_VALUE 0 214 #define SI32_USBEP_A_EPCONTROL_FDTEN_DISABLED_U32 \ 215 (SI32_USBEP_A_EPCONTROL_FDTEN_DISABLED_VALUE << SI32_USBEP_A_EPCONTROL_FDTEN_SHIFT) 216 // The endpoint data toggle is forced to switch after every data packet is 217 // transmitted, regardless of ACK reception. 218 #define SI32_USBEP_A_EPCONTROL_FDTEN_ENABLED_VALUE 1 219 #define SI32_USBEP_A_EPCONTROL_FDTEN_ENABLED_U32 \ 220 (SI32_USBEP_A_EPCONTROL_FDTEN_ENABLED_VALUE << SI32_USBEP_A_EPCONTROL_FDTEN_SHIFT) 221 222 #define SI32_USBEP_A_EPCONTROL_IDMAEN_MASK 0x00001000 223 #define SI32_USBEP_A_EPCONTROL_IDMAEN_SHIFT 12 224 // Disable the DMA request for the IN endpoint. 225 #define SI32_USBEP_A_EPCONTROL_IDMAEN_DISABLED_VALUE 0 226 #define SI32_USBEP_A_EPCONTROL_IDMAEN_DISABLED_U32 \ 227 (SI32_USBEP_A_EPCONTROL_IDMAEN_DISABLED_VALUE << SI32_USBEP_A_EPCONTROL_IDMAEN_SHIFT) 228 // Enable the DMA request for the IN endpoint. 229 #define SI32_USBEP_A_EPCONTROL_IDMAEN_ENABLED_VALUE 1 230 #define SI32_USBEP_A_EPCONTROL_IDMAEN_ENABLED_U32 \ 231 (SI32_USBEP_A_EPCONTROL_IDMAEN_ENABLED_VALUE << SI32_USBEP_A_EPCONTROL_IDMAEN_SHIFT) 232 233 #define SI32_USBEP_A_EPCONTROL_DIRSEL_MASK 0x00002000 234 #define SI32_USBEP_A_EPCONTROL_DIRSEL_SHIFT 13 235 // Select the endpoint direction as OUT. 236 #define SI32_USBEP_A_EPCONTROL_DIRSEL_OUT_VALUE 0 237 #define SI32_USBEP_A_EPCONTROL_DIRSEL_OUT_U32 \ 238 (SI32_USBEP_A_EPCONTROL_DIRSEL_OUT_VALUE << SI32_USBEP_A_EPCONTROL_DIRSEL_SHIFT) 239 // Select the endpoint direction as IN. 240 #define SI32_USBEP_A_EPCONTROL_DIRSEL_IN_VALUE 1 241 #define SI32_USBEP_A_EPCONTROL_DIRSEL_IN_U32 \ 242 (SI32_USBEP_A_EPCONTROL_DIRSEL_IN_VALUE << SI32_USBEP_A_EPCONTROL_DIRSEL_SHIFT) 243 244 #define SI32_USBEP_A_EPCONTROL_IISOEN_MASK 0x00004000 245 #define SI32_USBEP_A_EPCONTROL_IISOEN_SHIFT 14 246 // Configure the endpoint for Bulk/Interrupt transfers. 247 #define SI32_USBEP_A_EPCONTROL_IISOEN_BULK_INT_VALUE 0 248 #define SI32_USBEP_A_EPCONTROL_IISOEN_BULK_INT_U32 \ 249 (SI32_USBEP_A_EPCONTROL_IISOEN_BULK_INT_VALUE << SI32_USBEP_A_EPCONTROL_IISOEN_SHIFT) 250 // Configure the endpoint for Isochronous transfers. 251 #define SI32_USBEP_A_EPCONTROL_IISOEN_ISO_VALUE 1 252 #define SI32_USBEP_A_EPCONTROL_IISOEN_ISO_U32 \ 253 (SI32_USBEP_A_EPCONTROL_IISOEN_ISO_VALUE << SI32_USBEP_A_EPCONTROL_IISOEN_SHIFT) 254 255 #define SI32_USBEP_A_EPCONTROL_AUTOSETEN_MASK 0x00008000 256 #define SI32_USBEP_A_EPCONTROL_AUTOSETEN_SHIFT 15 257 // The IPRDYI bit is not automatically set by hardware. 258 #define SI32_USBEP_A_EPCONTROL_AUTOSETEN_DISABLED_VALUE 0 259 #define SI32_USBEP_A_EPCONTROL_AUTOSETEN_DISABLED_U32 \ 260 (SI32_USBEP_A_EPCONTROL_AUTOSETEN_DISABLED_VALUE << SI32_USBEP_A_EPCONTROL_AUTOSETEN_SHIFT) 261 // The IPRDYI bit is automatically set by hardware. 262 #define SI32_USBEP_A_EPCONTROL_AUTOSETEN_ENABLED_VALUE 1 263 #define SI32_USBEP_A_EPCONTROL_AUTOSETEN_ENABLED_U32 \ 264 (SI32_USBEP_A_EPCONTROL_AUTOSETEN_ENABLED_VALUE << SI32_USBEP_A_EPCONTROL_AUTOSETEN_SHIFT) 265 266 #define SI32_USBEP_A_EPCONTROL_OPRDYI_MASK 0x00010000 267 #define SI32_USBEP_A_EPCONTROL_OPRDYI_SHIFT 16 268 // A data packet is not available. 269 #define SI32_USBEP_A_EPCONTROL_OPRDYI_NOT_SET_VALUE 0 270 #define SI32_USBEP_A_EPCONTROL_OPRDYI_NOT_SET_U32 \ 271 (SI32_USBEP_A_EPCONTROL_OPRDYI_NOT_SET_VALUE << SI32_USBEP_A_EPCONTROL_OPRDYI_SHIFT) 272 // A data packet is available. 273 #define SI32_USBEP_A_EPCONTROL_OPRDYI_SET_VALUE 1 274 #define SI32_USBEP_A_EPCONTROL_OPRDYI_SET_U32 \ 275 (SI32_USBEP_A_EPCONTROL_OPRDYI_SET_VALUE << SI32_USBEP_A_EPCONTROL_OPRDYI_SHIFT) 276 277 #define SI32_USBEP_A_EPCONTROL_OFIFOFF_MASK 0x00020000 278 #define SI32_USBEP_A_EPCONTROL_OFIFOFF_SHIFT 17 279 // The OUT endpoint FIFO is not full. 280 #define SI32_USBEP_A_EPCONTROL_OFIFOFF_NOT_SET_VALUE 0 281 #define SI32_USBEP_A_EPCONTROL_OFIFOFF_NOT_SET_U32 \ 282 (SI32_USBEP_A_EPCONTROL_OFIFOFF_NOT_SET_VALUE << SI32_USBEP_A_EPCONTROL_OFIFOFF_SHIFT) 283 // The OUT endpoint FIFO is full. 284 #define SI32_USBEP_A_EPCONTROL_OFIFOFF_SET_VALUE 1 285 #define SI32_USBEP_A_EPCONTROL_OFIFOFF_SET_U32 \ 286 (SI32_USBEP_A_EPCONTROL_OFIFOFF_SET_VALUE << SI32_USBEP_A_EPCONTROL_OFIFOFF_SHIFT) 287 288 #define SI32_USBEP_A_EPCONTROL_OORF_MASK 0x00040000 289 #define SI32_USBEP_A_EPCONTROL_OORF_SHIFT 18 290 // No data overrun. 291 #define SI32_USBEP_A_EPCONTROL_OORF_NOT_SET_VALUE 0 292 #define SI32_USBEP_A_EPCONTROL_OORF_NOT_SET_U32 \ 293 (SI32_USBEP_A_EPCONTROL_OORF_NOT_SET_VALUE << SI32_USBEP_A_EPCONTROL_OORF_SHIFT) 294 // A data packet was lost because of a full FIFO since this flag was last cleared. 295 #define SI32_USBEP_A_EPCONTROL_OORF_SET_VALUE 1 296 #define SI32_USBEP_A_EPCONTROL_OORF_SET_U32 \ 297 (SI32_USBEP_A_EPCONTROL_OORF_SET_VALUE << SI32_USBEP_A_EPCONTROL_OORF_SHIFT) 298 299 #define SI32_USBEP_A_EPCONTROL_ODERRF_MASK 0x00080000 300 #define SI32_USBEP_A_EPCONTROL_ODERRF_SHIFT 19 301 // A CRC or bit-stuff error has not occurred. 302 #define SI32_USBEP_A_EPCONTROL_ODERRF_NOT_SET_VALUE 0 303 #define SI32_USBEP_A_EPCONTROL_ODERRF_NOT_SET_U32 \ 304 (SI32_USBEP_A_EPCONTROL_ODERRF_NOT_SET_VALUE << SI32_USBEP_A_EPCONTROL_ODERRF_SHIFT) 305 // A CRC or bit-stuff error occurred. 306 #define SI32_USBEP_A_EPCONTROL_ODERRF_SET_VALUE 1 307 #define SI32_USBEP_A_EPCONTROL_ODERRF_SET_U32 \ 308 (SI32_USBEP_A_EPCONTROL_ODERRF_SET_VALUE << SI32_USBEP_A_EPCONTROL_ODERRF_SHIFT) 309 310 #define SI32_USBEP_A_EPCONTROL_OFIFOFL_MASK 0x00100000 311 #define SI32_USBEP_A_EPCONTROL_OFIFOFL_SHIFT 20 312 // Flush the OUT FIFO. 313 #define SI32_USBEP_A_EPCONTROL_OFIFOFL_SET_VALUE 1 314 #define SI32_USBEP_A_EPCONTROL_OFIFOFL_SET_U32 \ 315 (SI32_USBEP_A_EPCONTROL_OFIFOFL_SET_VALUE << SI32_USBEP_A_EPCONTROL_OFIFOFL_SHIFT) 316 317 #define SI32_USBEP_A_EPCONTROL_OSDSTL_MASK 0x00200000 318 #define SI32_USBEP_A_EPCONTROL_OSDSTL_SHIFT 21 319 // Stop sending a stall. 320 #define SI32_USBEP_A_EPCONTROL_OSDSTL_STOP_VALUE 0 321 #define SI32_USBEP_A_EPCONTROL_OSDSTL_STOP_U32 \ 322 (SI32_USBEP_A_EPCONTROL_OSDSTL_STOP_VALUE << SI32_USBEP_A_EPCONTROL_OSDSTL_SHIFT) 323 // Generate a stall. 324 #define SI32_USBEP_A_EPCONTROL_OSDSTL_SEND_VALUE 1 325 #define SI32_USBEP_A_EPCONTROL_OSDSTL_SEND_U32 \ 326 (SI32_USBEP_A_EPCONTROL_OSDSTL_SEND_VALUE << SI32_USBEP_A_EPCONTROL_OSDSTL_SHIFT) 327 328 #define SI32_USBEP_A_EPCONTROL_OSTSTLI_MASK 0x00400000 329 #define SI32_USBEP_A_EPCONTROL_OSTSTLI_SHIFT 22 330 // Read: A stall condition has not been sent since this bit was last cleared. 331 // Write: Clear the interrupt. 332 #define SI32_USBEP_A_EPCONTROL_OSTSTLI_NOT_SET_VALUE 0 333 #define SI32_USBEP_A_EPCONTROL_OSTSTLI_NOT_SET_U32 \ 334 (SI32_USBEP_A_EPCONTROL_OSTSTLI_NOT_SET_VALUE << SI32_USBEP_A_EPCONTROL_OSTSTLI_SHIFT) 335 // Read: A stall condition has been sent since this bit was last cleared. Write: No 336 // effect. 337 #define SI32_USBEP_A_EPCONTROL_OSTSTLI_SET_VALUE 1 338 #define SI32_USBEP_A_EPCONTROL_OSTSTLI_SET_U32 \ 339 (SI32_USBEP_A_EPCONTROL_OSTSTLI_SET_VALUE << SI32_USBEP_A_EPCONTROL_OSTSTLI_SHIFT) 340 341 #define SI32_USBEP_A_EPCONTROL_OCLRDT_MASK 0x00800000 342 #define SI32_USBEP_A_EPCONTROL_OCLRDT_SHIFT 23 343 // Do not reset the OUT data toggle. 344 #define SI32_USBEP_A_EPCONTROL_OCLRDT_NO_RESET_VALUE 0 345 #define SI32_USBEP_A_EPCONTROL_OCLRDT_NO_RESET_U32 \ 346 (SI32_USBEP_A_EPCONTROL_OCLRDT_NO_RESET_VALUE << SI32_USBEP_A_EPCONTROL_OCLRDT_SHIFT) 347 // Reset the OUT data toggle. 348 #define SI32_USBEP_A_EPCONTROL_OCLRDT_RESET_VALUE 1 349 #define SI32_USBEP_A_EPCONTROL_OCLRDT_RESET_U32 \ 350 (SI32_USBEP_A_EPCONTROL_OCLRDT_RESET_VALUE << SI32_USBEP_A_EPCONTROL_OCLRDT_SHIFT) 351 352 #define SI32_USBEP_A_EPCONTROL_ODMAMD_MASK 0x10000000 353 #define SI32_USBEP_A_EPCONTROL_ODMAMD_SHIFT 28 354 // Automatic DMA service is requested on the last packet of the transfer until less 355 // than four bytes remain in the packet. At this time, an interrupt is generated. 356 // The firmware must read or write the last few bytes of the packet, if any remain. 357 #define SI32_USBEP_A_EPCONTROL_ODMAMD_AUTO_DMA_VALUE 0 358 #define SI32_USBEP_A_EPCONTROL_ODMAMD_AUTO_DMA_U32 \ 359 (SI32_USBEP_A_EPCONTROL_ODMAMD_AUTO_DMA_VALUE << SI32_USBEP_A_EPCONTROL_ODMAMD_SHIFT) 360 // No DMA service is requested on the last packet of the transfer. When the DMA 361 // recognizes the last packet, an interrupt is generated. The firmware must handle 362 // the entirety of the last packet. 363 #define SI32_USBEP_A_EPCONTROL_ODMAMD_NO_DMA_VALUE 1 364 #define SI32_USBEP_A_EPCONTROL_ODMAMD_NO_DMA_U32 \ 365 (SI32_USBEP_A_EPCONTROL_ODMAMD_NO_DMA_VALUE << SI32_USBEP_A_EPCONTROL_ODMAMD_SHIFT) 366 367 #define SI32_USBEP_A_EPCONTROL_ODMAEN_MASK 0x20000000 368 #define SI32_USBEP_A_EPCONTROL_ODMAEN_SHIFT 29 369 // Disable the DMA request for the OUT endpoint. 370 #define SI32_USBEP_A_EPCONTROL_ODMAEN_DISABLED_VALUE 0 371 #define SI32_USBEP_A_EPCONTROL_ODMAEN_DISABLED_U32 \ 372 (SI32_USBEP_A_EPCONTROL_ODMAEN_DISABLED_VALUE << SI32_USBEP_A_EPCONTROL_ODMAEN_SHIFT) 373 // Enable the DMA request for the OUT endpoint. 374 #define SI32_USBEP_A_EPCONTROL_ODMAEN_ENABLED_VALUE 1 375 #define SI32_USBEP_A_EPCONTROL_ODMAEN_ENABLED_U32 \ 376 (SI32_USBEP_A_EPCONTROL_ODMAEN_ENABLED_VALUE << SI32_USBEP_A_EPCONTROL_ODMAEN_SHIFT) 377 378 #define SI32_USBEP_A_EPCONTROL_OISOEN_MASK 0x40000000 379 #define SI32_USBEP_A_EPCONTROL_OISOEN_SHIFT 30 380 // Configure the endpoint for Bulk/Interrupt transfers. 381 #define SI32_USBEP_A_EPCONTROL_OISOEN_BULK_INT_VALUE 0 382 #define SI32_USBEP_A_EPCONTROL_OISOEN_BULK_INT_U32 \ 383 (SI32_USBEP_A_EPCONTROL_OISOEN_BULK_INT_VALUE << SI32_USBEP_A_EPCONTROL_OISOEN_SHIFT) 384 // Configure the endpoint for Isochronous transfers. 385 #define SI32_USBEP_A_EPCONTROL_OISOEN_ISO_VALUE 1 386 #define SI32_USBEP_A_EPCONTROL_OISOEN_ISO_U32 \ 387 (SI32_USBEP_A_EPCONTROL_OISOEN_ISO_VALUE << SI32_USBEP_A_EPCONTROL_OISOEN_SHIFT) 388 389 #define SI32_USBEP_A_EPCONTROL_AUTOCLREN_MASK 0x80000000 390 #define SI32_USBEP_A_EPCONTROL_AUTOCLREN_SHIFT 31 391 // The OPRDYI bit is not automatically cleared by hardware. 392 #define SI32_USBEP_A_EPCONTROL_AUTOCLREN_DISABLED_VALUE 0U 393 #define SI32_USBEP_A_EPCONTROL_AUTOCLREN_DISABLED_U32 \ 394 (SI32_USBEP_A_EPCONTROL_AUTOCLREN_DISABLED_VALUE << SI32_USBEP_A_EPCONTROL_AUTOCLREN_SHIFT) 395 // The OPRDYI bit is automatically cleared by hardware. 396 #define SI32_USBEP_A_EPCONTROL_AUTOCLREN_ENABLED_VALUE 1U 397 #define SI32_USBEP_A_EPCONTROL_AUTOCLREN_ENABLED_U32 \ 398 (SI32_USBEP_A_EPCONTROL_AUTOCLREN_ENABLED_VALUE << SI32_USBEP_A_EPCONTROL_AUTOCLREN_SHIFT) 399 400 401 402 struct SI32_USBEP_A_EPCOUNT_Struct 403 { 404 union 405 { 406 struct 407 { 408 // Endpoint OUT Data Count 409 volatile uint32_t COUNT: 10; 410 uint32_t reserved0: 22; 411 }; 412 volatile uint32_t U32; 413 }; 414 }; 415 416 #define SI32_USBEP_A_EPCOUNT_COUNT_MASK 0x000003FF 417 #define SI32_USBEP_A_EPCOUNT_COUNT_SHIFT 0 418 419 420 421 struct SI32_USBEP_A_EPFIFO_Struct 422 { 423 union 424 { 425 // This is a FIFO register 426 volatile uint8_t U8; 427 volatile uint16_t U16; 428 volatile uint32_t U32; 429 }; 430 }; 431 432 #define SI32_USBEP_A_EPFIFO_FIFO_MASK 0xFFFFFFFF 433 #define SI32_USBEP_A_EPFIFO_FIFO_SHIFT 0 434 435 436 437 typedef struct SI32_USBEP_A_Struct 438 { 439 struct SI32_USBEP_A_EPMPSIZE_Struct EPMPSIZE ; // Base Address + 0x0 440 uint32_t reserved0; 441 uint32_t reserved1; 442 uint32_t reserved2; 443 struct SI32_USBEP_A_EPCONTROL_Struct EPCONTROL ; // Base Address + 0x10 444 uint32_t reserved3; 445 uint32_t reserved4; 446 uint32_t reserved5; 447 struct SI32_USBEP_A_EPCOUNT_Struct EPCOUNT ; // Base Address + 0x20 448 uint32_t reserved6; 449 uint32_t reserved7; 450 uint32_t reserved8; 451 struct SI32_USBEP_A_EPFIFO_Struct EPFIFO ; // Base Address + 0x30 452 uint32_t reserved9; 453 uint32_t reserved10; 454 uint32_t reserved11; 455 } SI32_USBEP_A_Type; 456 457 #ifdef __cplusplus 458 } 459 #endif 460 461 #endif // __SI32_USBEP_A_REGISTERS_H__ 462 463 //-eof-------------------------------------------------------------------------- 464 465
