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Searched refs:ICACHE0_BASE (Results 1 – 25 of 118) sorted by relevance

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/hal_silabs-latest/simplicity_sdk/platform/service/device_manager/devices/
Dsl_device_peripheral_hal_efr32xg22.c152 #if defined(ICACHE0_BASE)
154 const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = ICACHE0_BASE,
Dsl_device_peripheral_hal_efr32xg21.c159 #if defined(ICACHE0_BASE)
161 const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = ICACHE0_BASE,
Dsl_device_peripheral_hal_efr32xg27.c166 #if defined(ICACHE0_BASE)
168 const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = ICACHE0_BASE,
Dsl_device_peripheral_hal_efr32xg29.c173 #if defined(ICACHE0_BASE)
175 const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = ICACHE0_BASE,
Dsl_device_peripheral_hal_efr32xg24.c187 #if defined(ICACHE0_BASE)
189 const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = ICACHE0_BASE,
Dsl_device_peripheral_hal_efr32xg23.c194 #if defined(ICACHE0_BASE)
196 const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = ICACHE0_BASE,
Dsl_device_peripheral_hal_efr32xg28.c194 #if defined(ICACHE0_BASE)
196 const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = ICACHE0_BASE,
Dsl_device_peripheral_hal_efr32xg25.c222 #if defined(ICACHE0_BASE)
224 const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = ICACHE0_BASE,
Dsl_device_peripheral_hal_efr32xg26.c229 #if defined(ICACHE0_BASE)
231 const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = ICACHE0_BASE,
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h606 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
608 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
868 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base …
Defr32mg21a010f512im32.h606 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
608 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
868 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base …
Defr32mg21a010f768im32.h606 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
608 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
868 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base …
Defr32mg21a020f1024im32.h608 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
610 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
870 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base …
Defr32mg21a020f512im32.h608 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
610 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
870 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base …
Defr32mg21a020f768im32.h608 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
610 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
870 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base …
Defr32mg21b010f1024im32.h606 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
608 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
868 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base …
Defr32mg21b010f512im32.h606 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
608 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
868 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base …
Defr32mg21b010f768im32.h606 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
608 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
868 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base …
Defr32mg21b020f1024im32.h608 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
610 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
870 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base …
Defr32mg21b020f512im32.h608 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
610 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
870 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base …
Defr32mg21b020f768im32.h608 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
610 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
870 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base …
Drm21z000f1024im32.h604 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
606 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
866 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base …
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c224f512gn32.h628 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
630 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
897 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICAC…
Defr32bg22c224f512im32.h628 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
630 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
897 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICAC…
Defr32bg22e224f512im40.h642 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ macro
644 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ macro
911 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICAC…

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