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Searched refs:HFXO0_BASE (Results 1 – 25 of 124) sorted by relevance

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/hal_silabs-latest/gecko/emlib/inc/
Dem_chip.h315 *(volatile uint32_t*)(HFXO0_BASE + 0x34U) = in CHIP_Init()
316 (*(volatile uint32_t*)(HFXO0_BASE + 0x34U) & 0xFF8000FFU) in CHIP_Init()
319 *(volatile uint32_t*)(HFXO0_BASE + 0x30U) = in CHIP_Init()
320 (*(volatile uint32_t*)(HFXO0_BASE + 0x30U) & 0xFFFF0FFFU) in CHIP_Init()
323 *(volatile uint32_t*)(HFXO0_BASE + 0x30U) |= 0x700; in CHIP_Init()
405 *(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) = in CHIP_Init()
406 (*(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) & 0xE3FFFFFFUL) in CHIP_Init()
/hal_silabs-latest/simplicity_sdk/platform/emlib/inc/
Dem_chip.h319 *(volatile uint32_t*)(HFXO0_BASE + 0x34U) = in CHIP_Init()
320 (*(volatile uint32_t*)(HFXO0_BASE + 0x34U) & 0xFF8000FFU) in CHIP_Init()
323 *(volatile uint32_t*)(HFXO0_BASE + 0x30U) = in CHIP_Init()
324 (*(volatile uint32_t*)(HFXO0_BASE + 0x30U) & 0xFFFF0FFFU) in CHIP_Init()
327 *(volatile uint32_t*)(HFXO0_BASE + 0x30U) |= 0x700; in CHIP_Init()
409 *(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) = in CHIP_Init()
410 (*(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) & 0xE3FFFFFFUL) in CHIP_Init()
/hal_silabs-latest/simplicity_sdk/platform/service/device_manager/devices/
Dsl_device_peripheral_hal_efr32xg22.c124 #if defined(HFXO0_BASE)
126 const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = HFXO0_BASE,
Dsl_device_peripheral_hal_efr32xg21.c131 #if defined(HFXO0_BASE)
133 const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = HFXO0_BASE,
Dsl_device_peripheral_hal_efr32xg27.c138 #if defined(HFXO0_BASE)
140 const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = HFXO0_BASE,
Dsl_device_peripheral_hal_efr32xg29.c145 #if defined(HFXO0_BASE)
147 const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = HFXO0_BASE,
Dsl_device_peripheral_hal_efr32xg24.c152 #if defined(HFXO0_BASE)
154 const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = HFXO0_BASE,
Dsl_device_peripheral_hal_efr32xg23.c159 #if defined(HFXO0_BASE)
161 const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = HFXO0_BASE,
Dsl_device_peripheral_hal_efr32xg28.c159 #if defined(HFXO0_BASE)
161 const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = HFXO0_BASE,
Dsl_device_peripheral_hal_efr32xg25.c187 #if defined(HFXO0_BASE)
189 const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = HFXO0_BASE,
Dsl_device_peripheral_hal_efr32xg26.c180 #if defined(HFXO0_BASE)
182 const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = HFXO0_BASE,
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h566 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
568 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
860 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po…
Defr32mg21a010f512im32.h566 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
568 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
860 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po…
Defr32mg21a010f768im32.h566 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
568 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
860 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po…
Defr32mg21a020f1024im32.h568 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
570 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
862 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po…
Defr32mg21a020f512im32.h568 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
570 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
862 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po…
Defr32mg21a020f768im32.h568 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
570 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
862 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po…
Defr32mg21b010f1024im32.h566 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
568 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
860 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po…
Defr32mg21b010f512im32.h566 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
568 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
860 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po…
Defr32mg21b010f768im32.h566 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
568 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
860 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po…
Defr32mg21b020f1024im32.h568 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
570 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
862 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po…
Defr32mg21b020f512im32.h568 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
570 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
862 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po…
Defr32mg21b020f768im32.h568 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
570 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
862 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po…
Drm21z000f1024im32.h564 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
566 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
858 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po…
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c224f512gn32.h588 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ macro
590 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ macro
889 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO…

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