1 /****************************************************************************** 2 * @file sl_si91x_gpio.h 3 ******************************************************************************* 4 * # License 5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b> 6 ******************************************************************************* 7 * 8 * SPDX-License-Identifier: Zlib 9 * 10 * The licensor of this software is Silicon Laboratories Inc. 11 * 12 * This software is provided 'as-is', without any express or implied 13 * warranty. In no event will the authors be held liable for any damages 14 * arising from the use of this software. 15 * 16 * Permission is granted to anyone to use this software for any purpose, 17 * including commercial applications, and to alter it and redistribute it 18 * freely, subject to the following restrictions: 19 * 20 * 1. The origin of this software must not be misrepresented; you must not 21 * claim that you wrote the original software. If you use this software 22 * in a product, an acknowledgment in the product documentation would be 23 * appreciated but is not required. 24 * 2. Altered source versions must be plainly marked as such, and must not be 25 * misrepresented as being the original software. 26 * 3. This notice may not be removed or altered from any source distribution. 27 * 28 ******************************************************************************/ 29 #ifndef SL_SI91X_GPIO_PERIPHERAL_H 30 #define SL_SI91X_GPIO_PERIPHERAL_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 //// Includes 37 #include "sl_si91x_gpio_common.h" 38 39 /******************************************************************************* 40 ******************************** ENUMS ************************************ 41 ******************************************************************************/ 42 ///@brief NPSS GPIO PIN MUX 43 typedef enum { 44 NPSS_GPIO_PIN_MUX_MODE0, ///< NPSS Pin MUX Mode 0 45 NPSS_GPIO_PIN_MUX_MODE1, ///< NPSS Pin MUX Mode 1 46 NPSS_GPIO_PIN_MUX_MODE2, ///< NPSS Pin MUX Mode 2 47 NPSS_GPIO_PIN_MUX_MODE3, ///< NPSS Pin MUX Mode 3 48 NPSS_GPIO_PIN_MUX_MODE4, ///< NPSS Pin MUX Mode 4 49 NPSS_GPIO_PIN_MUX_MODE5, ///< NPSS Pin MUX Mode 5 50 NPSS_GPIO_PIN_MUX_MODE6, ///< NPSS Pin MUX Mode 6 51 NPSS_GPIO_PIN_MUX_MODE7, ///< NPSS Pin MUX Mode 7 52 NPSS_GPIO_PIN_MUX_MODE8, ///< NPSS Pin MUX Mode 8 53 NPSS_GPIO_PIN_MUX_MODE9, ///< NPSS Pin MUX Mode 9 54 NPSS_GPIO_PIN_MUX_MODE10, ///< NPSS Pin MUX Mode 10 55 } sl_si91x_uulp_npss_mode_t; 56 57 ///@brief GPIO group interrupts 58 typedef enum { 59 GROUP_INT_1 = 0, ///< GPIO group interrupt 1 60 GROUP_INT_2 = 1, ///< GPIO group interrupt 2 61 } sl_si91x_group_interrupt_t; 62 63 ///@brief GPIO Interrupt Configurations. 64 typedef enum { 65 SL_GPIO_INTERRUPT_LEVEL_HIGH = (1 << 0), ///< interrupt when pin level is '1' 66 SL_GPIO_INTERRUPT_LEVEL_LOW = (1 << 1), ///< interrupt when pin level is '0' 67 SL_GPIO_INTERRUPT_RISE_EDGE = (1 << 2), ///< interrupt when rising edge is detected 68 SL_GPIO_INTERRUPT_FALL_EDGE = (1 << 3), ///< interrupt when falling edge is detected 69 } sl_si91x_gpio_interrupt_config_flag_t; 70 71 ///@brief GPIO driver disable state 72 typedef enum { 73 GPIO_HZ = 0, ///< 0 for Hi-impedance (P1=0,P2=0) 74 GPIO_PULLUP, ///< 1 for Pull up (P1=0,P2=1) 75 GPIO_PULLDOWN, ///< 2 for Pull down(P1=1,P2=0) 76 GPIO_REPEATER ///< 3 for Repeater (P1=1,P2=1) 77 } sl_si91x_gpio_driver_disable_state_t; 78 79 ///@brief GPIO driver strength select 80 typedef enum { 81 GPIO_TWO_MILLI_AMPS = 0, ///< 0 for two_milli_amps (E1=0,E2=0) 82 GPIO_FOUR_MILLI_AMPS, ///< 1 for four_milli_amps (E1=0,E2=1) 83 GPIO_EIGHT_MILLI_AMPS, ///< 2 for eight_milli_amps (E1=1,E2=0) 84 GPIO_TWELVE_MILLI_AMPS ///< 3 for twelve_milli_amps(E1=1,E2=1) 85 } sl_si91x_gpio_driver_strength_select_t; 86 87 ///@brief HP/ULP GPIO clock select 88 typedef enum { 89 M4CLK_GPIO = 0, ///< 0 for HP GPIO clock 90 ULPCLK_GPIO = 1 ///< 1 for ULP GPIO clock 91 } sl_si91x_gpio_select_clock_t; 92 93 ///@brief Direction of the GPIO pin enum 94 typedef enum { 95 GPIO_OUTPUT = 0, ///< GPIO direction output 96 GPIO_INPUT = 1, ///< GPIO direction input 97 } sl_si91x_gpio_direction_t; 98 99 ///@brief UULP GPIO PAD select enum 100 typedef enum { 101 GPIO_PAD_M4 = 0, ///< GPIO M4 PAD selection 102 GPIO_PAD_TA = 1, ///< GPIO NWP PAD selection 103 } sl_si91x_gpio_uulp_pad_t; 104 105 ///@brief AND/OR of the GPIO group interrupt 106 typedef enum { 107 GPIO_AND = 0, ///< GPIO AND group interrupt 108 GPIO_OR = 1, ///< GPIO OR group interrupt 109 } sl_si91x_gpio_and_or_t; 110 111 ///@brief GPIO group interrupt wakeup flag 112 typedef enum { 113 GPIO_FLAG_DS = 0, ///< wakeup flag disable 114 GPIO_FLAG_EN = 1, ///< wakeup flag enable 115 } sl_si91x_gpio_wakeup_t; 116 117 ///@brief GPIO polarity enum 118 typedef enum { 119 GPIO_POLARITY_0 = 0, ///< GPIO polarity 0 120 GPIO_POLARITY_1 = 1, ///< GPIO polarity 1 121 } sl_si91x_gpio_polarity_t; 122 123 ///@brief GPIO level edge select 124 typedef enum { 125 GPIO_LEVEL = 0, ///< GPIO level trigger 126 GPIO_EDGE = 1, ///< GPIO edge trigger 127 } sl_si91x_gpio_level_edge_t; 128 129 ///@brief GPIO slew rate select 130 typedef enum { 131 GPIO_SR_LOW = 0, ///< GPIO slew rate low 132 GPIO_SR_HIGH = 1, ///< GPIO slew rate high 133 } sl_si91x_gpio_slew_rate_t; 134 135 ///@brief GPIO pin set/clear 136 typedef enum { 137 GPIO_PIN_CLEAR = 0, ///< GPIO clear pin 138 GPIO_PIN_SET = 1, ///< GPIO set pin 139 } sl_si91x_gpio_pin_value_t; 140 141 ///@brief NPSS GPIO input buffer 142 typedef enum { 143 GPIO_RECEIVER_DS = 0, ///< receiver disable 144 GPIO_RECEIVER_EN = 1, ///< receiver enable 145 } sl_si91x_gpio_receiver_t; 146 147 ///@brief UULP GPIO PAD configuration register fields 148 typedef struct { 149 uint8_t gpio_padnum; ///< UULP GPIO pin number 150 sl_si91x_uulp_npss_mode_t mode; ///< UULP GPIO mode 151 sl_si91x_gpio_receiver_t receiver; ///< UULP GPIO PAD receiver 152 sl_si91x_gpio_direction_t direction; ///< UULP GPIO direction of PAD 153 sl_si91x_gpio_pin_value_t output; ///< UULP GPIO value driven on PAD 154 sl_si91x_gpio_uulp_pad_t pad_select; ///< UULP GPIO PAD selection 155 sl_si91x_gpio_polarity_t polarity; ///< UULP GPIO Polarity 156 } uulp_pad_config_t; 157 158 ///@brief GPIO Group Interrupt Configuration. It selects random ports and pins. 159 typedef struct { 160 sl_si91x_group_interrupt_t grp_interrupt; ///< configure group interrupt 161 uint8_t grp_interrupt_cnt; ///< Count of group interrupt pins 162 uint8_t grp_interrupt_port[MAX_GPIO_PIN_INT]; ///< ports used for group interrupts 163 uint8_t grp_interrupt_pin[MAX_GPIO_PIN_INT]; ///< pins used for group interrupts 164 uint8_t grp_interrupt_pol[MAX_GPIO_PIN_INT]; ///< polarity used for interrupts 165 sl_si91x_gpio_level_edge_t level_edge; ///< configure level or edge trigger 166 sl_si91x_gpio_and_or_t and_or; ///< AND/OR ing of interrupts 167 } sl_si91x_gpio_group_interrupt_config_t; 168 169 ///@brief GPIO pin numbers 170 typedef enum { 171 GPIO_PIN_NUMBER0 = 0, ///< GPIO pin number 0 172 GPIO_PIN_NUMBER1 = 1, ///< GPIO pin number 1 173 GPIO_PIN_NUMBER2 = 2, ///< GPIO pin number 2 174 GPIO_PIN_NUMBER3 = 3, ///< GPIO pin number 3 175 GPIO_PIN_NUMBER4 = 4, ///< GPIO pin number 4 176 GPIO_PIN_NUMBER5 = 5, ///< GPIO pin number 5 177 GPIO_PIN_NUMBER6 = 6, ///< GPIO pin number 6 178 GPIO_PIN_NUMBER7 = 7, ///< GPIO pin number 7 179 GPIO_PIN_NUMBER8 = 8, ///< GPIO pin number 8 180 GPIO_PIN_NUMBER9 = 9, ///< GPIO pin number 9 181 GPIO_PIN_NUMBER10 = 10, ///< GPIO pin number 10 182 GPIO_PIN_NUMBER11 = 11, ///< GPIO pin number 11 183 GPIO_PIN_NUMBER12 = 12, ///< GPIO pin number 12 184 GPIO_PIN_NUMBER13 = 13, ///< GPIO pin number 13 185 GPIO_PIN_NUMBER14 = 14, ///< GPIO pin number 14 186 GPIO_PIN_NUMBER15 = 15, ///< GPIO pin number 15 187 } sl_si91x_gpio_pin_t; 188 189 ///@brief GPIO ULP pin numbers 190 typedef enum { 191 ULP_GPIO_PIN_0 = 0, ///< ULP GPIO pin number 0 192 ULP_GPIO_PIN_1 = 1, ///< ULP GPIO pin number 1 193 ULP_GPIO_PIN_2 = 2, ///< ULP GPIO pin number 2 194 ULP_GPIO_PIN_3 = 3, ///< ULP GPIO pin number 3 195 ULP_GPIO_PIN_4 = 4, ///< ULP GPIO pin number 4 196 ULP_GPIO_PIN_5 = 5, ///< ULP GPIO pin number 5 197 ULP_GPIO_PIN_6 = 6, ///< ULP GPIO pin number 6 198 ULP_GPIO_PIN_7 = 7, ///< ULP GPIO pin number 7 199 ULP_GPIO_PIN_8 = 8, ///< ULP GPIO pin number 8 200 ULP_GPIO_PIN_9 = 9, ///< ULP GPIO pin number 9 201 ULP_GPIO_PIN_10 = 10, ///< ULP GPIO pin number 10 202 ULP_GPIO_PIN_11 = 11, ///< ULP GPIO pin number 11 203 } sl_si91x_gpio_pin_ulp_t; 204 205 ///@brief GPIO instances 206 typedef enum { 207 M4_GPIO_INSTANCE = 1, ///< 1 for HP GPIO 208 ULP_GPIO_INSTANCE = 2, ///< 2 for ULP GPIO 209 UULP_GPIO_INSTANCE = 3, ///< 3 for UULP GPIO 210 GPIO_INSTANCE_LAST, ///< Last enum for validating 211 } sl_si91x_gpio_instances_t; 212 213 ///@brief GPIO interrupt type 214 typedef enum { 215 GPIO_PIN_INTERRUPT, ///< 0 for GPIO pin interrupt 216 GPIO_GROUP_INTERRUPT, ///< 1 for GPIO group interrupt 217 } sl_si91x_gpio_intr_t; 218 219 /// @brief Structure to hold the versions of peripheral API 220 typedef struct { 221 uint8_t release; ///< Release version number 222 uint8_t major; ///< SQA version number 223 uint8_t minor; ///< Development version number 224 } sl_si91x_gpio_version_t; 225 226 /// @brief UULP GPIO pin/interrupt number 227 typedef enum { 228 UULP_GPIO_INTERRUPT_0 = 0, /// UULP GPIO 0 pin/interrupt number 229 UULP_GPIO_INTERRUPT_1 = 1, /// UULP GPIO 1 pin/interrupt number 230 UULP_GPIO_INTERRUPT_2 = 2, /// UULP GPIO 2 pin/interrupt number 231 UULP_GPIO_INTERRUPT_3 = 3, /// UULP GPIO 3 pin/interrupt number 232 UULP_GPIO_INTERRUPT_4 = 4, /// UULP GPIO 4 pin/interrupt number 233 } sl_si91x_uulp_gpio_interrupt_t; 234 235 /// @brief UULP GPIO interrupt bit position 236 typedef enum { 237 UULP_GPIO_INTERRUPT_0_BIT = BIT(0), /// UULP GPIO 0 interrupt bit position 238 UULP_GPIO_INTERRUPT_1_BIT = BIT(1), /// UULP GPIO 1 interrupt bit position 239 UULP_GPIO_INTERRUPT_2_BIT = BIT(2), /// UULP GPIO 2 interrupt bit position 240 UULP_GPIO_INTERRUPT_3_BIT = BIT(3), /// UULP GPIO 3 interrupt bit position 241 UULP_GPIO_INTERRUPT_4_BIT = BIT(4), /// UULP GPIO 4 interrupt bit position 242 } sl_si91x_uulp_gpio_interrupt_bit_t; 243 244 // ----------------------------------------------------------------------------- 245 // Prototypes 246 /***************************************************************************/ /** 247 * @brief Set the direction for a GPIO pin from the selected port. 248 * @pre \ref sl_si91x_gpio_enable_clock() \n 249 * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n 250 * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n 251 * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n 252 * Use corresponding pad receiver API for corresponding GPIO instance. 253 * @param[in] port - The port to associate with the pin. 254 * HP instance - PORT 0,1,2,3 255 * ULP instance - PORT 4 256 * @param[in] pin - The pin number on the port. 257 * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. 258 * Port 3 has 9 pins. 259 * ULP instance has total 12 pins. 260 * @param[in] direction - pin direction of type \ref sl_si91x_gpio_direction_t 261 * '0' - Output\n 262 * '1' - Input\n 263 * @return None 264 *******************************************************************************/ 265 void sl_si91x_gpio_set_pin_direction(uint8_t port, uint8_t pin, sl_si91x_gpio_direction_t direction); 266 267 /***************************************************************************/ /** 268 * @brief Get the direction of a GPIO pin from selected port. 269 * @pre \ref sl_si91x_gpio_enable_clock() \n 270 * \ref sl_si91x_gpio_enable_pad_selection, for HP instance \n 271 * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n 272 * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n 273 * Use corresponding pad receiver API for corresponding GPIO instance. \n 274 * \ref sl_si91x_gpio_set_pin_direction() \n 275 * \ref sl_si91x_gpio_get_pin_direction() \n 276 * @param[in] port - The port to associate with the pin. 277 * HP instance - PORT 0,1,2,3 278 * ULP instance - PORT 4 279 * @param[in] pin - The pin number on the port. 280 * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. 281 * Port 3 has 9 pins. 282 * ULP instance has total 12 pins. 283 * @return Returns the direction of the pin. 284 * '0' - Output\n 285 * '1' - Input\n 286 ******************************************************************************/ 287 uint8_t sl_si91x_gpio_get_pin_direction(uint8_t port, uint8_t pin); 288 289 /***************************************************************************/ /** 290 * @brief Enable the receiver enable bit in the PAD configuration register. 291 * @pre \ref sl_si91x_gpio_enable_clock() \n 292 * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n 293 * @param[in] gpio_num - GPIO pin number to be use. 294 * @return None 295 *******************************************************************************/ 296 void sl_si91x_gpio_enable_pad_receiver(uint8_t gpio_num); 297 298 /***************************************************************************/ /** 299 * @brief Disable the receiver enable bit in the PAD configuration register. 300 * @pre \ref sl_si91x_gpio_enable_clock() \n 301 * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n 302 * @param[in] gpio_num - GPIO pin number to be use. 303 * @return None 304 *******************************************************************************/ 305 void sl_si91x_gpio_disable_pad_receiver(uint8_t gpio_num); 306 307 /***************************************************************************/ /** 308 * @brief Select the pad enable for HP instance of GPIO pins 309 * @pre \ref sl_si91x_gpio_enable_clock() \n 310 * @param[in] gpio_padnum - PAD number to be use(0 to 21). 311 * @return None 312 *******************************************************************************/ 313 void sl_si91x_gpio_enable_pad_selection(uint8_t gpio_padnum); 314 315 /***************************************************************************/ /** 316 * @brief Select the host pad enable for HP instance of GPIO pins 317 * @pre \ref sl_si91x_gpio_enable_clock() \n 318 * @param[in] gpio_num - GPIO pin number(25 to 30). 319 * @return None 320 *******************************************************************************/ 321 void sl_si91x_gpio_enable_host_pad_selection(uint8_t gpio_num); 322 323 /***************************************************************************/ /** 324 * @brief Select drive strength of a GPIO pin for selected port. 325 * @pre \ref sl_si91x_gpio_enable_clock() \n 326 * \ref sl_si91x_gpio_enable_pad_selection() \n 327 * \ref sl_si91x_gpio_enable_pad_receiver() \n 328 * @param[in] gpio_num - GPIO pin number to be use 329 * @param[in] strength - Drive strength selector(E1,E2) of type 330 * \ref sl_si91x_gpio_driver_strength_select_t 331 * possible values are 332 * 0, for two_milli_amps (E1=0,E2=0)\n 333 * 1, for four_milli_amps (E1=0,E2=1)\n 334 * 2, for eight_milli_amps (E1=1,E2=0)\n 335 * 3, for twelve_milli_amps(E1=1,E2=1)\n 336 * @return None 337 ******************************************************************************/ 338 void sl_si91x_gpio_select_pad_driver_strength(uint8_t gpio_num, sl_si91x_gpio_driver_strength_select_t strength); 339 340 /***************************************************************************/ /** 341 * @brief Select the Driver disabled state control of a HP instance GPIO pin. 342 * @pre \ref sl_si91x_gpio_enable_clock() \n 343 * \ref sl_si91x_gpio_enable_pad_selection() \n 344 * \ref sl_si91x_gpio_enable_pad_receiver() \n 345 * @param[in] gpio_num - GPIO pin number to be use 346 * @param[in] disable_state - driver disable state of type 347 * \ref sl_si91x_gpio_driver_disable_state_t 348 * possible values are 349 * 0, for HiZ (P1=0,P2=0)\n 350 * 1, for Pull-up (P1=0,P2=1)\n 351 * 2, for Pull-down (P1=1,P2=0)\n 352 * 3, for Repeater (P1=1,P2=1)\n 353 * @return None 354 ******************************************************************************/ 355 void sl_si91x_gpio_select_pad_driver_disable_state(uint8_t gpio_num, 356 sl_si91x_gpio_driver_disable_state_t disable_state); 357 358 /***************************************************************************/ /** 359 * @brief Select AND/OR of the group interrupt. If multiple interrupts 360 * on same port (or) different are to be generated, then use this API. 361 * Example: Consider port 0: pin 2,3 and port 3: pin 1,2 for interrupt generation. 362 * Choose OR, any of the selected pin is fine for group interrupt generation 363 * Choose AND, all the selected pins are necessary for group interrupt generation 364 * @pre \ref sl_si91x_gpio_enable_clock() \n 365 * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n 366 * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n 367 * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n 368 * Use corresponding pad receiver API for corresponding GPIO instance. 369 * \ref sl_gpio_set_pin_mode() \n 370 * \ref sl_si91x_gpio_set_pin_direction() \n 371 * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n 372 * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n 373 * Use corresponding group interrupt configuration API for corresponding GPIO instance. 374 * @param[in] port - The port to associate with the pin. 375 * HP instance - PORT 0,1,2,3 376 * ULP instance - PORT 4 377 * @param[in] group_interrupt - Group interrupt number of type 378 * \ref sl_si91x_group_interrupt_t 379 * @param[in] and_or - AND/OR of GPIO group interrupts of type 380 * \ref sl_si91x_gpio_and_or_t 381 * '0' - AND\n 382 * '1' - OR\n 383 * @return None 384 *******************************************************************************/ 385 void sl_si91x_gpio_select_group_interrupt_and_or(uint8_t port, 386 sl_si91x_group_interrupt_t group_interrupt, 387 sl_si91x_gpio_and_or_t and_or); 388 389 /***************************************************************************/ /** 390 * @brief Clear the selected group interrupt status for HP instance GPIO pins. 391 * @pre \ref sl_si91x_gpio_enable_clock() \n 392 * \ref sl_si91x_gpio_enable_pad_selection() \n 393 * \ref sl_si91x_gpio_enable_pad_receiver() \n 394 * \ref sl_gpio_set_pin_mode() \n 395 * \ref sl_si91x_gpio_set_pin_direction() \n 396 * \ref sl_si91x_gpio_configure_group_interrupt() \n 397 * @param[in] group_interrupt - Group interrupt number of type 398 * \ref sl_si91x_group_interrupt_t 399 * @return None 400 *******************************************************************************/ 401 void sl_si91x_gpio_clear_group_interrupt(sl_si91x_group_interrupt_t group_interrupt); 402 403 /***************************************************************************/ /** 404 * @brief Get the group interrupt status of selected instance. 405 * @pre \ref sl_si91x_gpio_enable_clock() \n 406 * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n 407 * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n 408 * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n 409 * Use corresponding pad receiver API for corresponding GPIO instance. \n 410 * \ref sl_gpio_set_pin_mode(), 411 * \ref sl_si91x_gpio_set_pin_direction() \n 412 * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n 413 * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n 414 * Use corresponding group interrupt configuration API for corresponding GPIO instance. 415 * @param[in] port - The port to associate with the pin. 416 * HP instance - PORT 0,1,2,3 417 * ULP instance - PORT 4 418 * @param[in] group_interrupt - Group interrupt number of type 419 * \ref sl_si91x_group_interrupt_t 420 * @return returns the group interrupt status register 421 * 1, when interrupt is enabled\n 422 * 0, when interrupt is disabled\n 423 ******************************************************************************/ 424 uint32_t sl_si91x_gpio_get_group_interrupt_status(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); 425 426 /***************************************************************************/ /** 427 * @brief Configure the group interrupt as a wake up source across sleep wakeups. 428 * @param[in] port - The port to associate with the pin. 429 * HP instance - PORT 0,1,2,3 430 * ULP instance - PORT 4 431 * @param[in] group_interrupt - Group interrupt number of type 432 * \ref sl_si91x_group_interrupt_t 433 * @param[in] flags - GPIO group interrupt wake up flag of type 434 * \ref sl_si91x_gpio_wakeup_t 435 * '1' - enable\n 436 * '0' - disable\n 437 * @return None 438 ******************************************************************************/ 439 void sl_si91x_gpio_select_group_interrupt_wakeup(uint8_t port, 440 sl_si91x_group_interrupt_t group_interrupt, 441 sl_si91x_gpio_wakeup_t flags); 442 443 /***************************************************************************/ /** 444 * @brief Configure the MCU HP instance group interrupts with trigger type(level/edge), polarity(high/low),interrupt type(and/or) 445 * and register the callback function for interrupts. 446 * @pre \ref sl_si91x_gpio_enable_clock() \n 447 * \ref sl_si91x_gpio_enable_pad_selection() \n 448 * \ref sl_si91x_gpio_enable_pad_receiver() \n 449 * \ref sl_gpio_set_pin_mode() \n 450 * \ref sl_si91x_gpio_set_pin_direction() \n 451 * @param[in] configuration - configuration pointer to 452 * \ref sl_si91x_gpio_group_interrupt_config_t structure 453 * @return None 454 *******************************************************************************/ 455 void sl_si91x_gpio_configure_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration); 456 457 /***************************************************************************/ /** 458 * @brief Get the polarity of selected group interrupt of a HP instance GPIO. 459 * @pre \ref sl_si91x_gpio_enable_clock() \n 460 * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n 461 * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n 462 * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n 463 * Use corresponding pad receiver API for corresponding GPIO instance. \n 464 * \ref sl_gpio_set_pin_mode() \n 465 * \ref sl_si91x_gpio_set_pin_direction() \n 466 * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n 467 * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n 468 * Use corresponding group interrupt configuration API for corresponding GPIO instance. 469 * @param[in] group_interrupt - GPIO group interrupt number of type 470 * \ref sl_si91x_group_interrupt_t 471 * @param[in] port - The port to associate with the pin. 472 * HP instance - PORT 0,1,2,3 473 * ULP instance - PORT 4 474 * @param[in] pin - The pin number on the port. 475 * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. 476 * Port 3 has 9 pins. 477 * ULP instance has total 12 pins. 478 * @return returns group interrupt polarity 479 * 1, when GPIO pin status is '1'\n 480 * 0, when GPIO pin status is '0'\n 481 ******************************************************************************/ 482 uint8_t sl_si91x_gpio_get_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, 483 uint8_t port, 484 uint8_t pin); 485 486 /***************************************************************************/ /** 487 * @brief Configure the polarity of selected group interrupt for HP instance GPIO . 488 * @pre \ref sl_si91x_gpio_enable_clock() \n 489 * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n 490 * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n 491 * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n 492 * Use corresponding pad receiver API for corresponding GPIO instance. \n 493 * \ref sl_gpio_set_pin_mode() \n 494 * \ref sl_si91x_gpio_set_pin_direction() \n 495 * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n 496 * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n 497 * Use corresponding group interrupt configuration API for corresponding GPIO instance. 498 * @param[in] group_interrupt - GPIO group interrupt number of type 499 * \ref sl_si91x_group_interrupt_t 500 * @param[in] port - The port to associate with the pin. 501 * HP instance - PORT 0,1,2,3 502 * ULP instance - PORT 4 503 * @param[in] pin - The pin number on the port. 504 * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. 505 * Port 3 has 9 pins. 506 * ULP instance has total 12 pins. 507 * @param[in] polarity - polarity of GPIO group interrupt of type 508 * \ref sl_si91x_gpio_polarity_t 509 * 1, group interrupt gets generated when GPIO pin status is '1'\n 510 * 0, group interrupt gets generated when GPIO pin status is '0'\n 511 * @return None 512 ******************************************************************************/ 513 void sl_si91x_gpio_set_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, 514 uint8_t port, 515 uint8_t pin, 516 sl_si91x_gpio_polarity_t polarity); 517 518 /***************************************************************************/ /** 519 * @brief Get the level/edge event status of selected group interrupt. 520 * @pre \ref sl_si91x_gpio_enable_clock() \n 521 * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n 522 * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n 523 * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n 524 * Use corresponding pad receiver API for corresponding GPIO instance. \n 525 * \ref sl_gpio_set_pin_mode(), \n 526 * \ref sl_si91x_gpio_set_pin_direction(), \n 527 * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n 528 * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n 529 * Use corresponding group interrupt configuration API for corresponding GPIO instance. 530 * @param[in] port - The port to associate with the pin. 531 * HP instance - PORT 0,1,2,3 532 * ULP instance - PORT 4 533 * @param[in] group_interrupt - GPIO group interrupt number of type 534 * \ref sl_si91x_group_interrupt_t 535 * @return returns group interrupt level_edge 536 * 1, for Edge\n 537 * 0, for Level\n 538 ******************************************************************************/ 539 uint8_t sl_si91x_gpio_get_group_interrupt_level_edge(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); 540 541 /***************************************************************************/ /** 542 * @brief Set the level/edge event of group interrupt. 543 * @pre \ref sl_si91x_gpio_enable_clock() \n 544 * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n 545 * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n 546 * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n 547 * Use corresponding pad receiver API for corresponding GPIO instance. \n 548 * \ref sl_gpio_set_pin_mode() \n 549 * \ref sl_si91x_gpio_set_pin_direction() \n 550 * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n 551 * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n 552 * Use corresponding group interrupt configuration API for corresponding GPIO instance. 553 * @param[in] port - The port to associate with the pin. 554 * HP instance - PORT 0,1,2,3 555 * ULP instance - PORT 4 556 * @param[in] group_interrupt - GPIO group interrupt number of type 557 * \ref sl_si91x_group_interrupt_t 558 * @param[in] level_edge - GPIO level edge group interrupt of type 559 * \ref sl_si91x_gpio_level_edge_t 560 * 1, for Edge\n 561 * 0, for Level\n 562 * @return None 563 ******************************************************************************/ 564 void sl_si91x_gpio_set_group_interrupt_level_edge(uint8_t port, 565 sl_si91x_group_interrupt_t group_interrupt, 566 sl_si91x_gpio_level_edge_t level_edge); 567 568 /***************************************************************************/ /** 569 * @brief Unmask the selected group interrupt to enable interrupt clearing upon generation. 570 * @pre \ref sl_si91x_gpio_enable_clock() \n 571 * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n 572 * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n 573 * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n 574 * Use corresponding pad receiver API for corresponding GPIO instance. \n 575 * \ref sl_gpio_set_pin_mode() \n 576 * \ref sl_si91x_gpio_set_pin_direction() \n 577 * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n 578 * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n 579 * Use corresponding group interrupt configuration API for corresponding GPIO instance. 580 * @param[in] port - The port to associate with the pin. 581 * HP instance - PORT 0,1,2,3 582 * ULP instance - PORT 4 583 * @param[in] group_interrupt - GPIO group interrupt number of type 584 * \ref sl_si91x_group_interrupt_t 585 * @return None 586 *******************************************************************************/ 587 void sl_si91x_gpio_unmask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); 588 589 /***************************************************************************/ /** 590 * @brief Mask the selected group interrupts. 591 * @pre \ref sl_si91x_gpio_enable_clock() \n 592 * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n 593 * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n 594 * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n 595 * Use corresponding pad receiver API for corresponding GPIO instance. \n 596 * \ref sl_gpio_set_pin_mode() \n 597 * \ref sl_si91x_gpio_set_pin_direction() \n 598 * @param[in] port - The port to associate with the pin. 599 * HP instance - PORT 0,1,2,3 600 * ULP instance - PORT 4 601 * @param[in] group_interrupt - GPIO group interrupt number of type 602 * \ref sl_si91x_group_interrupt_t 603 * @return None 604 *******************************************************************************/ 605 void sl_si91x_gpio_mask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); 606 607 /***************************************************************************/ /** 608 * @brief Disable the clock for either HP or ULP instance of GPIO Peripheral. 609 * @param[in] clock - Selects M4 clock or ULP clock of type 610 * \ref sl_si91x_gpio_select_clock_t 611 * 0, for M4 GPIO CLK\n 612 * 1, for ULP GPIO CLK\n 613 * @return None 614 ******************************************************************************/ 615 void sl_si91x_gpio_disable_clock(sl_si91x_gpio_select_clock_t clock); 616 617 /***************************************************************************/ /** 618 * @brief Enable the clock for either HP or ULP instance of GPIO peripheral. 619 * @param[in] clock - Selects M4 clock or ULP clock of type 620 * \ref sl_si91x_gpio_select_clock_t 621 * 0, for M4 GPIO CLK\n 622 * 1, for ULP GPIO CLK\n 623 * @return None 624 ******************************************************************************/ 625 void sl_si91x_gpio_enable_clock(sl_si91x_gpio_select_clock_t clock); 626 627 /***************************************************************************/ /** 628 * @brief Enable the selected group interrupts for either HP or ULP instance of GPIO peripheral. 629 * @pre \ref sl_si91x_gpio_enable_clock() \n 630 * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n 631 * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n 632 * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n 633 * Use corresponding pad receiver API for corresponding GPIO instance. \n 634 * \ref sl_gpio_set_pin_mode() \n 635 * \ref sl_si91x_gpio_set_pin_direction() \n 636 * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n 637 * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n 638 * Use corresponding group interrupt configuration API for corresponding GPIO instance. 639 * @param[in] group_interrupt - GPIO group interrupt number of type 640 * \ref sl_si91x_group_interrupt_t 641 * @param[in] port - The port to associate with the pin. 642 * HP instance - PORT 0,1,2,3 643 * ULP instance - PORT 4 644 * @param[in] pin - The pin number on the port. 645 * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. 646 * Port 3 has 9 pins. 647 * ULP instance has total 12 pins. 648 * @return None 649 *******************************************************************************/ 650 void sl_si91x_gpio_enable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, uint8_t port, uint8_t pin); 651 652 /***************************************************************************/ /** 653 * @brief Disable the selected group interrupts for either HP or ULP instance of GPIO peripheral. 654 * @pre \ref sl_si91x_gpio_enable_clock() \n 655 * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n 656 * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n 657 * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n 658 * Use corresponding pad receiver API for corresponding GPIO instance. \n 659 * \ref sl_gpio_set_pin_mode() \n 660 * \ref sl_si91x_gpio_set_pin_direction() \n 661 * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n 662 * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n 663 * Use corresponding group interrupt configuration API for corresponding GPIO instance. 664 * @param[in] group_interrupt - GPIO group interrupt number of type 665 * \ref sl_si91x_group_interrupt_t 666 * @param[in] port - The port to associate with the pin. 667 * HP instance - PORT 0,1,2,3 668 * ULP instance - PORT 4 669 * @param[in] pin - The pin number on the port. 670 * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. 671 * Port 3 has 9 pins. 672 * ULP instance has total 12 pins. 673 * 674 * @return None 675 *******************************************************************************/ 676 void sl_si91x_gpio_disable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, uint8_t port, uint8_t pin); 677 678 /***************************************************************************/ /** 679 * @brief Select the slew rate for the ULP instance of GPIO peripheral. 680 * @pre \ref sl_si91x_gpio_enable_clock() \n 681 * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n 682 * @param[in] gpio_num - GPIO pin number to be use 683 * @param[in] slew_rate - slew rate of type \ref sl_si91x_gpio_slew_rate_t 684 * '0' - Slow\n 685 * '1' - Fast\n 686 * @return None 687 ******************************************************************************/ 688 void sl_si91x_gpio_select_ulp_pad_slew_rate(uint8_t gpio_num, sl_si91x_gpio_slew_rate_t slew_rate); 689 690 /***************************************************************************/ /** 691 * @brief Select the drive strength for the ULP instance of GPIO peripheral. 692 * @pre \ref sl_si91x_gpio_enable_clock() \n 693 * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n 694 * @param[in] gpio_num - GPIO pin number to be use 695 * @param[in] strength - Drive strength selector(E1,E2) of type 696 * \ref sl_si91x_gpio_driver_strength_select_t 697 * 0, for two_milli_amps (E1=0,E2=0)\n 698 * 1, for four_milli_amps (E1=0,E2=1)\n 699 * 2, for eight_milli_amps (E1=1,E2=0)\n 700 * 3, for twelve_milli_amps(E1=1,E2=1)\n 701 * @return None 702 ******************************************************************************/ 703 void sl_si91x_gpio_select_ulp_pad_driver_strength(uint8_t gpio_num, sl_si91x_gpio_driver_strength_select_t strength); 704 705 /***************************************************************************/ /** 706 * @brief Select the driver-disabled state control for the ULP instance of GPIO peripheral. 707 * @pre \ref sl_si91x_gpio_enable_clock() \n 708 * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n 709 * @param[in] gpio_num - GPIO pin number to be use 710 * @param[in] disable_state - driver disable state of type 711 * \ref sl_si91x_gpio_driver_disable_state_t 712 * 0, for HiZ (P1=0,P2=0)\n 713 * 1, for Pull up (P1=0,P2=1)\n 714 * 2, for Pull down (P1=1,P2=0)\n 715 * 3, for Repeater (P1=1,P2=1)\n 716 * @return None 717 ******************************************************************************/ 718 void sl_si91x_gpio_select_ulp_pad_driver_disable_state(uint8_t gpio_num, 719 sl_si91x_gpio_driver_disable_state_t disable_state); 720 721 /***************************************************************************/ /** 722 * @brief Disable the receiver enable bit for the ULP instance of GPIO peripheral. 723 * @pre \ref sl_si91x_gpio_enable_clock() \n 724 * @param[in] gpio_num - GPIO pin number to be used 725 * @return None 726 *******************************************************************************/ 727 void sl_si91x_gpio_disable_ulp_pad_receiver(uint32_t gpio_num); 728 729 /***************************************************************************/ /** 730 * @brief Enable the receiver enable bit for the ULP instance of GPIO peripheral. 731 * @pre \ref sl_si91x_gpio_enable_clock() \n 732 * @param[in] gpio_num - GPIO pin number to be used 733 * @return None 734 *******************************************************************************/ 735 void sl_si91x_gpio_enable_ulp_pad_receiver(uint8_t gpio_num); 736 737 /***************************************************************************/ /** 738 * @brief Configure the MCU ULP instance pin interrupts with trigger type(level/edge) 739 * and register the callback function for interrupts. 740 * @pre \ref sl_si91x_gpio_enable_clock() \n 741 * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n 742 * \ref sl_gpio_set_pin_mode() \n 743 * \ref sl_si91x_gpio_set_pin_direction() \n 744 * @param[in] interrupt_no - The interrupt number to trigger. 745 * @param[in] flags - Interrupt configuration flags of type 746 * \ref sl_si91x_gpio_interrupt_config_flag_t 747 * @param[in] pin - GPIO pin number 748 * @return None 749 *******************************************************************************/ 750 void sl_si91x_gpio_configure_ulp_pin_interrupt(uint8_t interrupt_no, 751 sl_si91x_gpio_interrupt_config_flag_t flags, 752 sl_si91x_gpio_pin_ulp_t pin); 753 754 /***************************************************************************/ /** 755 * @brief Set the NPSS GPIO pin MUX(mode) to selected mode. 756 * @pre \ref sl_si91x_gpio_enable_clock() \n 757 * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n 758 * @param[in] pin - NPSS GPIO pin number(0 to 4) of type 759 * \ref sl_si91x_uulp_npss_mode_t 760 * @param[in] mode - NPSS GPIO MUX value 761 * @return none 762 *******************************************************************************/ 763 void sl_si91x_gpio_set_uulp_npss_pin_mux(uint8_t pin, sl_si91x_uulp_npss_mode_t mode); 764 765 /***************************************************************************/ /** 766 * @brief Enable/disable the NPSS GPIO Input Buffer. 767 * @pre \ref sl_si91x_gpio_enable_clock() \n 768 * @param[in] pin - is NPSS GPIO pin number (0 to 4) 769 * @param[in] receiver - is enable/disable NPSS GPIO receiver of type 770 * \ref sl_si91x_gpio_receiver_t 771 * '1' - Enable\n 772 * '0' - Disable\n 773 * @return None 774 ******************************************************************************/ 775 void sl_si91x_gpio_select_uulp_npss_receiver(uint8_t pin, sl_si91x_gpio_receiver_t receiver); 776 777 /***************************************************************************/ /** 778 * @brief Set the direction for the selected NPSS GPIO. 779 * @pre \ref sl_si91x_gpio_enable_clock() \n 780 * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n 781 * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n 782 * @param[in] pin - is NPSS GPIO pin number (0 to 4) 783 * @param[in] direction - is direction value (Input / Output) of type 784 * \ref sl_si91x_gpio_direction_t 785 * '1' - Input Direction\n 786 * '0' - Output Direction\n 787 * @return None 788 ******************************************************************************/ 789 void sl_si91x_gpio_set_uulp_npss_direction(uint8_t pin, sl_si91x_gpio_direction_t direction); 790 791 /***************************************************************************/ /** 792 * @brief Get the direction of the selected NPSS GPIO. 793 * @pre \ref sl_si91x_gpio_enable_clock() \n 794 * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n 795 * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n 796 * \ref sl_si91x_gpio_set_uulp_npss_direction() \n 797 * @param[in] pin - is NPSS GPIO pin number(0...4) 798 * @return returns the GPIO pin direction 799 * - 1, Input Direction 800 * - 0, Output Direction 801 *******************************************************************************/ 802 uint8_t sl_si91x_gpio_get_uulp_npss_direction(uint8_t pin); 803 804 /***************************************************************************/ /** 805 * @brief Control(set or clear) the NPSS GPIO pin value. 806 * @pre \ref sl_si91x_gpio_enable_clock() \n 807 * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n 808 * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n 809 * \ref sl_si91x_gpio_set_uulp_npss_direction() \n 810 * @param[in] pin - is NPSS GPIO pin number (0...4) of type 811 * \ref sl_si91x_gpio_pin_value_t 812 * @param[in] pin_value - is NPSS GPIO pin value 813 * '1' - SET \n 814 * '0' - CLEAR \n 815 * @return None 816 ******************************************************************************/ 817 void sl_si91x_gpio_set_uulp_npss_pin_value(uint8_t pin, sl_si91x_gpio_pin_value_t pin_value); 818 819 /***************************************************************************/ /** 820 * @brief Read the status of selected NPSS GPIO pin value. 821 * @pre \ref sl_si91x_gpio_enable_clock() \n 822 * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n 823 * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n 824 * \ref sl_si91x_gpio_set_uulp_npss_direction() \n 825 * \ref sl_si91x_gpio_set_uulp_npss_pin_value() \n 826 * @param[in] pin - is NPSS GPIO pin number (0 to 4) 827 * @return returns the pin logical state of pin 828 * '0' - LOW \n 829 * '1' - HIGH \n 830 ******************************************************************************/ 831 uint8_t sl_si91x_gpio_get_uulp_npss_pin(uint8_t pin); 832 833 /***************************************************************************/ /** 834 * @brief Select the NPSS GPIO polarity for generating interrupt. 835 * @pre \ref sl_si91x_gpio_enable_clock() \n 836 * @param[in] pin - is NPSS GPIO pin number (0 to 4) 837 * @param[in] polarity - GPIO polarity 838 * \ref sl_si91x_gpio_polarity_t 839 * '1' - High\n 840 * '0' - Low\n 841 * @return None 842 ******************************************************************************/ 843 void sl_si91x_gpio_select_uulp_npss_polarity(uint8_t pin, sl_si91x_gpio_polarity_t polarity); 844 845 /***************************************************************************/ /** 846 * @brief Set the NPSS GPIO interrupt as a wake up source across sleep wakeups. 847 * @pre \ref sl_si91x_gpio_enable_clock() \n 848 * @param[in] npssgpio_interrupt - NPSS GPIO pin number (0 to 4) 849 * \ref sl_si91x_uulp_gpio_interrupt_t 850 * @return none 851 *******************************************************************************/ 852 void sl_si91x_gpio_set_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt); 853 854 /***************************************************************************/ /** 855 * @brief Clear the UULP NPSS GPIO Interrupt as wake up source. 856 * @pre \ref sl_si91x_gpio_enable_clock() \n 857 * @param[in] npssgpio_interrupt - NPSS GPIO pin number (0 to 4) 858 * \ref sl_si91x_uulp_gpio_interrupt_t 859 * @return none 860 *******************************************************************************/ 861 void sl_si91x_gpio_clear_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt); 862 863 /***************************************************************************/ /** 864 * @brief Mask the selected NPSS GPIO interrupt. 865 * @pre \ref sl_si91x_gpio_enable_clock() \n 866 * \ref sl_si91x_gpio_set_uulp_pad_configuration() \n 867 * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n 868 * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n 869 * \ref sl_si91x_gpio_set_uulp_npss_direction() \n 870 * @param[in] npssgpio_interrupt - Bit position of the NPSS GPIO interrupt to be masked 871 * \ref sl_si91x_uulp_gpio_interrupt_bit_t 872 * @return none 873 *******************************************************************************/ 874 void sl_si91x_gpio_mask_uulp_npss_interrupt(uint8_t npssgpio_interrupt); 875 876 /***************************************************************************/ /** 877 * @brief Unmask the selected NPSS GPIO interrupt. 878 * @pre \ref sl_si91x_gpio_enable_clock() \n 879 * \ref sl_si91x_gpio_set_uulp_pad_configuration() \n 880 * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n 881 * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n 882 * \ref sl_si91x_gpio_set_uulp_npss_direction() \n 883 * @param[in] npssgpio_interrupt - Bit position of the NPSS GPIO interrupt to be unmasked 884 * \ref sl_si91x_uulp_gpio_interrupt_bit_t 885 * @return none 886 *******************************************************************************/ 887 void sl_si91x_gpio_unmask_uulp_npss_interrupt(uint8_t npssgpio_interrupt); 888 889 /***************************************************************************/ /** 890 * @brief Clear the selected NPSS GPIO interrupt. 891 * @pre \ref sl_si91x_gpio_enable_clock() \n 892 * \ref sl_si91x_gpio_set_uulp_pad_configuration() \n 893 * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n 894 * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n 895 * \ref sl_si91x_gpio_set_uulp_npss_direction() \n 896 * \ref sl_si91x_gpio_configure_uulp_interrupt() \n 897 * @param[in] npssgpio_interrupt - Bit position of the NPSS GPIO interrupt to be cleared 898 * \ref sl_si91x_uulp_gpio_interrupt_bit_t 899 * @return none 900 *******************************************************************************/ 901 void sl_si91x_gpio_clear_uulp_interrupt(uint8_t npssgpio_interrupt); 902 903 /***************************************************************************/ /** 904 * @brief Get the current status of all the NPSS GPIO interrupt status. 905 * @pre \ref sl_si91x_gpio_enable_clock() \n 906 * \ref sl_si91x_gpio_set_uulp_pad_configuration() \n 907 * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n 908 * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n 909 * \ref sl_si91x_gpio_set_uulp_npss_direction() \n 910 * \ref sl_si91x_gpio_configure_uulp_interrupt() \n 911 * @param[in] None 912 * @return returns the UULP INTR status. 913 * 1, interrupt has been raised\n 914 * 0, interrupt is masked or not raised\n 915 ******************************************************************************/ 916 uint8_t sl_si91x_gpio_get_uulp_interrupt_status(void); 917 918 /***************************************************************************/ /** 919 * @brief Get the selected ULP instance GPIO pin interrupt status. 920 * @pre \ref sl_si91x_gpio_enable_clock() \n 921 * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n 922 * \ref sl_gpio_set_pin_mode() \n 923 * \ref sl_si91x_gpio_set_pin_direction() \n 924 * \ref sl_si91x_gpio_configure_ulp_pin_interrupt() \n 925 * @param[in] flags : ULP GPIO interrupt sources. 926 * @return returns the ULP INTR status. 927 * 1, interrupt has been raised\n 928 * 0, interrupt is masked or not raised\n 929 ******************************************************************************/ 930 uint32_t sl_si91x_gpio_get_ulp_interrupt_status(uint32_t flags); 931 932 /***************************************************************************/ /** 933 * @brief Clear the selected ULP instance GPIO pin interrupts. 934 * @pre \ref sl_si91x_gpio_enable_clock() \n 935 * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n 936 * \ref sl_gpio_set_pin_mode() \n 937 * \ref sl_si91x_gpio_set_pin_direction() \n 938 * \ref sl_si91x_gpio_configure_ulp_pin_interrupt() \n 939 * @param[in] flags : ULP GPIO interrupt sources to clear. 940 * @return None 941 *******************************************************************************/ 942 void sl_si91x_gpio_clear_ulp_interrupt(uint32_t flags); 943 944 /***************************************************************************/ /** 945 * @brief Clear the selected ULP instance group interrupt. 946 * @pre \ref sl_si91x_gpio_enable_clock() \n 947 * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n 948 * \ref sl_gpio_set_pin_mode() \n 949 * \ref sl_si91x_gpio_set_pin_direction() \n 950 * \ref sl_si91x_gpio_configure_ulp_group_interrupt() \n 951 * Use corresponding group interrupt configuration API for corresponding GPIO instance. 952 * @param[in] group_interrupt - Group interrupt number of type 953 * \ref sl_si91x_group_interrupt_t 954 * @return None 955 *******************************************************************************/ 956 void sl_si91x_gpio_clear_ulp_group_interrupt(sl_si91x_group_interrupt_t group_interrupt); 957 958 /***************************************************************************/ /** 959 * @brief Configure the UULP GPIO pin interrupt with interrupt type level or edge and registers callback function for interrupts. 960 * @pre \ref sl_si91x_gpio_enable_clock() \n 961 * \ref sl_si91x_gpio_set_uulp_pad_configuration() \n 962 * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n 963 * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n 964 * \ref sl_si91x_gpio_set_uulp_npss_direction() \n 965 * @param[in] flags - Interrupt configuration flags of type 966 * \ref sl_si91x_gpio_interrupt_config_flag_t 967 * @param[in] npssgpio_interrupt - NPSS GPIO pin number(0 to 4) 968 * \ref sl_si91x_uulp_gpio_interrupt_t 969 * @return None 970 *******************************************************************************/ 971 void sl_si91x_gpio_configure_uulp_interrupt(sl_si91x_gpio_interrupt_config_flag_t flags, uint8_t npssgpio_interrupt); 972 973 /***************************************************************************/ /** 974 * @brief Configure the MCU ULP instance group interrupts with trigger type(level/edge), polarity(high/low),interrupt type(and/or) 975 * and register the callback function for interrupts. 976 * @pre \ref sl_si91x_gpio_enable_clock() \n 977 * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n 978 * \ref sl_gpio_set_pin_mode() \n 979 * \ref sl_si91x_gpio_set_pin_direction() \n 980 * @param[in] configuration - configuration pointer to 981 * \ref sl_si91x_gpio_group_interrupt_config_t structure 982 * @return None 983 *******************************************************************************/ 984 void sl_si91x_gpio_configure_ulp_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration); 985 986 /***************************************************************************/ /** 987 * @brief Verify assumptions and print message if the assumption is false. 988 * @param[in] file - File name 989 * @param[in] line - Line number 990 * @return None 991 ******************************************************************************/ 992 void sl_assert_failed(uint8_t *file, uint32_t line); 993 994 /***************************************************************************/ /** 995 * Toggle the selected UULP pin status. 996 * @pre \ref sl_si91x_gpio_enable_clock() \n 997 * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n 998 * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n 999 * \ref sl_si91x_gpio_set_uulp_npss_direction() \n 1000 * @param[in] pin - UULP pin number to toggle 1001 * @return None 1002 ******************************************************************************/ 1003 void sl_si91x_gpio_toggle_uulp_npss_pin(uint8_t pin); 1004 1005 /***************************************************************************/ /** 1006 * @brief Indicate UULP GPIO PAD configuration. 1007 * @pre \ref sl_si91x_gpio_enable_clock() \n 1008 * @param[in] pad_config : PAD configuration pointer to \ref uulp_pad_config_t structure 1009 * @return None 1010 *******************************************************************************/ 1011 void sl_si91x_gpio_set_uulp_pad_configuration(uulp_pad_config_t *pad_config); 1012 1013 /***************************************************************************/ /** 1014 * @brief Get the release, SQA, and development version numbers of the GPIO peripheral. 1015 * @param[in] None 1016 * @return returns structure of type \ref sl_si91x_gpio_version_t 1017 *******************************************************************************/ 1018 sl_si91x_gpio_version_t sl_si91x_gpio_get_version(void); 1019 1020 /** @} (end addtogroup GPIO) */ 1021 1022 #ifdef __cplusplus 1023 } 1024 #endif 1025 1026 #endif ///< SL_SI91X_GPIO_PERIPHERAL_H 1027 /**************************************************************************************************/ 1028
