Home
last modified time | relevance | path

Searched refs:FclkSource (Results 1 – 4 of 4) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_ulpss_clk.c619 ULP_VAD_FCLK_SELECT_T FclkSource, in ulpss_vad_clk_config() argument
624 || FclkSource > ULP_VAD_FCLK_MAX_SEL) { in ulpss_vad_clk_config()
649 switch (FclkSource) { in ulpss_vad_clk_config()
652 pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; in ulpss_vad_clk_config()
658 pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; in ulpss_vad_clk_config()
664 pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; in ulpss_vad_clk_config()
669 pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; in ulpss_vad_clk_config()
673 pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; in ulpss_vad_clk_config()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/
Drsi_rom_ulpss_clk.h532 ULP_VAD_FCLK_SELECT_T FclkSource, in RSI_ULPSS_VadClkConfig() argument
536 return ROMAPI_ULPSS_CLK_API->ulpss_vad_clk_config(pULPCLK, clkSource, FclkSource, divFactor); in RSI_ULPSS_VadClkConfig()
538 return ulpss_vad_clk_config(pULPCLK, clkSource, FclkSource, divFactor); in RSI_ULPSS_VadClkConfig()
667 ULP_VAD_FCLK_SELECT_T FclkSource,
Drsi_rom_table_si91x.h808 ULP_VAD_FCLK_SELECT_T FclkSource,
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/
Drsi_ulpss_clk.h346 ULP_VAD_FCLK_SELECT_T FclkSource,