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Searched refs:EMU_PWRCTRL_REGPWRSEL_DVDD (Results 1 – 25 of 73) sorted by relevance

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/hal_silabs-latest/gecko/emlib/src/
Dem_emu.c2814 EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; in EMU_DCDCInit()
2963 EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_IMMEDIATEPWRSWITCH; in EMU_DCDCPowerOff()
2964 #elif defined(EMU_PWRCTRL_REGPWRSEL_DVDD) in EMU_DCDCPowerOff()
2965 EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; in EMU_DCDCPowerOff()
Dem_cmu.c11272 EFM_ASSERT((EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD) != 0UL); in CMU_OscillatorEnable()
/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_emu.c2869 EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; in EMU_DCDCInit()
3018 EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_IMMEDIATEPWRSWITCH; in EMU_DCDCPowerOff()
3019 #elif defined(EMU_PWRCTRL_REGPWRSEL_DVDD) in EMU_DCDCPowerOff()
3020 EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; in EMU_DCDCPowerOff()
Dem_cmu.c11325 EFM_ASSERT((EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD) != 0UL); in CMU_OscillatorEnable()
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_emu.h801 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_emu.h784 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_emu.h801 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_emu.h784 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_emu.h801 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_emu.h912 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b390f1024gl112.h2988 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b390f512gl112.h2988 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b530f512il120.h3827 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b530f512im64.h3827 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b530f512iq100.h3827 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b530f512iq64.h3827 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b530f512gq100.h3827 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b530f512gq64.h3827 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b530f512il112.h3827 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b110f1024gm64.h3819 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b110f1024gq64.h3819 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b530f512gl112.h3827 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b530f512gl120.h3827 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
Defm32gg12b530f512gm64.h3827 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_emu.h920 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) … macro

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