1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG21 EMU register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG21_EMU_H 31 #define EFR32MG21_EMU_H 32 #define EMU_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG21_EMU EMU 40 * @{ 41 * @brief EFR32MG21 EMU Register Declaration. 42 *****************************************************************************/ 43 44 /** EMU Register Declaration. */ 45 typedef struct emu_typedef{ 46 uint32_t RESERVED0[4U]; /**< Reserved for future use */ 47 __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ 48 uint32_t RESERVED1[3U]; /**< Reserved for future use */ 49 __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ 50 uint32_t RESERVED2[15U]; /**< Reserved for future use */ 51 __IOM uint32_t LOCK; /**< EMU Configuration lock register */ 52 __IOM uint32_t IF; /**< Interrupt Flags */ 53 __IOM uint32_t IEN; /**< Interrupt Enables */ 54 __IOM uint32_t EM4CTRL; /**< EM4 Control */ 55 __IOM uint32_t CMD; /**< EMU Command register */ 56 __IOM uint32_t CTRL; /**< EMU Control register */ 57 __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ 58 uint32_t RESERVED3[2U]; /**< Reserved for future use */ 59 __IM uint32_t STATUS; /**< EMU Status register */ 60 __IM uint32_t TEMP; /**< Temperature */ 61 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 62 __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ 63 __IM uint32_t RSTCAUSE; /**< Reset cause */ 64 uint32_t RESERVED5[2U]; /**< Reserved for future use */ 65 __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ 66 __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ 67 __IOM uint32_t SEIF; /**< Interrupt Flags Secure Element */ 68 __IOM uint32_t SEIEN; /**< Interrupt Enables Secure Elements */ 69 uint32_t RESERVED6[4U]; /**< Reserved for future use */ 70 uint32_t RESERVED7[1U]; /**< Reserved for future use */ 71 uint32_t RESERVED8[975U]; /**< Reserved for future use */ 72 uint32_t RESERVED9[4U]; /**< Reserved for future use */ 73 __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ 74 uint32_t RESERVED10[3U]; /**< Reserved for future use */ 75 __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ 76 uint32_t RESERVED11[15U]; /**< Reserved for future use */ 77 __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ 78 __IOM uint32_t IF_SET; /**< Interrupt Flags */ 79 __IOM uint32_t IEN_SET; /**< Interrupt Enables */ 80 __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ 81 __IOM uint32_t CMD_SET; /**< EMU Command register */ 82 __IOM uint32_t CTRL_SET; /**< EMU Control register */ 83 __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ 84 uint32_t RESERVED12[2U]; /**< Reserved for future use */ 85 __IM uint32_t STATUS_SET; /**< EMU Status register */ 86 __IM uint32_t TEMP_SET; /**< Temperature */ 87 uint32_t RESERVED13[1U]; /**< Reserved for future use */ 88 __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ 89 __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ 90 uint32_t RESERVED14[2U]; /**< Reserved for future use */ 91 __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ 92 __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ 93 __IOM uint32_t SEIF_SET; /**< Interrupt Flags Secure Element */ 94 __IOM uint32_t SEIEN_SET; /**< Interrupt Enables Secure Elements */ 95 uint32_t RESERVED15[4U]; /**< Reserved for future use */ 96 uint32_t RESERVED16[1U]; /**< Reserved for future use */ 97 uint32_t RESERVED17[975U]; /**< Reserved for future use */ 98 uint32_t RESERVED18[4U]; /**< Reserved for future use */ 99 __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ 100 uint32_t RESERVED19[3U]; /**< Reserved for future use */ 101 __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ 102 uint32_t RESERVED20[15U]; /**< Reserved for future use */ 103 __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ 104 __IOM uint32_t IF_CLR; /**< Interrupt Flags */ 105 __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ 106 __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ 107 __IOM uint32_t CMD_CLR; /**< EMU Command register */ 108 __IOM uint32_t CTRL_CLR; /**< EMU Control register */ 109 __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ 110 uint32_t RESERVED21[2U]; /**< Reserved for future use */ 111 __IM uint32_t STATUS_CLR; /**< EMU Status register */ 112 __IM uint32_t TEMP_CLR; /**< Temperature */ 113 uint32_t RESERVED22[1U]; /**< Reserved for future use */ 114 __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ 115 __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ 116 uint32_t RESERVED23[2U]; /**< Reserved for future use */ 117 __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ 118 __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ 119 __IOM uint32_t SEIF_CLR; /**< Interrupt Flags Secure Element */ 120 __IOM uint32_t SEIEN_CLR; /**< Interrupt Enables Secure Elements */ 121 uint32_t RESERVED24[4U]; /**< Reserved for future use */ 122 uint32_t RESERVED25[1U]; /**< Reserved for future use */ 123 uint32_t RESERVED26[975U]; /**< Reserved for future use */ 124 uint32_t RESERVED27[4U]; /**< Reserved for future use */ 125 __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ 126 uint32_t RESERVED28[3U]; /**< Reserved for future use */ 127 __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ 128 uint32_t RESERVED29[15U]; /**< Reserved for future use */ 129 __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ 130 __IOM uint32_t IF_TGL; /**< Interrupt Flags */ 131 __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ 132 __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ 133 __IOM uint32_t CMD_TGL; /**< EMU Command register */ 134 __IOM uint32_t CTRL_TGL; /**< EMU Control register */ 135 __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ 136 uint32_t RESERVED30[2U]; /**< Reserved for future use */ 137 __IM uint32_t STATUS_TGL; /**< EMU Status register */ 138 __IM uint32_t TEMP_TGL; /**< Temperature */ 139 uint32_t RESERVED31[1U]; /**< Reserved for future use */ 140 __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ 141 __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ 142 uint32_t RESERVED32[2U]; /**< Reserved for future use */ 143 __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ 144 __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ 145 __IOM uint32_t SEIF_TGL; /**< Interrupt Flags Secure Element */ 146 __IOM uint32_t SEIEN_TGL; /**< Interrupt Enables Secure Elements */ 147 uint32_t RESERVED33[4U]; /**< Reserved for future use */ 148 uint32_t RESERVED34[1U]; /**< Reserved for future use */ 149 } EMU_TypeDef; 150 /** @} End of group EFR32MG21_EMU */ 151 152 /**************************************************************************//** 153 * @addtogroup EFR32MG21_EMU 154 * @{ 155 * @defgroup EFR32MG21_EMU_BitFields EMU Bit Fields 156 * @{ 157 *****************************************************************************/ 158 159 /* Bit fields for EMU DECBOD */ 160 #define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ 161 #define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ 162 #define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ 163 #define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ 164 #define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ 165 #define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ 166 #define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ 167 #define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ 168 #define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ 169 #define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ 170 #define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ 171 #define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ 172 #define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ 173 #define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ 174 #define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ 175 #define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ 176 #define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ 177 #define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ 178 #define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ 179 #define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ 180 #define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ 181 #define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ 182 183 /* Bit fields for EMU BOD3SENSE */ 184 #define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ 185 #define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ 186 #define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ 187 #define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ 188 #define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ 189 #define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ 190 #define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ 191 #define EMU_BOD3SENSE_IOVDD0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ 192 #define _EMU_BOD3SENSE_IOVDD0BODEN_SHIFT 1 /**< Shift value for EMU_IOVDD0BODEN */ 193 #define _EMU_BOD3SENSE_IOVDD0BODEN_MASK 0x2UL /**< Bit mask for EMU_IOVDD0BODEN */ 194 #define _EMU_BOD3SENSE_IOVDD0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ 195 #define EMU_BOD3SENSE_IOVDD0BODEN_DEFAULT (_EMU_BOD3SENSE_IOVDD0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ 196 #define EMU_BOD3SENSE_IOVDD1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ 197 #define _EMU_BOD3SENSE_IOVDD1BODEN_SHIFT 2 /**< Shift value for EMU_IOVDD1BODEN */ 198 #define _EMU_BOD3SENSE_IOVDD1BODEN_MASK 0x4UL /**< Bit mask for EMU_IOVDD1BODEN */ 199 #define _EMU_BOD3SENSE_IOVDD1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ 200 #define EMU_BOD3SENSE_IOVDD1BODEN_DEFAULT (_EMU_BOD3SENSE_IOVDD1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ 201 202 /* Bit fields for EMU LOCK */ 203 #define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ 204 #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ 205 #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ 206 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ 207 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ 208 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ 209 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ 210 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ 211 212 /* Bit fields for EMU IF */ 213 #define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ 214 #define _EMU_IF_MASK 0xE3070000UL /**< Mask for EMU_IF */ 215 #define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ 216 #define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ 217 #define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ 218 #define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 219 #define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ 220 #define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ 221 #define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ 222 #define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ 223 #define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 224 #define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ 225 #define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ 226 #define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 227 #define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 228 #define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 229 #define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ 230 #define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ 231 #define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 232 #define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 233 #define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 234 #define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ 235 #define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ 236 #define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 237 #define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 238 #define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 239 #define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ 240 #define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ 241 #define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 242 #define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 243 #define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 244 #define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ 245 246 /* Bit fields for EMU IEN */ 247 #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ 248 #define _EMU_IEN_MASK 0xE3070000UL /**< Mask for EMU_IEN */ 249 #define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ 250 #define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ 251 #define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ 252 #define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 253 #define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ 254 #define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ 255 #define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ 256 #define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ 257 #define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 258 #define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ 259 #define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ 260 #define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 261 #define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 262 #define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 263 #define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ 264 #define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ 265 #define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 266 #define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 267 #define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 268 #define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ 269 #define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ 270 #define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 271 #define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 272 #define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 273 #define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ 274 #define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ 275 #define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 276 #define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 277 #define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 278 #define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ 279 280 /* Bit fields for EMU EM4CTRL */ 281 #define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ 282 #define _EMU_EM4CTRL_MASK 0x00000033UL /**< Mask for EMU_EM4CTRL */ 283 #define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ 284 #define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ 285 #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 286 #define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 287 #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ 288 #define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ 289 #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 290 #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ 291 #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ 292 #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ 293 #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 294 #define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ 295 #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ 296 #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ 297 298 /* Bit fields for EMU CMD */ 299 #define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ 300 #define _EMU_CMD_MASK 0x00020E02UL /**< Mask for EMU_CMD */ 301 #define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ 302 #define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ 303 #define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ 304 #define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ 305 #define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ 306 #define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ 307 #define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ 308 #define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ 309 #define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ 310 #define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ 311 312 /* Bit fields for EMU CTRL */ 313 #define _EMU_CTRL_RESETVALUE 0x0000A200UL /**< Default value for EMU_CTRL */ 314 #define _EMU_CTRL_MASK 0x0001F303UL /**< Mask for EMU_CTRL */ 315 #define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ 316 #define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ 317 #define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ 318 #define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 319 #define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ 320 #define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ 321 #define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ 322 #define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ 323 #define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 324 #define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ 325 326 /* Bit fields for EMU TEMPLIMITS */ 327 #define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ 328 #define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ 329 #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ 330 #define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ 331 #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ 332 #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ 333 #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ 334 #define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ 335 #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ 336 #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ 337 338 /* Bit fields for EMU STATUS */ 339 #define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ 340 #define _EMU_STATUS_MASK 0x000054F7UL /**< Mask for EMU_STATUS */ 341 #define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ 342 #define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ 343 #define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ 344 #define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 345 #define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ 346 #define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ 347 #define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ 348 #define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ 349 #define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ 350 #define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ 351 #define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ 352 #define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ 353 #define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 354 #define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ 355 #define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ 356 #define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ 357 #define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ 358 #define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 359 #define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ 360 #define EMU_STATUS_RACACTIVE (0x1UL << 10) /**< RAC active */ 361 #define _EMU_STATUS_RACACTIVE_SHIFT 10 /**< Shift value for EMU_RACACTIVE */ 362 #define _EMU_STATUS_RACACTIVE_MASK 0x400UL /**< Bit mask for EMU_RACACTIVE */ 363 #define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 364 #define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ 365 #define EMU_STATUS_EM4IORET (0x1UL << 12) /**< EM4 IO retention status */ 366 #define _EMU_STATUS_EM4IORET_SHIFT 12 /**< Shift value for EMU_EM4IORET */ 367 #define _EMU_STATUS_EM4IORET_MASK 0x1000UL /**< Bit mask for EMU_EM4IORET */ 368 #define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 369 #define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ 370 #define EMU_STATUS_EM2ENTERED (0x1UL << 14) /**< EM2 entered */ 371 #define _EMU_STATUS_EM2ENTERED_SHIFT 14 /**< Shift value for EMU_EM2ENTERED */ 372 #define _EMU_STATUS_EM2ENTERED_MASK 0x4000UL /**< Bit mask for EMU_EM2ENTERED */ 373 #define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 374 #define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_STATUS */ 375 376 /* Bit fields for EMU TEMP */ 377 #define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ 378 #define _EMU_TEMP_MASK 0x000007FFUL /**< Mask for EMU_TEMP */ 379 #define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ 380 #define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ 381 #define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ 382 #define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ 383 #define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ 384 #define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ 385 #define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ 386 #define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ 387 388 /* Bit fields for EMU RSTCTRL */ 389 #define _EMU_RSTCTRL_RESETVALUE 0x00004407UL /**< Default value for EMU_RSTCTRL */ 390 #define _EMU_RSTCTRL_MASK 0x0000C5CFUL /**< Mask for EMU_RSTCTRL */ 391 #define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ 392 #define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ 393 #define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ 394 #define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ 395 #define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 396 #define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 397 #define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 398 #define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 399 #define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 400 #define EMU_RSTCTRL_WDOG1RMODE (0x1UL << 1) /**< Enable WDOG1 reset */ 401 #define _EMU_RSTCTRL_WDOG1RMODE_SHIFT 1 /**< Shift value for EMU_WDOG1RMODE */ 402 #define _EMU_RSTCTRL_WDOG1RMODE_MASK 0x2UL /**< Bit mask for EMU_WDOG1RMODE */ 403 #define _EMU_RSTCTRL_WDOG1RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ 404 #define _EMU_RSTCTRL_WDOG1RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 405 #define _EMU_RSTCTRL_WDOG1RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 406 #define EMU_RSTCTRL_WDOG1RMODE_DEFAULT (_EMU_RSTCTRL_WDOG1RMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 407 #define EMU_RSTCTRL_WDOG1RMODE_DISABLED (_EMU_RSTCTRL_WDOG1RMODE_DISABLED << 1) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 408 #define EMU_RSTCTRL_WDOG1RMODE_ENABLED (_EMU_RSTCTRL_WDOG1RMODE_ENABLED << 1) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 409 #define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ 410 #define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ 411 #define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ 412 #define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ 413 #define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 414 #define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 415 #define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 416 #define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 417 #define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 418 #define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ 419 #define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ 420 #define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ 421 #define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ 422 #define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 423 #define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 424 #define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 425 #define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 426 #define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 427 #define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ 428 #define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ 429 #define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ 430 #define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ 431 #define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 432 #define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 433 #define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 434 #define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 435 #define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 436 #define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ 437 #define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ 438 #define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ 439 #define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ 440 #define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 441 #define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 442 #define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 443 #define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 444 #define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 445 #define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ 446 #define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ 447 #define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ 448 #define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ 449 #define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 450 #define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 451 #define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 452 #define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 453 #define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 454 #define EMU_RSTCTRL_SESYSRMODE (0x1UL << 14) /**< Enable SE System reset */ 455 #define _EMU_RSTCTRL_SESYSRMODE_SHIFT 14 /**< Shift value for EMU_SESYSRMODE */ 456 #define _EMU_RSTCTRL_SESYSRMODE_MASK 0x4000UL /**< Bit mask for EMU_SESYSRMODE */ 457 #define _EMU_RSTCTRL_SESYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ 458 #define _EMU_RSTCTRL_SESYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 459 #define _EMU_RSTCTRL_SESYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 460 #define EMU_RSTCTRL_SESYSRMODE_DEFAULT (_EMU_RSTCTRL_SESYSRMODE_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 461 #define EMU_RSTCTRL_SESYSRMODE_DISABLED (_EMU_RSTCTRL_SESYSRMODE_DISABLED << 14) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 462 #define EMU_RSTCTRL_SESYSRMODE_ENABLED (_EMU_RSTCTRL_SESYSRMODE_ENABLED << 14) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 463 #define EMU_RSTCTRL_SELOCKUPRMODE (0x1UL << 15) /**< Enable SE Lockup reset */ 464 #define _EMU_RSTCTRL_SELOCKUPRMODE_SHIFT 15 /**< Shift value for EMU_SELOCKUPRMODE */ 465 #define _EMU_RSTCTRL_SELOCKUPRMODE_MASK 0x8000UL /**< Bit mask for EMU_SELOCKUPRMODE */ 466 #define _EMU_RSTCTRL_SELOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ 467 #define _EMU_RSTCTRL_SELOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ 468 #define _EMU_RSTCTRL_SELOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ 469 #define EMU_RSTCTRL_SELOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_SELOCKUPRMODE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ 470 #define EMU_RSTCTRL_SELOCKUPRMODE_DISABLED (_EMU_RSTCTRL_SELOCKUPRMODE_DISABLED << 15) /**< Shifted mode DISABLED for EMU_RSTCTRL */ 471 #define EMU_RSTCTRL_SELOCKUPRMODE_ENABLED (_EMU_RSTCTRL_SELOCKUPRMODE_ENABLED << 15) /**< Shifted mode ENABLED for EMU_RSTCTRL */ 472 473 /* Bit fields for EMU RSTCAUSE */ 474 #define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ 475 #define _EMU_RSTCAUSE_MASK 0x0000FFFFUL /**< Mask for EMU_RSTCAUSE */ 476 #define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ 477 #define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ 478 #define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ 479 #define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 480 #define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 481 #define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ 482 #define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ 483 #define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ 484 #define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 485 #define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 486 #define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ 487 #define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ 488 #define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ 489 #define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 490 #define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 491 #define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ 492 #define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ 493 #define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ 494 #define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 495 #define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 496 #define EMU_RSTCAUSE_WDOG1 (0x1UL << 4) /**< Watchdog 1 Reset */ 497 #define _EMU_RSTCAUSE_WDOG1_SHIFT 4 /**< Shift value for EMU_WDOG1 */ 498 #define _EMU_RSTCAUSE_WDOG1_MASK 0x10UL /**< Bit mask for EMU_WDOG1 */ 499 #define _EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 500 #define EMU_RSTCAUSE_WDOG1_DEFAULT (_EMU_RSTCAUSE_WDOG1_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 501 #define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ 502 #define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ 503 #define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ 504 #define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 505 #define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 506 #define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ 507 #define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ 508 #define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ 509 #define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 510 #define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 511 #define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ 512 #define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ 513 #define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ 514 #define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 515 #define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 516 #define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ 517 #define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ 518 #define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ 519 #define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 520 #define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 521 #define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ 522 #define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ 523 #define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ 524 #define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 525 #define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 526 #define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ 527 #define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ 528 #define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ 529 #define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 530 #define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 531 #define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ 532 #define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ 533 #define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ 534 #define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 535 #define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 536 #define EMU_RSTCAUSE_SETAMPER (0x1UL << 13) /**< SE Tamper event Reset */ 537 #define _EMU_RSTCAUSE_SETAMPER_SHIFT 13 /**< Shift value for EMU_SETAMPER */ 538 #define _EMU_RSTCAUSE_SETAMPER_MASK 0x2000UL /**< Bit mask for EMU_SETAMPER */ 539 #define _EMU_RSTCAUSE_SETAMPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 540 #define EMU_RSTCAUSE_SETAMPER_DEFAULT (_EMU_RSTCAUSE_SETAMPER_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 541 #define EMU_RSTCAUSE_SESYSREQ (0x1UL << 14) /**< SE System Reset */ 542 #define _EMU_RSTCAUSE_SESYSREQ_SHIFT 14 /**< Shift value for EMU_SESYSREQ */ 543 #define _EMU_RSTCAUSE_SESYSREQ_MASK 0x4000UL /**< Bit mask for EMU_SESYSREQ */ 544 #define _EMU_RSTCAUSE_SESYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 545 #define EMU_RSTCAUSE_SESYSREQ_DEFAULT (_EMU_RSTCAUSE_SESYSREQ_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 546 #define EMU_RSTCAUSE_SELOCKUP (0x1UL << 15) /**< SE Lockup Reset */ 547 #define _EMU_RSTCAUSE_SELOCKUP_SHIFT 15 /**< Shift value for EMU_SELOCKUP */ 548 #define _EMU_RSTCAUSE_SELOCKUP_MASK 0x8000UL /**< Bit mask for EMU_SELOCKUP */ 549 #define _EMU_RSTCAUSE_SELOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ 550 #define EMU_RSTCAUSE_SELOCKUP_DEFAULT (_EMU_RSTCAUSE_SELOCKUP_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ 551 552 /* Bit fields for EMU DGIF */ 553 #define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ 554 #define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ 555 #define EMU_DGIF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ 556 #define _EMU_DGIF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 557 #define _EMU_DGIF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 558 #define _EMU_DGIF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ 559 #define EMU_DGIF_EM23WAKEUP_DEFAULT (_EMU_DGIF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ 560 #define EMU_DGIF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ 561 #define _EMU_DGIF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 562 #define _EMU_DGIF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 563 #define _EMU_DGIF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ 564 #define EMU_DGIF_TEMP_DEFAULT (_EMU_DGIF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ 565 #define EMU_DGIF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ 566 #define _EMU_DGIF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 567 #define _EMU_DGIF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 568 #define _EMU_DGIF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ 569 #define EMU_DGIF_TEMPLOW_DEFAULT (_EMU_DGIF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ 570 #define EMU_DGIF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ 571 #define _EMU_DGIF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 572 #define _EMU_DGIF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 573 #define _EMU_DGIF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ 574 #define EMU_DGIF_TEMPHIGH_DEFAULT (_EMU_DGIF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ 575 576 /* Bit fields for EMU DGIEN */ 577 #define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ 578 #define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ 579 #define EMU_DGIEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ 580 #define _EMU_DGIEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 581 #define _EMU_DGIEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 582 #define _EMU_DGIEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ 583 #define EMU_DGIEN_EM23WAKEUP_DEFAULT (_EMU_DGIEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ 584 #define EMU_DGIEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ 585 #define _EMU_DGIEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 586 #define _EMU_DGIEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 587 #define _EMU_DGIEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ 588 #define EMU_DGIEN_TEMP_DEFAULT (_EMU_DGIEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ 589 #define EMU_DGIEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ 590 #define _EMU_DGIEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 591 #define _EMU_DGIEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 592 #define _EMU_DGIEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ 593 #define EMU_DGIEN_TEMPLOW_DEFAULT (_EMU_DGIEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ 594 #define EMU_DGIEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ 595 #define _EMU_DGIEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 596 #define _EMU_DGIEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 597 #define _EMU_DGIEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ 598 #define EMU_DGIEN_TEMPHIGH_DEFAULT (_EMU_DGIEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ 599 600 /* Bit fields for EMU SEIF */ 601 #define _EMU_SEIF_RESETVALUE 0x00000000UL /**< Default value for EMU_SEIF */ 602 #define _EMU_SEIF_MASK 0xE0000000UL /**< Mask for EMU_SEIF */ 603 #define EMU_SEIF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ 604 #define _EMU_SEIF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 605 #define _EMU_SEIF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 606 #define _EMU_SEIF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEIF */ 607 #define EMU_SEIF_TEMP_DEFAULT (_EMU_SEIF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_SEIF */ 608 #define EMU_SEIF_TEMPLOW (0x1UL << 30) /**< Temperature Interrupt flag */ 609 #define _EMU_SEIF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 610 #define _EMU_SEIF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 611 #define _EMU_SEIF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEIF */ 612 #define EMU_SEIF_TEMPLOW_DEFAULT (_EMU_SEIF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_SEIF */ 613 #define EMU_SEIF_TEMPHIGH (0x1UL << 31) /**< Temperature low Interrupt flag */ 614 #define _EMU_SEIF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 615 #define _EMU_SEIF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 616 #define _EMU_SEIF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEIF */ 617 #define EMU_SEIF_TEMPHIGH_DEFAULT (_EMU_SEIF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_SEIF */ 618 619 /* Bit fields for EMU SEIEN */ 620 #define _EMU_SEIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_SEIEN */ 621 #define _EMU_SEIEN_MASK 0xE0000000UL /**< Mask for EMU_SEIEN */ 622 #define EMU_SEIEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ 623 #define _EMU_SEIEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 624 #define _EMU_SEIEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 625 #define _EMU_SEIEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEIEN */ 626 #define EMU_SEIEN_TEMP_DEFAULT (_EMU_SEIEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_SEIEN */ 627 #define EMU_SEIEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ 628 #define _EMU_SEIEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 629 #define _EMU_SEIEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 630 #define _EMU_SEIEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEIEN */ 631 #define EMU_SEIEN_TEMPLOW_DEFAULT (_EMU_SEIEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_SEIEN */ 632 #define EMU_SEIEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ 633 #define _EMU_SEIEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 634 #define _EMU_SEIEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 635 #define _EMU_SEIEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_SEIEN */ 636 #define EMU_SEIEN_TEMPHIGH_DEFAULT (_EMU_SEIEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_SEIEN */ 637 638 /** @} End of group EFR32MG21_EMU_BitFields */ 639 /** @} End of group EFR32MG21_EMU */ 640 /** @} End of group Parts */ 641 642 #endif // EFR32MG21_EMU_H 643
