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Searched refs:ECC_RAM1_MEM_BASE (Results 1 – 2 of 2) sorted by relevance

/hal_silabs-latest/gecko/emlib/src/
Dem_msc.c79 #define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) macro
103 #define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) macro
181 #define ECC_RAM1_MEM_BASE (DMEM1_RAM0_RAM_MEM_BASE) macro
278 ECC_RAM1_MEM_BASE, ECC_RAM1_MEM_SIZE
1577 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccReadWriteExistingPio()
1601 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccReadWriteExistingPio()
1848 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccBankInit()
1881 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccBankDisable()
/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_msc.c79 #define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) macro
103 #define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) macro
182 #define ECC_RAM1_MEM_BASE (DMEM1_RAM0_RAM_MEM_BASE) macro
280 ECC_RAM1_MEM_BASE, ECC_RAM1_MEM_SIZE
1580 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccReadWriteExistingPio()
1606 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccReadWriteExistingPio()
1854 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccBankInit()
1887 } else if (eccBank->base == ECC_RAM1_MEM_BASE) { in mscEccBankDisable()