1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // This file applies to the SIM3L1XX_DTM_A module 24 // 25 // Version: 1 26 27 #ifndef __SI32_DTM_A_Support_Guard__ 28 #define __SI32_DTM_A_Support_Guard__ 29 30 #include <stdint.h> 31 #include <si32_device.h> 32 #include <SI32_DMAXBAR_A_Support.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 //----------------------------------------------------------------------------- 39 // These are the DTM state flags and values 40 41 // DTM Channels within a DTM module 42 #define DTM_DMA_A SI32_DTM_A_STATE_DTMCHSEL_CH_A_VALUE 43 #define DTM_DMA_B SI32_DTM_A_STATE_DTMCHSEL_CH_B_VALUE 44 #define DTM_DMA_C SI32_DTM_A_STATE_DTMCHSEL_CH_C_VALUE 45 #define DTM_DMA_D SI32_DTM_A_STATE_DTMCHSEL_CH_D_VALUE 46 47 // DTM sources for each state 48 #define DTM_SRC_MEMORY 15 49 #define DTM_SRC_DMA0T1 14 // dma_io_dmatrig1_req 50 #define DTM_SRC_DMA0T0 13 // dma_io_dmatrig0_req 51 #define DTM_SRC_ENCDEC0 9 // dma_enc0_rx_sreq 52 #define DTM_SRC_EPCA0 8 // dma_pca0_rx_req 53 #define DTM_SRC_SARADC0 7 // dma_adc0_req 54 #define DTM_SRC_I2C0 6 // dma_smb0_rx_sreq 55 #define DTM_SRC_USART0 4 // dma_usart0_rx_sreq 56 #define DTM_SRC_AES0 2 // dma_aes_tx_req 57 #define DTM_SRC_SPI1 1 // dma_spi1_rx_req 58 #define DTM_SRC_SPI0 0 // dma_spi0_rx_req 59 60 // DTM destinations for each state 61 #define DTM_DST_MEMORY 15 62 #define DTM_DST_DMA0T1 14 // dma_io_dmatrig1_req 63 #define DTM_DST_DMA0T0 13 // dma_io_dmatrig0_req 64 #define DTM_DST_ENCDEC0 9 // dma_enc0_tx_sreq 65 #define DTM_DST_EPCA0 8 // dma_pca0_tx_req 66 #define DTM_DST_IDAC0 7 // dma_idac10_sreq 67 #define DTM_DST_I2C0 6 // dma_smb0_tx_sreq 68 #define DTM_DST_USART0 4 // dma_usart0_tx_sreq 69 #define DTM_DST_AES0_XOR 3 // dma_aes_xor_req 70 #define DTM_DST_AES0 2 // dma_aes_rx_req 71 #define DTM_DST_SPI1 1 // dma_spi1_tx_req 72 #define DTM_DST_SPI0 0 // dma_spi0_tx_req 73 74 #define DTM_DONE 15 75 76 // Additional flags for each state 77 #define DTM_INHSPOL SI32_DTM_A_STATE_INHSPOL_MASK 78 #define DTM_DTMINH SI32_DTM_A_STATE_DTMINH_MASK 79 #define DTM_MSTDECEN SI32_DTM_A_STATE_MSTDECEN_MASK 80 #define DTM_TOERRIEN SI32_DTM_A_STATE_TOERRIEN_MASK 81 #define DTM_SECSTIEN SI32_DTM_A_STATE_SECSTIEN_MASK 82 #define DTM_PRISTIEN SI32_DTM_A_STATE_PRISTIEN_MASK 83 84 //----------------------------------------------------------------------------- 85 // Define the DTM state 86 87 #define DTM_STATE(ch, src, dst, pri, sec, cnt) \ 88 ( (((ch) << SI32_DTM_A_STATE_DTMCHSEL_SHIFT) & SI32_DTM_A_STATE_DTMCHSEL_MASK) \ 89 | (((src) << SI32_DTM_A_STATE_SRCMOD_SHIFT) & SI32_DTM_A_STATE_SRCMOD_MASK) \ 90 | (((dst) << SI32_DTM_A_STATE_DSTMOD_SHIFT) & SI32_DTM_A_STATE_DSTMOD_MASK) \ 91 | (((pri) << SI32_DTM_A_STATE_PRIST_SHIFT) & SI32_DTM_A_STATE_PRIST_MASK) \ 92 | (((sec) << SI32_DTM_A_STATE_SECST_SHIFT) & SI32_DTM_A_STATE_SECST_MASK) \ 93 | (((cnt) << SI32_DTM_A_STATE_STRELOAD_SHIFT) & SI32_DTM_A_STATE_STRELOAD_MASK) ) 94 95 typedef struct SI32_DTM_A_STATE_Struct SI32_DTM_A_STATE_Type; 96 97 // Structure for associating each DTM unit with its assigned MCU resources 98 typedef struct SI32_DTM_Unit_Struct 99 { 100 SI32_DTM_A_Type * pBASE; 101 uint32_t AHBCLKG_Mask; 102 uint32_t APBCLKG0_Mask; 103 IRQn_Type NVIC_IRQn; 104 SI32_DMAXBAR_CHNSEL_Enum_Type DMAXBAR_Select[4]; 105 } 106 SI32_DTM_Unit_Type; 107 108 #ifdef __cplusplus 109 } 110 #endif 111 112 #endif // __SI32_DTM_A_Support_Guard__ 113 114 //-eof-------------------------------------------------------------------------- 115
