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Searched refs:DCDC (Results 1 – 25 of 105) sorted by relevance

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/hal_silabs-latest/simplicity_sdk/platform/peripheral/inc/
Dsl_hal_dcdc_coulomb_counter.h127 DCDC->CCCTRL_SET = DCDC_CCCTRL_CCEN; in sl_hal_dcdc_coulomb_counter_enable()
141 while ((DCDC->CCSTATUS & _DCDC_CCSTATUS_CCRUNNING_MASK) == 0U) { in sl_hal_dcdc_coulomb_counter_wait_start()
152 while ((DCDC->CCSTATUS & _DCDC_CCSTATUS_CCRUNNING_MASK) == DCDC_CCSTATUS_CCRUNNING) { in sl_hal_dcdc_coulomb_counter_wait_stop()
163 while ((DCDC->CCSTATUS & _DCDC_CCSTATUS_CLRBSY_MASK) == DCDC_CCSTATUS_CLRBSY) { in sl_hal_dcdc_coulomb_counter_wait_clear_counters()
180 DCDC->CCCMD_SET = DCDC_CCCMD_START; in sl_hal_dcdc_coulomb_counter_start()
195 DCDC->CCCMD_SET = DCDC_CCCMD_STOP; in sl_hal_dcdc_coulomb_counter_stop()
210 DCDC->CCCMD_SET = DCDC_CCCMD_CLR; in sl_hal_dcdc_coulomb_counter_clear_counters()
229 return DCDC->CCSTATUS; in sl_hal_dcdc_coulomb_counter_get_status()
245 DCDC->CCIEN_SET = flags; in sl_hal_dcdc_coulomb_counter_enable_interrupts()
257 DCDC->CCIEN_CLR = flags; in sl_hal_dcdc_coulomb_counter_disable_interrupts()
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/hal_silabs-latest/simplicity_sdk/platform/peripheral/src/
Dsl_hal_dcdc_coulomb_counter.c56 if (DCDC->CCCTRL & _DCDC_CCCTRL_CCEN_MASK) { in sl_hal_dcdc_coulomb_counter_init()
64 DCDC->CCTHR = ((uint32_t)(p_config->counter_threshold_em0) << _DCDC_CCTHR_EM0CNT_SHIFT) in sl_hal_dcdc_coulomb_counter_init()
74 if ((DCDC->CCCTRL & _DCDC_CCCTRL_CCEN_MASK) == 0U) { in sl_hal_dcdc_coulomb_counter_disable()
79 if (DCDC->CCSTATUS & _DCDC_CCSTATUS_CCRUNNING_MASK) { in sl_hal_dcdc_coulomb_counter_disable()
85 DCDC->CCCTRL_CLR = DCDC_CCCTRL_CCEN; in sl_hal_dcdc_coulomb_counter_disable()
97 return DCDC->CCEM0CNT; in sl_hal_dcdc_coulomb_counter_get_count()
99 return DCDC->CCEM2CNT; in sl_hal_dcdc_coulomb_counter_get_count()
139 DCDC->IF_CLR = DCDC_IF_REGULATION; in sl_hal_dcdc_coulomb_counter_cal_init()
140 while ((DCDC->IF & DCDC_IF_REGULATION) == 0U) { in sl_hal_dcdc_coulomb_counter_cal_init()
146 DCDC->CCCALCTRL_CLR = DCDC_CCCALCTRL_CCCALHALT; in sl_hal_dcdc_coulomb_counter_cal_init()
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/hal_silabs-latest/simplicity_sdk/platform/service/power_manager/src/common/
Dsl_power_manager_em4.c276 DCDC->EM01CTRL0 = (DCDC->EM01CTRL0 & ~_DCDC_EM01CTRL0_IPKVAL_MASK) | (ipkval << 0); in ramp_dvdd_and_switch_to_dcdc_bypass_mode()
277 DCDC->CTRL = (DCDC->CTRL & ~_DCDC_CTRL_IPKTMAXCTRL_MASK) | (ipktimeout << 4); in ramp_dvdd_and_switch_to_dcdc_bypass_mode()
287 DCDC->CTRL_CLR = DCDC_CTRL_MODE; in ramp_dvdd_and_switch_to_dcdc_bypass_mode()
304 DCDC->CTRL_CLR = DCDC_CTRL_MODE; in ramp_dvdd_and_switch_to_dcdc_bypass_mode()
309 if (DCDC->IF & DCDC_IF_TMAX) { in ramp_dvdd_and_switch_to_dcdc_bypass_mode()
318 DCDC->EM01CTRL0 = (DCDC->EM01CTRL0 & ~_DCDC_EM01CTRL0_IPKVAL_MASK) | (ipkval << 0); in ramp_dvdd_and_switch_to_dcdc_bypass_mode()
319 DCDC->CTRL = (DCDC->CTRL & ~_DCDC_CTRL_IPKTMAXCTRL_MASK) | (ipktimeout << 4); in ramp_dvdd_and_switch_to_dcdc_bypass_mode()
321 DCDC->IF_CLR = DCDC_IF_TMAX; in ramp_dvdd_and_switch_to_dcdc_bypass_mode()
/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_emu.c1592 EFM_ASSERT((DCDC->IF & _DCDC_IF_EM4ERR_MASK) == 0);
3347 DCDC->EN_SET = DCDC_EN_EN; in EMU_DCDCBoostInit()
3349 dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); in EMU_DCDCBoostInit()
3357 BUS_RegMaskedWrite(&DCDC->CTRL, in EMU_DCDCBoostInit()
3362 DCDC->BSTCTRL = (DCDC->BSTCTRL & ~(_DCDC_BSTCTRL_IPKTMAXCTRL_MASK)) in EMU_DCDCBoostInit()
3364 DCDC->BSTEM01CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM01 << _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT) in EMU_DCDCBoostInit()
3366 DCDC->BSTEM23CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM23 << _DCDC_BSTEM23CTRL_DRVSPEED_SHIFT) in EMU_DCDCBoostInit()
3397 dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); in EMU_EM01BoostPeakCurrentSet()
3405 BUS_RegMaskedWrite(&DCDC->BSTEM01CTRL, in EMU_EM01BoostPeakCurrentSet()
3451 dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); in EMU_DCDCBoostOutputVoltageSet()
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/hal_silabs-latest/gecko/emlib/src/
Dem_emu.c1537 EFM_ASSERT((DCDC->IF & _DCDC_IF_EM4ERR_MASK) == 0);
3292 DCDC->EN_SET = DCDC_EN_EN; in EMU_DCDCBoostInit()
3294 dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); in EMU_DCDCBoostInit()
3301 DCDC->BSTCTRL = (DCDC->BSTCTRL & ~(_DCDC_BSTCTRL_IPKTMAXCTRL_MASK)) in EMU_DCDCBoostInit()
3303 DCDC->BSTEM01CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM01 << _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT) in EMU_DCDCBoostInit()
3305 DCDC->BSTEM23CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM23 << _DCDC_BSTEM23CTRL_DRVSPEED_SHIFT) in EMU_DCDCBoostInit()
3336 dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); in EMU_EM01BoostPeakCurrentSet()
3344 BUS_RegMaskedWrite(&DCDC->BSTEM01CTRL, in EMU_EM01BoostPeakCurrentSet()
3414 DCDC->EN_SET = DCDC_EN_EN; in EMU_DCDCModeSet()
3416 dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); in EMU_DCDCModeSet()
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/hal_silabs-latest/gecko/emlib/inc/
Dem_chip.h368 bool dcdcIsLock = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK_LOCKED) != 0); in CHIP_Init()
369 DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; in CHIP_Init()
371 while (DCDC->SYNCBUSY & DCDC_SYNCBUSY_CTRL) { in CHIP_Init()
375 DCDC->CTRL_CLR = DCDC_CTRL_MODE; in CHIP_Init()
376 while ((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) { in CHIP_Init()
381 DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; in CHIP_Init()
Dem_emu.h1251 DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; in EMU_DCDCLock()
1262 DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; in EMU_DCDCUnlock()
1277 while (0UL != (DCDC->SYNCBUSY & mask)) { in EMU_DCDCSync()
/hal_silabs-latest/simplicity_sdk/platform/emlib/inc/
Dem_chip.h372 bool dcdcIsLock = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK_LOCKED) != 0); in CHIP_Init()
373 DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; in CHIP_Init()
375 while (DCDC->SYNCBUSY & DCDC_SYNCBUSY_CTRL) { in CHIP_Init()
379 DCDC->CTRL_CLR = DCDC_CTRL_MODE; in CHIP_Init()
380 while ((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) { in CHIP_Init()
385 DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; in CHIP_Init()
Dem_emu.h1322 DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; in EMU_DCDCLock()
1333 DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; in EMU_DCDCUnlock()
1348 while (0UL != (DCDC->SYNCBUSY & mask)) { in EMU_DCDCSync()
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c224f512gn32.h915 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC… macro
Defr32bg22c224f512im32.h915 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC… macro
Defr32bg22e224f512im40.h929 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC… macro
Defr32bg22c112f352gm32.h913 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC… macro
Defr32bg22c224f512im40.h929 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC… macro
Defr32bg22e224f512im32.h915 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC… macro
Defr32bg22c112f352gm40.h927 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC… macro
Defr32bg22c222f352gm32.h915 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC… macro
Defr32bg22c222f352gm40.h929 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC… macro
Defr32bg22c222f352gn32.h915 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC… macro
Defr32bg22c224f512gm32.h915 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC… macro
Defr32bg22c224f512gm40.h929 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC… macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/
Defr32fg23b020f128gm40.h1030 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base poi… macro
Defr32fg23b020f512im40.h1030 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base poi… macro
Defr32fg23b021f512im40.h1027 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base poi… macro
Defr32fg23a010f128gm40.h1029 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base poi… macro

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