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Searched refs:CTRL (Results 1 – 25 of 755) sorted by relevance

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/hal_silabs-latest/gecko/emlib/src/
Dem_vcmp.c61 VCMP->CTRL |= VCMP_CTRL_HALFBIAS; in VCMP_Init()
63 VCMP->CTRL &= ~(VCMP_CTRL_HALFBIAS); in VCMP_Init()
67 VCMP->CTRL &= ~(_VCMP_CTRL_BIASPROG_MASK); in VCMP_Init()
68 VCMP->CTRL |= (vcmpInit->biasProg << _VCMP_CTRL_BIASPROG_SHIFT); in VCMP_Init()
72 VCMP->CTRL |= VCMP_CTRL_IFALL; in VCMP_Init()
74 VCMP->CTRL &= ~(VCMP_CTRL_IFALL); in VCMP_Init()
79 VCMP->CTRL |= VCMP_CTRL_IRISE; in VCMP_Init()
81 VCMP->CTRL &= ~(VCMP_CTRL_IRISE); in VCMP_Init()
85 VCMP->CTRL &= ~(_VCMP_CTRL_WARMTIME_MASK); in VCMP_Init()
86 VCMP->CTRL |= (vcmpInit->warmup << _VCMP_CTRL_WARMTIME_SHIFT); in VCMP_Init()
[all …]
Dem_can.c98 can->CTRL = _CAN_CTRL_TEST_MASK; in CAN_Init()
103 can->CTRL = CAN_CTRL_INIT; in CAN_Init()
178 messageLost = mir->CTRL & _CAN_MIR_CTRL_MESSAGEOF_MASK; in CAN_MessageLost()
184 mir->CTRL &= ~_CAN_MIR_CTRL_MESSAGEOF_MASK; in CAN_MessageLost()
299 can->CTRL |= CAN_CTRL_CCE | CAN_CTRL_INIT; in CAN_SetBitTiming()
308 can->CTRL &= ~(_CAN_CTRL_CCE_MASK | _CAN_CTRL_INIT_MASK); in CAN_SetBitTiming()
310 can->CTRL &= ~_CAN_CTRL_CCE_MASK; in CAN_SetBitTiming()
333 can->CTRL |= _CAN_CTRL_TEST_MASK; in CAN_SetMode()
335 can->CTRL &= ~_CAN_CTRL_TEST_MASK; in CAN_SetMode()
337 can->CTRL = _CAN_CTRL_EIE_MASK in CAN_SetMode()
[all …]
Dem_prs.c90 signal = (PRS_Signal_t) (PRS->ASYNC_CH[ch].CTRL in getSignal()
93 signal = (PRS_Signal_t) (PRS->SYNC_CH[ch].CTRL in getSignal()
98 signal = (PRS_Signal_t) (PRS->CH[ch].CTRL in getSignal()
331 PRS->SYNC_CH[ch].CTRL = (source & _PRS_SYNC_CH_CTRL_SOURCESEL_MASK) in PRS_SourceSignalSet()
335 PRS->CH[ch].CTRL = (source & _PRS_CH_CTRL_SOURCESEL_MASK) in PRS_SourceSignalSet()
464 PRS->ASYNC_CH[i].CTRL = _PRS_ASYNC_CH_CTRL_RESETVALUE; in PRS_Reset()
467 PRS->SYNC_CH[i].CTRL = _PRS_SYNC_CH_CTRL_RESETVALUE; in PRS_Reset()
472 PRS->CH[i].CTRL = _PRS_CH_CTRL_RESETVALUE; in PRS_Reset()
505 PRS->ASYNC_CH[ch].CTRL = PRS_ASYNC_CH_CTRL_FNSEL_A in PRS_ConnectSignal()
512 PRS->SYNC_CH[ch].CTRL = (sourceField << _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT) in PRS_ConnectSignal()
[all …]
Dem_pcnt.c125 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); in PCNT_CounterReset()
128 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); in PCNT_CounterReset()
168 tmp = pcnt->CTRL & ~_PCNT_CTRL_MODE_MASK; in PCNT_Enable()
173 pcnt->CTRL = tmp; in PCNT_Enable()
226 return ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE); in PCNT_IsEnabled()
287 ctrl = pcnt->CTRL; in PCNT_CounterTopSet()
292 pcnt->CTRL = (ctrl & ~_PCNT_CTRL_MODE_MASK) | PCNT_CTRL_MODE_DISABLE; in PCNT_CounterTopSet()
329 pcnt->CTRL = ctrl; in PCNT_CounterTopSet()
626 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); in PCNT_Init()
645 pcnt->CTRL = PCNT_CTRL_RSTEN; in PCNT_Init()
[all …]
Dem_aes.c181 AES->CTRL = AES_CTRL_KEYBUFEN | AES_CTRL_XORSTART; in AES_CBC128()
183 AES->CTRL = AES_CTRL_XORSTART; in AES_CBC128()
220 AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART; in AES_CBC128()
222 AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_DATASTART; in AES_CBC128()
314 AES->CTRL = AES_CTRL_AES256 | AES_CTRL_XORSTART; in AES_CBC256()
345 AES->CTRL = AES_CTRL_AES256 | AES_CTRL_DECRYPT | AES_CTRL_DATASTART; in AES_CBC256()
454 AES->CTRL = AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART; in AES_CFB128()
456 AES->CTRL = AES_CTRL_DATASTART; in AES_CFB128()
548 AES->CTRL = AES_CTRL_AES256 | AES_CTRL_DATASTART; in AES_CFB256()
657 AES->CTRL = AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART; in AES_CTR128()
[all …]
Dem_burtc.c88 || ((BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK) == BURTC_CTRL_CLKSEL_NONE) in regSync()
89 || ((BURTC->CTRL & _BURTC_CTRL_RSTEN_MASK) == BURTC_CTRL_RSTEN)) { in regSync()
178 BURTC->CTRL = ctrl; in BURTC_Init()
265 && ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK) in BURTC_Enable()
268 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, (uint32_t) !enable); in BURTC_Enable()
328 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1U); in BURTC_CounterReset()
329 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0U); in BURTC_CounterReset()
351 buResetState = BUS_RegBitRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT); in BURTC_Reset()
352 BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1); in BURTC_Reset()
353 BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState); in BURTC_Reset()
[all …]
Dem_dma.c197 inc = (descr->CTRL & _DMA_CTRL_SRC_INC_MASK) >> _DMA_CTRL_SRC_INC_SHIFT; in DMA_Prepare()
206 inc = (descr->CTRL & _DMA_CTRL_DST_INC_MASK) >> _DMA_CTRL_DST_INC_SHIFT; in DMA_Prepare()
228 tmp = descr->CTRL & ~(_DMA_CTRL_CYCLE_CTRL_MASK | _DMA_CTRL_N_MINUS_1_MASK); in DMA_Prepare()
231 descr->CTRL = tmp; in DMA_Prepare()
589 cycleCtrl = altDescr->CTRL & _DMA_CTRL_CYCLE_CTRL_MASK; in DMA_ActivateScatterGather()
598 altDescr[count - 1].CTRL &= ~_DMA_CTRL_CYCLE_CTRL_MASK; in DMA_ActivateScatterGather()
600 altDescr[count - 1].CTRL |= (uint32_t)dmaCycleCtrlAuto in DMA_ActivateScatterGather()
603 altDescr[count - 1].CTRL |= (uint32_t)dmaCycleCtrlBasic in DMA_ActivateScatterGather()
617 descr->CTRL = ((uint32_t)dmaDataInc4 << _DMA_CTRL_DST_INC_SHIFT) in DMA_ActivateScatterGather()
622 | (altDescr->CTRL & _DMA_CTRL_SRC_PROT_CTRL_MASK) in DMA_ActivateScatterGather()
[all …]
Dem_leuart.c452 leuart->CTRL = (leuart->CTRL & ~(_LEUART_CTRL_PARITY_MASK in LEUART_Init()
486 leuart->CTRL = _LEUART_CTRL_RESETVALUE; in LEUART_Reset()
655 leuart->CTRL |= LEUART_CTRL_TXDMAWU; in LEUART_TxDmaInEM2Enable()
657 leuart->CTRL &= ~LEUART_CTRL_TXDMAWU; in LEUART_TxDmaInEM2Enable()
665 leuart->CTRL |= LEUART_CTRL_TXDMAWU; in LEUART_TxDmaInEM2Enable()
667 leuart->CTRL &= ~LEUART_CTRL_TXDMAWU; in LEUART_TxDmaInEM2Enable()
700 leuart->CTRL |= LEUART_CTRL_RXDMAWU; in LEUART_RxDmaInEM2Enable()
702 leuart->CTRL &= ~LEUART_CTRL_RXDMAWU; in LEUART_RxDmaInEM2Enable()
710 leuart->CTRL |= LEUART_CTRL_RXDMAWU; in LEUART_RxDmaInEM2Enable()
712 leuart->CTRL &= ~LEUART_CTRL_RXDMAWU; in LEUART_RxDmaInEM2Enable()
Dem_idac.c100 idac->CTRL = tmp; in IDAC_Init()
116 BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_EN_SHIFT, enable); in IDAC_Enable()
136 idac->CTRL = _IDAC_CTRL_RESETVALUE | IDAC_CTRL_EN; in IDAC_Reset()
145 idac->CTRL = _IDAC_CTRL_RESETVALUE; in IDAC_Reset()
167 BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_MINOUTTRANS_SHIFT, enable); in IDAC_MinimalOutputTransitionMode()
233 if (idac->CTRL & IDAC_CTRL_CURSINK) { in IDAC_RangeSet()
337 BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_OUTEN_SHIFT, enable); in IDAC_OutEnable()
339 BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_APORTOUTEN_SHIFT, enable); in IDAC_OutEnable()
367 BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_MAINOUTEN_SHIFT, enable); in IDAC_OutpadEnable()
Dem_acmp.c178 acmp->CTRL = _ACMP_CTRL_RESETVALUE; in ACMP_CapsenseInit()
194 acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) in ACMP_CapsenseInit()
206 BUS_RegBitWrite(&acmp->CTRL, _ACMP_CTRL_EN_SHIFT, init->enable); in ACMP_CapsenseInit()
214 acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) in ACMP_CapsenseInit()
225 BUS_RegBitWrite(&acmp->CTRL, _ACMP_CTRL_EN_SHIFT, init->enable); in ACMP_CapsenseInit()
304 acmp->CTRL &= ~ACMP_CTRL_EN; in ACMP_Disable()
323 acmp->CTRL |= ACMP_CTRL_EN; in ACMP_Enable()
383 acmp->CTRL = _ACMP_CTRL_RESETVALUE; in ACMP_Reset()
388 acmp->CTRL = _ACMP_CTRL_RESETVALUE; in ACMP_Reset()
434 acmp->CTRL = (acmp->CTRL & _ACMP_CTRL_NOTRDYVAL_MASK) in ACMP_GPIOSetup()
[all …]
Dem_rtcc.c84 RTCC->CC[ch].CTRL = ((uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT) in RTCC_ChannelInit()
94 RTCC->CC[ch].CTRL = ( (uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT) in RTCC_ChannelInit()
116 BUS_RegBitWrite((&RTCC->CTRL), _RTCC_CTRL_ENABLE_SHIFT, (uint32_t)enable); in RTCC_Enable()
155 RTCC->CTRL = ((init->enable ? 1UL : 0UL) << _RTCC_CTRL_ENABLE_SHIFT) in RTCC_Init()
194 RTCC->CTRL = _RTCC_CTRL_RESETVALUE; in RTCC_Reset()
205 RTCC->CC[i].CTRL = _RTCC_CC_CTRL_RESETVALUE; in RTCC_Reset()
225 RTCC->CC[i].CTRL = _RTCC_CC_CTRL_RESETVALUE; in RTCC_Reset()
Dem_usart.c421 usart->CTRL &= ~_USART_CTRL_OVS_MASK; in USART_BaudrateAsyncSet()
422 usart->CTRL |= ovs; in USART_BaudrateAsyncSet()
592 if (usart->CTRL & USART_CTRL_SYNC) { in USART_BaudrateGet()
612 ovs = (USART_OVS_TypeDef)(usart->CTRL & _USART_CTRL_OVS_MASK); in USART_BaudrateGet()
779 usart->CTRL |= USART_CTRL_MVDIS; in USART_InitAsync()
799 usart->CTRL |= USART_CTRL_AUTOCS; in USART_InitAsync()
802 usart->CTRL |= USART_CTRL_CSINV; in USART_InitAsync()
883 usart->CTRL |= (USART_CTRL_SYNC) in USART_InitSync()
888 usart->CTRL |= init->autoTx ? USART_CTRL_AUTOTX : 0; in USART_InitSync()
911 usart->CTRL |= USART_CTRL_AUTOCS; in USART_InitSync()
[all …]
Dem_wdog.c83 if (wdog->CTRL & WDOG_CTRL_LOCK) { in WDOGn_Enable()
108 bool wdogState = ((wdog->CTRL & _WDOG_CTRL_EN_MASK) != 0U); in WDOGn_Enable()
112 BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT, enable); in WDOGn_Enable()
146 if (!(wdog->CTRL & WDOG_CTRL_EN)) { in WDOGn_Feed()
273 wdog->CTRL = setting; in WDOGn_Init()
309 BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_LOCK_SHIFT, 1); in WDOGn_Lock()
Dem_crypto.c390 BUS_RegBitWrite(&crypto->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES256); in CRYPTO_KeyBufWrite()
396 BUS_RegBitWrite(&crypto->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES128); in CRYPTO_KeyBufWrite()
578 crypto->CTRL = CRYPTO_CTRL_SHA_SHA1; in CRYPTO_SHA_1()
735 crypto->CTRL = CRYPTO_CTRL_SHA_SHA2; in CRYPTO_SHA_256()
920 crypto->CTRL = in CRYPTO_Mul()
1135 crypto->CTRL = CRYPTO_CTRL_AES_AES128; in CRYPTO_AES_CBC128()
1181 crypto->CTRL = CRYPTO_CTRL_AES_AES256; in CRYPTO_AES_CBC256()
1258 crypto->CTRL = CRYPTO_CTRL_AES_AES128; in CRYPTO_AES_PCBC128()
1304 crypto->CTRL = CRYPTO_CTRL_AES_AES256; in CRYPTO_AES_PCBC256()
1377 crypto->CTRL = CRYPTO_CTRL_AES_AES128; in CRYPTO_AES_CFB128()
[all …]
Dem_msc.c92 #define ECC_FAULT_CTRL_REG (MSC->CTRL)
122 #define ECC_FAULT_CTRL_REG (MSC->CTRL)
184 #define ECC_CTRL0_REG (DMEM0->CTRL)
185 #define ECC_CTRL1_REG (DMEM1->CTRL)
191 #define ECC_FAULT_CTRL0_REG (DMEM0->CTRL)
192 #define ECC_FAULT_CTRL1_REG (DMEM1->CTRL)
206 #define ECC_FAULT_CTRL_REG (SYSCFG->CTRL)
210 #define ECC_CTRL_REG (DMEM->CTRL)
213 #define ECC_FAULT_CTRL_REG (DMEM->CTRL)
751 LDMA->CH[ch].CTRL = LDMA_CH_CTRL_DSTINC_NONE in MSC_WriteWordDma()
[all …]
/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_prs.c90 signal = (PRS_Signal_t) (PRS->ASYNC_CH[ch].CTRL in getSignal()
93 signal = (PRS_Signal_t) (PRS->SYNC_CH[ch].CTRL in getSignal()
98 signal = (PRS_Signal_t) (PRS->CH[ch].CTRL in getSignal()
331 PRS->SYNC_CH[ch].CTRL = (source & _PRS_SYNC_CH_CTRL_SOURCESEL_MASK) in PRS_SourceSignalSet()
335 PRS->CH[ch].CTRL = (source & _PRS_CH_CTRL_SOURCESEL_MASK) in PRS_SourceSignalSet()
464 PRS->ASYNC_CH[i].CTRL = _PRS_ASYNC_CH_CTRL_RESETVALUE; in PRS_Reset()
467 PRS->SYNC_CH[i].CTRL = _PRS_SYNC_CH_CTRL_RESETVALUE; in PRS_Reset()
472 PRS->CH[i].CTRL = _PRS_CH_CTRL_RESETVALUE; in PRS_Reset()
505 PRS->ASYNC_CH[ch].CTRL = PRS_ASYNC_CH_CTRL_FNSEL_A in PRS_ConnectSignal()
512 PRS->SYNC_CH[ch].CTRL = (sourceField << _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT) in PRS_ConnectSignal()
[all …]
Dem_pcnt.c125 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); in PCNT_CounterReset()
128 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); in PCNT_CounterReset()
168 tmp = pcnt->CTRL & ~_PCNT_CTRL_MODE_MASK; in PCNT_Enable()
173 pcnt->CTRL = tmp; in PCNT_Enable()
226 return ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE); in PCNT_IsEnabled()
287 ctrl = pcnt->CTRL; in PCNT_CounterTopSet()
292 pcnt->CTRL = (ctrl & ~_PCNT_CTRL_MODE_MASK) | PCNT_CTRL_MODE_DISABLE; in PCNT_CounterTopSet()
329 pcnt->CTRL = ctrl; in PCNT_CounterTopSet()
626 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); in PCNT_Init()
645 pcnt->CTRL = PCNT_CTRL_RSTEN; in PCNT_Init()
[all …]
Dem_burtc.c88 || ((BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK) == BURTC_CTRL_CLKSEL_NONE) in regSync()
89 || ((BURTC->CTRL & _BURTC_CTRL_RSTEN_MASK) == BURTC_CTRL_RSTEN)) { in regSync()
178 BURTC->CTRL = ctrl; in BURTC_Init()
267 && ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK) in BURTC_Enable()
270 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, (uint32_t) !enable); in BURTC_Enable()
330 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1U); in BURTC_CounterReset()
331 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0U); in BURTC_CounterReset()
353 buResetState = BUS_RegBitRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT); in BURTC_Reset()
354 BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1); in BURTC_Reset()
355 BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState); in BURTC_Reset()
[all …]
Dem_acmp.c178 acmp->CTRL = _ACMP_CTRL_RESETVALUE; in ACMP_CapsenseInit()
194 acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) in ACMP_CapsenseInit()
206 BUS_RegBitWrite(&acmp->CTRL, _ACMP_CTRL_EN_SHIFT, init->enable); in ACMP_CapsenseInit()
214 acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) in ACMP_CapsenseInit()
225 BUS_RegBitWrite(&acmp->CTRL, _ACMP_CTRL_EN_SHIFT, init->enable); in ACMP_CapsenseInit()
304 acmp->CTRL &= ~ACMP_CTRL_EN; in ACMP_Disable()
323 acmp->CTRL |= ACMP_CTRL_EN; in ACMP_Enable()
383 acmp->CTRL = _ACMP_CTRL_RESETVALUE; in ACMP_Reset()
388 acmp->CTRL = _ACMP_CTRL_RESETVALUE; in ACMP_Reset()
434 acmp->CTRL = (acmp->CTRL & _ACMP_CTRL_NOTRDYVAL_MASK) in ACMP_GPIOSetup()
[all …]
Dem_rtcc.c84 RTCC->CC[ch].CTRL = ((uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT) in RTCC_ChannelInit()
94 RTCC->CC[ch].CTRL = ( (uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT) in RTCC_ChannelInit()
116 BUS_RegBitWrite((&RTCC->CTRL), _RTCC_CTRL_ENABLE_SHIFT, (uint32_t)enable); in RTCC_Enable()
155 RTCC->CTRL = ((init->enable ? 1UL : 0UL) << _RTCC_CTRL_ENABLE_SHIFT) in RTCC_Init()
194 RTCC->CTRL = _RTCC_CTRL_RESETVALUE; in RTCC_Reset()
205 RTCC->CC[i].CTRL = _RTCC_CC_CTRL_RESETVALUE; in RTCC_Reset()
225 RTCC->CC[i].CTRL = _RTCC_CC_CTRL_RESETVALUE; in RTCC_Reset()
Dem_usart.c421 usart->CTRL &= ~_USART_CTRL_OVS_MASK; in USART_BaudrateAsyncSet()
422 usart->CTRL |= ovs; in USART_BaudrateAsyncSet()
592 if (usart->CTRL & USART_CTRL_SYNC) { in USART_BaudrateGet()
612 ovs = (USART_OVS_TypeDef)(usart->CTRL & _USART_CTRL_OVS_MASK); in USART_BaudrateGet()
779 usart->CTRL |= USART_CTRL_MVDIS; in USART_InitAsync()
799 usart->CTRL |= USART_CTRL_AUTOCS; in USART_InitAsync()
802 usart->CTRL |= USART_CTRL_CSINV; in USART_InitAsync()
883 usart->CTRL |= (USART_CTRL_SYNC) in USART_InitSync()
888 usart->CTRL |= init->autoTx ? USART_CTRL_AUTOTX : 0; in USART_InitSync()
911 usart->CTRL |= USART_CTRL_AUTOCS; in USART_InitSync()
[all …]
Dem_wdog.c83 if (wdog->CTRL & WDOG_CTRL_LOCK) { in WDOGn_Enable()
108 bool wdogState = ((wdog->CTRL & _WDOG_CTRL_EN_MASK) != 0U); in WDOGn_Enable()
112 BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT, enable); in WDOGn_Enable()
146 if (!(wdog->CTRL & WDOG_CTRL_EN)) { in WDOGn_Feed()
273 wdog->CTRL = setting; in WDOGn_Init()
309 BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_LOCK_SHIFT, 1); in WDOGn_Lock()
Dem_crypto.c390 BUS_RegBitWrite(&crypto->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES256); in CRYPTO_KeyBufWrite()
396 BUS_RegBitWrite(&crypto->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES128); in CRYPTO_KeyBufWrite()
578 crypto->CTRL = CRYPTO_CTRL_SHA_SHA1; in CRYPTO_SHA_1()
735 crypto->CTRL = CRYPTO_CTRL_SHA_SHA2; in CRYPTO_SHA_256()
920 crypto->CTRL = in CRYPTO_Mul()
1135 crypto->CTRL = CRYPTO_CTRL_AES_AES128; in CRYPTO_AES_CBC128()
1181 crypto->CTRL = CRYPTO_CTRL_AES_AES256; in CRYPTO_AES_CBC256()
1258 crypto->CTRL = CRYPTO_CTRL_AES_AES128; in CRYPTO_AES_PCBC128()
1304 crypto->CTRL = CRYPTO_CTRL_AES_AES256; in CRYPTO_AES_PCBC256()
1377 crypto->CTRL = CRYPTO_CTRL_AES_AES128; in CRYPTO_AES_CFB128()
[all …]
Dem_msc.c92 #define ECC_FAULT_CTRL_REG (MSC->CTRL)
122 #define ECC_FAULT_CTRL_REG (MSC->CTRL)
185 #define ECC_CTRL0_REG (DMEM0->CTRL)
186 #define ECC_CTRL1_REG (DMEM1->CTRL)
192 #define ECC_FAULT_CTRL0_REG (DMEM0->CTRL)
193 #define ECC_FAULT_CTRL1_REG (DMEM1->CTRL)
208 #define ECC_FAULT_CTRL_REG (SYSCFG->CTRL)
212 #define ECC_CTRL_REG (DMEM->CTRL)
215 #define ECC_FAULT_CTRL_REG (DMEM->CTRL)
753 LDMA->CH[ch].CTRL = LDMA_CH_CTRL_DSTINC_NONE in MSC_WriteWordDma()
[all …]
Dem_emu.c471 if ((EMU->CTRL & _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK) != 0U) { in emState()
667 uint32_t em23vs = (EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) >> _EMU_CTRL_EM23VSCALE_SHIFT; in vScaleDownEM23Setup()
672 EMU->CTRL |= EMU_CTRL_EM23VSCALEAUTOWSEN; in vScaleDownEM23Setup()
680 EMU->CTRL &= ~EMU_CTRL_EM23VSCALEAUTOWSEN; in vScaleDownEM23Setup()
687 if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { in vScaleAfterWakeup()
807 EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG) in EMU_EM23Init()
808 : (EMU->CTRL & ~EMU_CTRL_EMVREG); in EMU_EM23Init()
810 EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EM23VREG) in EMU_EM23Init()
811 : (EMU->CTRL & ~EMU_CTRL_EM23VREG); in EMU_EM23Init()
817 EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK) in EMU_EM23Init()
[all …]

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