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Searched refs:CONTROL_SET (Results 1 – 25 of 136) sorted by relevance

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/hal_silabs-latest/si32/si32Hal/SI32_Modules/
DSI32_LPTIMER_B_Type.c106 basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_CMD_RISING_EDGE_U32; in _SI32_LPTIMER_B_select_rising_edge_increment_mode()
120 basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_CMD_FALLING_EDGE_U32; in _SI32_LPTIMER_B_select_falling_edge_increment_mode()
133 basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_CMD_MASK; in _SI32_LPTIMER_B_select_both_edge_increment_mode()
152 basePointer->CONTROL_SET = source << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT; in _SI32_LPTIMER_B_select_timer_source()
166 basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_TMRSET_SET_U32; in _SI32_LPTIMER_B_start_timer_write()
194 basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_TMRCAP_SET_U32; in _SI32_LPTIMER_B_start_timer_read()
221 basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_HSMDEN_ENABLED_U32; in _SI32_LPTIMER_B_enter_high_speed_timer_access_mode()
247 basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_CMP0EN_ENABLED_U32; in _SI32_LPTIMER_B_enable_compare0_threshold()
273 basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_CMP1EN_ENABLED_U32; in _SI32_LPTIMER_B_enable_compare1_threshold()
299 basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_OUTEN_ENABLED_U32; in _SI32_LPTIMER_B_enable_output()
[all …]
DSI32_LPTIMER_B_Type.h149 basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_CMD_RISING_EDGE_U32;\
164 basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_CMD_FALLING_EDGE_U32;\
178 (basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_CMD_MASK)
203 basePointer->CONTROL_SET = source << SI32_LPTIMER_B_CONTROL_EXTSEL_SHIFT;\
220 (basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_TMRSET_SET_U32)
252 (basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_TMRCAP_SET_U32)
281 (basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_HSMDEN_ENABLED_U32)
307 (basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_CMP0EN_ENABLED_U32)
333 (basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_CMP1EN_ENABLED_U32)
359 (basePointer->CONTROL_SET = SI32_LPTIMER_B_CONTROL_OUTEN_ENABLED_U32)
[all …]
DSI32_LPTIMER_A_Type.c104 basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_CMD_RISING_EDGE_U32; in _SI32_LPTIMER_A_select_rising_edge_increment_mode()
118 basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_CMD_FALLING_EDGE_U32; in _SI32_LPTIMER_A_select_falling_edge_increment_mode()
131 basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_CMD_MASK; in _SI32_LPTIMER_A_select_both_edge_increment_mode()
150 basePointer->CONTROL_SET = source << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT; in _SI32_LPTIMER_A_select_timer_source()
164 basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_TMRSET_SET_U32; in _SI32_LPTIMER_A_start_timer_write()
192 basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_TMRCAP_SET_U32; in _SI32_LPTIMER_A_start_timer_read()
220 basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_CMPSET_SET_U32; in _SI32_LPTIMER_A_start_comparator_write()
248 basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_CMPCAP_SET_U32; in _SI32_LPTIMER_A_start_comparator_read()
275 basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_OVFIEN_ENABLED_U32; in _SI32_LPTIMER_A_enable_overflow_interrupt()
314 basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_CMPIEN_ENABLED_U32; in _SI32_LPTIMER_A_enable_compare_interrupt()
[all …]
DSI32_IDAC_A_Type.c91 basePointer->CONTROL_SET = trigger; in _SI32_IDAC_A_set_output_update_trigger()
111 basePointer->CONTROL_SET = trigger_src << SI32_IDAC_A_CONTROL_ETRIG_SHIFT; in _SI32_IDAC_A_set_external_trigger_channel()
126 basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_OUTMD_2_MA_U32; in _SI32_IDAC_A_select_output_fullscale_2ma()
141 basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_OUTMD_1_MA_U32; in _SI32_IDAC_A_select_output_fullscale_1ma()
170 basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_INFMT_2_10_BIT_U32; in _SI32_IDAC_A_select_2x10bit_input_format()
199 basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_INFMT_4_8_BIT_U32; in _SI32_IDAC_A_select_4x8bit_input_format()
212 basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_DMARUN_MASK; in _SI32_IDAC_A_start_dma_operation()
239 basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_JSEL_MASK; in _SI32_IDAC_A_select_left_justification()
267 basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_BUFRESET_MASK; in _SI32_IDAC_A_reset_buffer()
295 basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_TRIGINH_MASK; in _SI32_IDAC_A_disable_trigger()
[all …]
DSI32_ENCDEC_A_Type.c86 basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_INRDYIEN_ENABLED_U32; in _SI32_ENCDEC_A_enable_input_ready_interrupt()
125 basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_ORDYIEN_ENABLED_U32; in _SI32_ENCDEC_A_enable_output_ready_interrupt()
164 basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_ERRIEN_ENABLED_U32; in _SI32_ENCDEC_A_enable_error_interrupt()
203 basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_RESET_ACTIVE_U32; in _SI32_ENCDEC_A_reset_module()
229 basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_MOSIZE_LARGE_U32; in _SI32_ENCDEC_A_select_manchester_output_size_large()
242 basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_EDMD_ENCODE_U32; in _SI32_ENCDEC_A_select_encode_mode()
281 basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_OPMD_3OUTOF6_U32; in _SI32_ENCDEC_A_select_three_out_of_six_mode()
294 basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_BEN_ENABLED_U32; in _SI32_ENCDEC_A_enter_bypass_mode()
320 basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_DMAEN_ENABLED_U32; in _SI32_ENCDEC_A_enable_dma_mode()
346 basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_DBGMD_HALT_U32; in _SI32_ENCDEC_A_enable_stall_in_debug_mode()
[all …]
DSI32_LPTIMER_A_Type.h142 basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_CMD_RISING_EDGE_U32;\
157 basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_CMD_FALLING_EDGE_U32;\
171 (basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_CMD_MASK)
196 basePointer->CONTROL_SET = source << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT;\
213 (basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_TMRSET_SET_U32)
245 (basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_TMRCAP_SET_U32)
277 (basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_CMPSET_SET_U32)
309 (basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_CMPCAP_SET_U32)
338 (basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_OVFIEN_ENABLED_U32)
377 (basePointer->CONTROL_SET = SI32_LPTIMER_A_CONTROL_CMPIEN_ENABLED_U32)
[all …]
DSI32_DCDC_A_Type.c168 basePointer->CONTROL_SET = SI32_DCDC_A_CONTROL_OSCDIS_ACTIVE_U32; in _SI32_DCDC_A_disable_dcdc_oscillator()
182 basePointer->CONTROL_SET = SI32_DCDC_A_CONTROL_CLKSEL_MASK; in _SI32_DCDC_A_select_clock_source_apb()
215 basePointer->CONTROL_SET = divider << SI32_DCDC_A_CONTROL_CLKDIV_SHIFT; in _SI32_DCDC_A_select_clock_divider()
229 basePointer->CONTROL_SET = SI32_DCDC_A_CONTROL_ADCSYNCEN_ENABLED_U32; in _SI32_DCDC_A_select_adc_synchronous_mode()
256 basePointer->CONTROL_SET = SI32_DCDC_A_CONTROL_CLKINVEN_ENABLED_U32; in _SI32_DCDC_A_enable_converter_clock_inversion()
284 basePointer->CONTROL_SET = SI32_DCDC_A_CONTROL_ADCCLKINVEN_ENABLED_U32; in _SI32_DCDC_A_enable_adc_clock_inversion()
317 basePointer->CONTROL_SET = voltage << SI32_DCDC_A_CONTROL_OUTVSEL_SHIFT; in _SI32_DCDC_A_select_output_voltage()
330 basePointer->CONTROL_SET = SI32_DCDC_A_CONTROL_MIEN_ENABLED_U32; in _SI32_DCDC_A_enable_interrupt()
361 basePointer->CONTROL_SET = width << SI32_DCDC_A_CONTROL_MINPWSEL_SHIFT; in _SI32_DCDC_A_select_minimum_pulse_width()
379 basePointer->CONTROL_SET = size << SI32_DCDC_A_CONTROL_PSMD_SHIFT; in _SI32_DCDC_A_select_power_switch_size()
[all …]
DSI32_DCDC_A_Type.h211 (basePointer->CONTROL_SET = SI32_DCDC_A_CONTROL_OSCDIS_ACTIVE_U32)
227 (basePointer->CONTROL_SET = SI32_DCDC_A_CONTROL_CLKSEL_MASK)
268 basePointer->CONTROL_SET = divider << SI32_DCDC_A_CONTROL_CLKDIV_SHIFT;\
285 (basePointer->CONTROL_SET = SI32_DCDC_A_CONTROL_ADCSYNCEN_ENABLED_U32)
314 (basePointer->CONTROL_SET = SI32_DCDC_A_CONTROL_CLKINVEN_ENABLED_U32)
344 (basePointer->CONTROL_SET = SI32_DCDC_A_CONTROL_ADCCLKINVEN_ENABLED_U32)
383 basePointer->CONTROL_SET = voltage << SI32_DCDC_A_CONTROL_OUTVSEL_SHIFT;\
397 (basePointer->CONTROL_SET = SI32_DCDC_A_CONTROL_MIEN_ENABLED_U32)
434 basePointer->CONTROL_SET = width << SI32_DCDC_A_CONTROL_MINPWSEL_SHIFT;\
459 basePointer->CONTROL_SET = size << SI32_DCDC_A_CONTROL_PSMD_SHIFT;\
[all …]
DSI32_IDAC_A_Type.h126 basePointer->CONTROL_SET = trigger;\
153 basePointer->CONTROL_SET = trigger_src << SI32_IDAC_A_CONTROL_ETRIG_SHIFT;\
171 basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_OUTMD_2_MA_U32;\
189 basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_OUTMD_1_MA_U32;\
223 basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_INFMT_2_10_BIT_U32;\
257 basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_INFMT_4_8_BIT_U32;\
271 (basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_DMARUN_MASK)
303 (basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_JSEL_MASK)
335 (basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_BUFRESET_MASK)
367 (basePointer->CONTROL_SET = SI32_IDAC_A_CONTROL_TRIGINH_MASK)
[all …]
DSI32_ENCDEC_A_Type.h111 (basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_INRDYIEN_ENABLED_U32)
150 (basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_ORDYIEN_ENABLED_U32)
189 (basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_ERRIEN_ENABLED_U32)
228 (basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_RESET_ACTIVE_U32)
254 (basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_MOSIZE_LARGE_U32)
267 (basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_EDMD_ENCODE_U32)
306 (basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_OPMD_3OUTOF6_U32)
319 (basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_BEN_ENABLED_U32)
345 (basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_DMAEN_ENABLED_U32)
371 (basePointer->CONTROL_SET = SI32_ENCDEC_A_CONTROL_DBGMD_HALT_U32)
[all …]
DSI32_AES_A_Type.h131 (basePointer->CONTROL_SET = SI32_AES_A_CONTROL_XFRSTA_START_U32)
144 (basePointer->CONTROL_SET = SI32_AES_A_CONTROL_KEYCPEN_ENABLED_U32)
170 (basePointer->CONTROL_SET = SI32_AES_A_CONTROL_EDMD_ENCRYPT_U32)
199 (basePointer->CONTROL_SET = SI32_AES_A_CONTROL_SWMDEN_ENABLED_U32)
228 (basePointer->CONTROL_SET = SI32_AES_A_CONTROL_BEN_ENABLED_U32)
268 basePointer->CONTROL_SET = SI32_AES_A_CONTROL_XOREN_XOR_INPUT_U32;\
283 basePointer->CONTROL_SET = SI32_AES_A_CONTROL_XOREN_XOR_OUTPUT_U32;\
297 (basePointer->CONTROL_SET = SI32_AES_A_CONTROL_HCTREN_ENABLED_U32)
323 (basePointer->CONTROL_SET = SI32_AES_A_CONTROL_HCBCEN_ENABLED_U32)
363 basePointer->CONTROL_SET = SI32_AES_A_CONTROL_KEYSIZE_KEY192_U32;\
[all …]
DSI32_CAPSENSE_A_Type.c110 basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_BUSYF_MASK; in _SI32_CAPSENSE_A_start_manual_conversion()
123 basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_CSEN_MASK; in _SI32_CAPSENSE_A_enable_module()
149 basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_BIASEN_MASK; in _SI32_CAPSENSE_A_enable_bias()
175 basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_CMPPOL_MASK; in _SI32_CAPSENSE_A_set_threshold_polarity_to_less_than_or_equal()
215 basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_CMD_SCAN_U32; in _SI32_CAPSENSE_A_select_single_scan_mode()
229 basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_CMD_CONT_SINGLE_U32; in _SI32_CAPSENSE_A_select_continuous_single_conversion_mode()
242 basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_CMD_CONT_SCAN_U32; in _SI32_CAPSENSE_A_select_continuous_scan_mode()
260 basePointer->CONTROL_SET = rate << SI32_CAPSENSE_A_CONTROL_CNVR_SHIFT; in _SI32_CAPSENSE_A_set_conversion_rate()
278 basePointer->CONTROL_SET = samples << SI32_CAPSENSE_A_CONTROL_ACCMD_SHIFT; in _SI32_CAPSENSE_A_set_number_to_accumulate()
295 basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_MCEN_ENABLED_U32; in _SI32_CAPSENSE_A_enter_channels_connected_mode()
[all …]
DSI32_CAPSENSE_A_Type.h160 (basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_BUSYF_MASK)
173 (basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_CSEN_MASK)
199 (basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_BIASEN_MASK)
225 (basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_CMPPOL_MASK)
265 basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_CMD_SCAN_U32;\
280 basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_CMD_CONT_SINGLE_U32;\
294 (basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_CMD_CONT_SCAN_U32)
316 basePointer->CONTROL_SET = rate << SI32_CAPSENSE_A_CONTROL_CNVR_SHIFT;\
339 basePointer->CONTROL_SET = samples << SI32_CAPSENSE_A_CONTROL_ACCMD_SHIFT;\
359 (basePointer->CONTROL_SET = SI32_CAPSENSE_A_CONTROL_MCEN_ENABLED_U32)
[all …]
DSI32_AES_B_Type.h129 (basePointer->CONTROL_SET = SI32_AES_B_CONTROL_XFRSTA_START_U32)
142 (basePointer->CONTROL_SET = SI32_AES_B_CONTROL_KEYCPEN_ENABLED_U32)
168 (basePointer->CONTROL_SET = SI32_AES_B_CONTROL_EDMD_ENCRYPT_U32)
197 (basePointer->CONTROL_SET = SI32_AES_B_CONTROL_SWMDEN_ENABLED_U32)
226 (basePointer->CONTROL_SET = SI32_AES_B_CONTROL_BEN_ENABLED_U32)
266 basePointer->CONTROL_SET = SI32_AES_B_CONTROL_XOREN_XOR_INPUT_U32;\
281 basePointer->CONTROL_SET = SI32_AES_B_CONTROL_XOREN_XOR_OUTPUT_U32;\
295 (basePointer->CONTROL_SET = SI32_AES_B_CONTROL_HCTREN_ENABLED_U32)
321 (basePointer->CONTROL_SET = SI32_AES_B_CONTROL_HCBCEN_ENABLED_U32)
361 basePointer->CONTROL_SET = SI32_AES_B_CONTROL_KEYSIZE_KEY192_U32;\
[all …]
DSI32_AES_A_Type.c90 basePointer->CONTROL_SET = SI32_AES_A_CONTROL_XFRSTA_START_U32; in _SI32_AES_A_start_operation()
103 basePointer->CONTROL_SET = SI32_AES_A_CONTROL_KEYCPEN_ENABLED_U32; in _SI32_AES_A_enable_key_capture()
129 basePointer->CONTROL_SET = SI32_AES_A_CONTROL_EDMD_ENCRYPT_U32; in _SI32_AES_A_select_encryption_mode()
156 basePointer->CONTROL_SET = SI32_AES_A_CONTROL_SWMDEN_ENABLED_U32; in _SI32_AES_A_select_software_mode()
183 basePointer->CONTROL_SET = SI32_AES_A_CONTROL_BEN_ENABLED_U32; in _SI32_AES_A_enter_bypass_hardware_mode()
223 basePointer->CONTROL_SET = SI32_AES_A_CONTROL_XOREN_XOR_INPUT_U32; in _SI32_AES_A_select_xor_path_input()
237 basePointer->CONTROL_SET = SI32_AES_A_CONTROL_XOREN_XOR_OUTPUT_U32; in _SI32_AES_A_select_xor_path_output()
250 basePointer->CONTROL_SET = SI32_AES_A_CONTROL_HCTREN_ENABLED_U32; in _SI32_AES_A_enter_counter_mode()
276 basePointer->CONTROL_SET = SI32_AES_A_CONTROL_HCBCEN_ENABLED_U32; in _SI32_AES_A_enter_cipher_block_chaining_mode()
316 basePointer->CONTROL_SET = SI32_AES_A_CONTROL_KEYSIZE_KEY192_U32; in _SI32_AES_A_select_key_size_192()
[all …]
DSI32_EPCACH_A_Type.c307 basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_COUTST_HIGH_U32; in _SI32_EPCACH_A_set_output_state()
333 basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_CPCAPEN_ENABLED_U32; in _SI32_EPCACH_A_enable_positive_edge_input_capture()
359 basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_CNCAPEN_ENABLED_U32; in _SI32_EPCACH_A_enable_negative_edge_input_capture()
411 basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_YPHST_HIGH_U32; in _SI32_EPCACH_A_select_differential_y_phase_state_high()
437 basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_ACTIVEPH_XACTIVE_U32; in _SI32_EPCACH_A_select_active_x_phase()
463 basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_XPHST_HIGH_U32; in _SI32_EPCACH_A_select_differential_x_phase_state_high()
476 basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_CCIEN_ENABLED_U32; in _SI32_EPCACH_A_enable_capture_compare_interrupt()
515 basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_CCDEN_ENABLED_U32; in _SI32_EPCACH_A_enable_capture_compare_dma_request()
541 basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_CCSEN_ENABLED_U32; in _SI32_EPCACH_A_enable_capture_compare_sync_signal()
567 basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_CIOVFIEN_ENABLED_U32; in _SI32_EPCACH_A_enable_intermediate_overflow_interrupt()
[all …]
DSI32_PLL_A_Type.c188 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_OUTMD_DCO_U32; in _SI32_PLL_A_select_dco_free_running_mode()
202 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_OUTMD_FLL_U32; in _SI32_PLL_A_select_dco_frequency_lock_mode()
215 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_OUTMD_PLL_U32; in _SI32_PLL_A_select_dco_phase_lock_mode()
241 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_EDGSEL_RISING_EDGE_U32; in _SI32_PLL_A_lock_on_rising_edge()
267 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_DITHEN_ENABLED_U32; in _SI32_PLL_A_enable_dither()
293 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_STALL_ENABLED_U32; in _SI32_PLL_A_enable_dco_update_stall()
361 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_REFSEL_LPOSC0DIV_U32; in _SI32_PLL_A_select_reference_clock_source_lp0oscdiv()
375 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_REFSEL_EXTOSC0_U32; in _SI32_PLL_A_select_reference_clock_source_ext0osc()
389 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_REFSEL_USBOSC0_U32; in _SI32_PLL_A_select_reference_clock_source_usb0osc()
403 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_REFSEL_LPOSC0_U32; in _SI32_PLL_A_select_reference_clock_source_lp0osc()
[all …]
DSI32_CRC_A_Type.c85 basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_SINITEN_MASK; in _SI32_CRC_A_initialize_seed_to_zero()
99 basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_SEED_ALL_ONES_U32 in _SI32_CRC_A_initialize_seed_to_one()
113 basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_CRCEN_MASK; in _SI32_CRC_A_enable_module()
153 basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_POLYSEL_CRC_16_1021_U32; in _SI32_CRC_A_select_polynomial_16_bit_1021()
167 basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_POLYSEL_CRC_16_3D65_U32; in _SI32_CRC_A_select_polynomial_16_bit_3D65()
180 basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_POLYSEL_CRC_16_8005_U32; in _SI32_CRC_A_select_polynomial_16_bit_8005()
218 basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_BMDEN_MASK; in _SI32_CRC_A_select_byte_mode()
244 basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_BBREN_MASK; in _SI32_CRC_A_enable_bit_reversal()
276 basePointer->CONTROL_SET = order << SI32_CRC_A_CONTROL_ORDER_SHIFT; in _SI32_CRC_A_set_processing_order()
DSI32_CRC_A_Type.h112 (basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_SINITEN_MASK)
128 basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_SEED_ALL_ONES_U32\
143 (basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_CRCEN_MASK)
183 basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_POLYSEL_CRC_16_1021_U32;\
198 basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_POLYSEL_CRC_16_3D65_U32;\
212 (basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_POLYSEL_CRC_16_8005_U32)
242 (basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_BMDEN_MASK)
268 (basePointer->CONTROL_SET = SI32_CRC_A_CONTROL_BBREN_MASK)
304 basePointer->CONTROL_SET = order << SI32_CRC_A_CONTROL_ORDER_SHIFT;\
DSI32_AES_B_Type.c90 basePointer->CONTROL_SET = SI32_AES_B_CONTROL_XFRSTA_START_U32; in _SI32_AES_B_start_operation()
103 basePointer->CONTROL_SET = SI32_AES_B_CONTROL_KEYCPEN_ENABLED_U32; in _SI32_AES_B_enable_key_capture()
129 basePointer->CONTROL_SET = SI32_AES_B_CONTROL_EDMD_ENCRYPT_U32; in _SI32_AES_B_select_encryption_mode()
156 basePointer->CONTROL_SET = SI32_AES_B_CONTROL_SWMDEN_ENABLED_U32; in _SI32_AES_B_select_software_mode()
183 basePointer->CONTROL_SET = SI32_AES_B_CONTROL_BEN_ENABLED_U32; in _SI32_AES_B_enter_bypass_hardware_mode()
223 basePointer->CONTROL_SET = SI32_AES_B_CONTROL_XOREN_XOR_INPUT_U32; in _SI32_AES_B_select_xor_path_input()
237 basePointer->CONTROL_SET = SI32_AES_B_CONTROL_XOREN_XOR_OUTPUT_U32; in _SI32_AES_B_select_xor_path_output()
250 basePointer->CONTROL_SET = SI32_AES_B_CONTROL_HCTREN_ENABLED_U32; in _SI32_AES_B_enter_counter_mode()
276 basePointer->CONTROL_SET = SI32_AES_B_CONTROL_HCBCEN_ENABLED_U32; in _SI32_AES_B_enter_cipher_block_chaining_mode()
316 basePointer->CONTROL_SET = SI32_AES_B_CONTROL_KEYSIZE_KEY192_U32; in _SI32_AES_B_select_key_size_192()
[all …]
DSI32_ECRC_A_Type.c91 basePointer->CONTROL_SET = SI32_ECRC_A_CONTROL_SINITEN_MASK; in _SI32_ECRC_A_initialize_seed_to_zero()
105 basePointer->CONTROL_SET = SI32_ECRC_A_CONTROL_SEED_ALL_ONES_U32 in _SI32_ECRC_A_initialize_seed_to_one()
119 basePointer->CONTROL_SET = SI32_ECRC_A_CONTROL_CRCEN_MASK; in _SI32_ECRC_A_enable_module()
158 basePointer->CONTROL_SET = SI32_ECRC_A_CONTROL_POLYSEL_MASK; in _SI32_ECRC_A_select_polynomial_programmable_16_bit()
171 basePointer->CONTROL_SET = SI32_ECRC_A_CONTROL_BMDEN_MASK; in _SI32_ECRC_A_select_byte_mode()
197 basePointer->CONTROL_SET = SI32_ECRC_A_CONTROL_BBREN_MASK; in _SI32_ECRC_A_enable_bit_reversal()
235 basePointer->CONTROL_SET = SI32_ECRC_A_CONTROL_ORDER_BIG_ENDIAN_16_U32; in _SI32_ECRC_A_set_processing_order()
239 basePointer->CONTROL_SET = SI32_ECRC_A_CONTROL_ORDER_BIG_ENDIAN_32_U32; in _SI32_ECRC_A_set_processing_order()
271 basePointer->CONTROL_SET = SI32_ECRC_A_CONTROL_ASEEDEN_ENABLED_U32; in _SI32_ECRC_A_enable_autoseed()
310 basePointer->CONTROL_SET = SI32_ECRC_A_CONTROL_ASEEDSEL_MSB_READ_U32; in _SI32_ECRC_A_select_autoseed_after_reading_msb_mode()
DSI32_EPCACH_A_Type.h381 (basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_COUTST_HIGH_U32)
410 (basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_CPCAPEN_ENABLED_U32)
436 (basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_CNCAPEN_ENABLED_U32)
492 (basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_YPHST_HIGH_U32)
518 (basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_ACTIVEPH_XACTIVE_U32)
544 (basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_XPHST_HIGH_U32)
557 (basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_CCIEN_ENABLED_U32)
596 (basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_CCDEN_ENABLED_U32)
622 (basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_CCSEN_ENABLED_U32)
648 (basePointer->CONTROL_SET = SI32_EPCACH_A_CONTROL_CIOVFIEN_ENABLED_U32)
[all …]
DSI32_PLL_A_Type.h257 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_OUTMD_DCO_U32;\
272 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_OUTMD_FLL_U32;\
286 (basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_OUTMD_PLL_U32)
312 (basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_EDGSEL_RISING_EDGE_U32)
338 (basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_DITHEN_ENABLED_U32)
364 (basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_STALL_ENABLED_U32)
436 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_REFSEL_LPOSC0DIV_U32;\
451 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_REFSEL_EXTOSC0_U32;\
466 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_REFSEL_USBOSC0_U32;\
481 basePointer->CONTROL_SET = SI32_PLL_A_CONTROL_REFSEL_LPOSC0_U32;\
[all …]
DSI32_EXTOSC_A_Type.c89 basePointer->CONTROL_SET = freqcn; in _SI32_EXTOSC_A_set_frequency_control_range()
131 basePointer->CONTROL_SET = SI32_EXTOSC_A_CONTROL_OSCMD_CMOS_U32; in _SI32_EXTOSC_A_select_oscillator_mode_cmos()
147 basePointer->CONTROL_SET = SI32_EXTOSC_A_CONTROL_OSCMD_CMOSDIV2_U32; in _SI32_EXTOSC_A_select_oscillator_mode_cmos_div2()
163 basePointer->CONTROL_SET = SI32_EXTOSC_A_CONTROL_OSCMD_RC_U32; in _SI32_EXTOSC_A_select_oscillator_mode_rc_div2()
179 basePointer->CONTROL_SET = SI32_EXTOSC_A_CONTROL_OSCMD_C_U32; in _SI32_EXTOSC_A_select_oscillator_mode_c_div2()
194 basePointer->CONTROL_SET = SI32_EXTOSC_A_CONTROL_OSCMD_XTAL_U32; in _SI32_EXTOSC_A_select_oscillator_mode_crystal()
209 basePointer->CONTROL_SET = SI32_EXTOSC_A_CONTROL_OSCMD_XTALDIV2_U32; in _SI32_EXTOSC_A_select_oscillator_mode_crystal_div2()
DSI32_EXTOSC_A_Type.h117 basePointer->CONTROL_SET = freqcn;\
164 basePointer->CONTROL_SET = SI32_EXTOSC_A_CONTROL_OSCMD_CMOS_U32;\
183 basePointer->CONTROL_SET = SI32_EXTOSC_A_CONTROL_OSCMD_CMOSDIV2_U32;\
202 basePointer->CONTROL_SET = SI32_EXTOSC_A_CONTROL_OSCMD_RC_U32;\
221 basePointer->CONTROL_SET = SI32_EXTOSC_A_CONTROL_OSCMD_C_U32;\
239 basePointer->CONTROL_SET = SI32_EXTOSC_A_CONTROL_OSCMD_XTAL_U32;\
257 (basePointer->CONTROL_SET = SI32_EXTOSC_A_CONTROL_OSCMD_XTALDIV2_U32)

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