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Searched refs:CONTROL_CLR (Results 1 – 25 of 136) sorted by relevance

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/hal_silabs-latest/si32/si32Hal/SI32_Modules/
DSI32_LPTIMER_B_Type.c92 basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_CMD_MASK; in _SI32_LPTIMER_B_select_free_run_mode()
105 basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_CMD_MASK; in _SI32_LPTIMER_B_select_rising_edge_increment_mode()
119 basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_CMD_MASK; in _SI32_LPTIMER_B_select_falling_edge_increment_mode()
151 basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_EXTSEL_MASK; in _SI32_LPTIMER_B_select_timer_source()
234 basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_HSMDEN_MASK; in _SI32_LPTIMER_B_exit_high_speed_timer_access_mode()
260 basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_CMP0EN_MASK; in _SI32_LPTIMER_B_disable_compare0_threshold()
286 basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_CMP1EN_MASK; in _SI32_LPTIMER_B_disable_compare1_threshold()
312 basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_OUTEN_MASK; in _SI32_LPTIMER_B_disable_output()
338 basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_OVFIEN_MASK; in _SI32_LPTIMER_B_disable_overflow_interrupt()
377 basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_CMP0IEN_MASK; in _SI32_LPTIMER_B_disable_compare0_interrupt()
[all …]
DSI32_ENCDEC_A_Type.c99 basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_INRDYIEN_MASK; in _SI32_ENCDEC_A_disable_input_ready_interrupt()
138 basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_ORDYIEN_MASK; in _SI32_ENCDEC_A_disable_output_ready_interrupt()
177 basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_ERRIEN_MASK; in _SI32_ENCDEC_A_disable_error_interrupt()
216 basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_MOSIZE_MASK; in _SI32_ENCDEC_A_select_manchester_output_size_small()
255 basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_EDMD_MASK; in _SI32_ENCDEC_A_select_decode_mode()
268 basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_OPMD_MASK; in _SI32_ENCDEC_A_select_manchester_mode()
307 basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_BEN_MASK; in _SI32_ENCDEC_A_exit_bypass_mode()
333 basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_DMAEN_MASK; in _SI32_ENCDEC_A_disable_dma_mode()
359 basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_DBGMD_MASK; in _SI32_ENCDEC_A_disable_stall_in_debug_mode()
372 basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_OORDER_MASK; in _SI32_ENCDEC_A_select_output_order_no_change()
[all …]
DSI32_LPTIMER_B_Type.h135 (basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_CMD_MASK)
148 basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_CMD_MASK;\
163 basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_CMD_MASK;\
202 basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_EXTSEL_MASK;\
294 (basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_HSMDEN_MASK)
320 (basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_CMP0EN_MASK)
346 (basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_CMP1EN_MASK)
372 (basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_OUTEN_MASK)
398 (basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_OVFIEN_MASK)
437 (basePointer->CONTROL_CLR = SI32_LPTIMER_B_CONTROL_CMP0IEN_MASK)
[all …]
DSI32_IDAC_A_Type.c90 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_OUPDT_MASK; in _SI32_IDAC_A_set_output_update_trigger()
110 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_ETRIG_MASK; in _SI32_IDAC_A_set_external_trigger_channel()
125 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_OUTMD_MASK; in _SI32_IDAC_A_select_output_fullscale_2ma()
140 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_OUTMD_MASK; in _SI32_IDAC_A_select_output_fullscale_1ma()
155 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_OUTMD_MASK; in _SI32_IDAC_A_select_output_fullscale_0p5ma()
169 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_INFMT_MASK; in _SI32_IDAC_A_select_2x10bit_input_format()
184 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_INFMT_MASK; in _SI32_IDAC_A_select_1x10bit_input_format()
198 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_INFMT_MASK; in _SI32_IDAC_A_select_4x8bit_input_format()
253 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_JSEL_MASK; in _SI32_IDAC_A_select_right_justification()
281 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_TRIGINH_MASK; in _SI32_IDAC_A_enable_trigger()
[all …]
DSI32_ENCDEC_A_Type.h124 (basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_INRDYIEN_MASK)
163 (basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_ORDYIEN_MASK)
202 (basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_ERRIEN_MASK)
241 (basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_MOSIZE_MASK)
280 (basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_EDMD_MASK)
293 (basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_OPMD_MASK)
332 (basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_BEN_MASK)
358 (basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_DMAEN_MASK)
384 (basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_DBGMD_MASK)
397 (basePointer->CONTROL_CLR = SI32_ENCDEC_A_CONTROL_OORDER_MASK)
[all …]
DSI32_DCDC_A_Type.c154 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_OSCDIS_MASK; in _SI32_DCDC_A_enable_dcdc_oscillator()
197 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_CLKSEL_MASK; in _SI32_DCDC_A_select_clock_source_local()
214 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_CLKDIV_MASK; in _SI32_DCDC_A_select_clock_divider()
243 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_ADCSYNCEN_MASK; in _SI32_DCDC_A_select_adc_asynchronous_mode()
269 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_CLKINVEN_MASK; in _SI32_DCDC_A_disable_converter_clock_inversion()
297 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_ADCCLKINVEN_MASK; in _SI32_DCDC_A_disable_adc_clock_inversion()
316 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_OUTVSEL_MASK; in _SI32_DCDC_A_select_output_voltage()
343 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_MIEN_MASK; in _SI32_DCDC_A_disable_interrupt()
360 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_MINPWSEL_MASK; in _SI32_DCDC_A_select_minimum_pulse_width()
378 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_PSMD_MASK; in _SI32_DCDC_A_select_power_switch_size()
[all …]
DSI32_DCDC_A_Type.h195 (basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_OSCDIS_MASK)
244 (basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_CLKSEL_MASK)
267 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_CLKDIV_MASK;\
301 (basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_ADCSYNCEN_MASK)
327 (basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_CLKINVEN_MASK)
357 (basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_ADCCLKINVEN_MASK)
382 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_OUTVSEL_MASK;\
410 (basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_MIEN_MASK)
433 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_MINPWSEL_MASK;\
458 basePointer->CONTROL_CLR = SI32_DCDC_A_CONTROL_PSMD_MASK;\
[all …]
DSI32_IDAC_A_Type.h125 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_OUPDT_MASK;\
152 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_ETRIG_MASK;\
170 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_OUTMD_MASK;\
188 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_OUTMD_MASK;\
206 (basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_OUTMD_MASK)
222 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_INFMT_MASK;\
240 (basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_INFMT_MASK)
256 basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_INFMT_MASK;\
319 (basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_JSEL_MASK)
351 (basePointer->CONTROL_CLR = SI32_IDAC_A_CONTROL_TRIGINH_MASK)
[all …]
DSI32_CAPSENSE_A_Type.c136 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CSEN_MASK; in _SI32_CAPSENSE_A_disable_module()
162 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_BIASEN_MASK; in _SI32_CAPSENSE_A_disable_bias()
188 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CMPPOL_MASK; in _SI32_CAPSENSE_A_set_threshold_polarity_to_greater_than()
201 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CMD_MASK; in _SI32_CAPSENSE_A_select_single_conversion_mode()
214 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CMD_MASK; in _SI32_CAPSENSE_A_select_single_scan_mode()
228 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CMD_MASK; in _SI32_CAPSENSE_A_select_continuous_single_conversion_mode()
259 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CNVR_MASK; in _SI32_CAPSENSE_A_set_conversion_rate()
277 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_ACCMD_MASK; in _SI32_CAPSENSE_A_set_number_to_accumulate()
309 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_MCEN_MASK; in _SI32_CAPSENSE_A_exit_channels_connected_mode()
325 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CSCM_MASK; in _SI32_CAPSENSE_A_set_conversion_start_source()
[all …]
DSI32_CAPSENSE_A_Type.h186 (basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CSEN_MASK)
212 (basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_BIASEN_MASK)
238 (basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CMPPOL_MASK)
251 (basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CMD_MASK)
264 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CMD_MASK;\
279 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CMD_MASK;\
315 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CNVR_MASK;\
338 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_ACCMD_MASK;\
375 (basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_MCEN_MASK)
395 basePointer->CONTROL_CLR = SI32_CAPSENSE_A_CONTROL_CSCM_MASK;\
[all …]
DSI32_AES_A_Type.h157 (basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_KEYCPEN_MASK)
183 (basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_EDMD_MASK)
215 (basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_SWMDEN_MASK)
241 (basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_BEN_MASK)
254 (basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_XOREN_MASK)
267 basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_XOREN_MASK;\
282 basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_XOREN_MASK;\
310 (basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_HCTREN_MASK)
336 (basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_HCBCEN_MASK)
349 (basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_KEYSIZE_MASK)
[all …]
DSI32_AES_B_Type.h155 (basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_KEYCPEN_MASK)
181 (basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_EDMD_MASK)
213 (basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_SWMDEN_MASK)
239 (basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_BEN_MASK)
252 (basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_XOREN_MASK)
265 basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_XOREN_MASK;\
280 basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_XOREN_MASK;\
308 (basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_HCTREN_MASK)
334 (basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_HCBCEN_MASK)
347 (basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_KEYSIZE_MASK)
[all …]
DSI32_AES_A_Type.c116 basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_KEYCPEN_MASK; in _SI32_AES_A_disable_key_capture()
142 basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_EDMD_MASK; in _SI32_AES_A_select_decryption_mode()
170 basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_SWMDEN_MASK; in _SI32_AES_A_select_dma_mode()
196 basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_BEN_MASK; in _SI32_AES_A_exit_bypass_hardware_mode()
209 basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_XOREN_MASK; in _SI32_AES_A_select_xor_path_none()
222 basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_XOREN_MASK; in _SI32_AES_A_select_xor_path_input()
236 basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_XOREN_MASK; in _SI32_AES_A_select_xor_path_output()
263 basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_HCTREN_MASK; in _SI32_AES_A_exit_counter_mode()
289 basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_HCBCEN_MASK; in _SI32_AES_A_exit_cipher_block_chaining_mode()
302 basePointer->CONTROL_CLR = SI32_AES_A_CONTROL_KEYSIZE_MASK; in _SI32_AES_A_select_key_size_128()
[all …]
DSI32_PLL_A_Type.c187 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_OUTMD_MASK; in _SI32_PLL_A_select_dco_free_running_mode()
201 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_OUTMD_MASK; in _SI32_PLL_A_select_dco_frequency_lock_mode()
228 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_OUTMD_MASK; in _SI32_PLL_A_select_disable_dco_output()
254 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_EDGSEL_MASK; in _SI32_PLL_A_lock_on_falling_edge()
280 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_DITHEN_MASK; in _SI32_PLL_A_disable_dither()
306 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_STALL_MASK; in _SI32_PLL_A_disable_dco_update_stall()
347 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_REFSEL_MASK; in _SI32_PLL_A_select_reference_clock_source_rtc0osc()
360 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_REFSEL_MASK; in _SI32_PLL_A_select_reference_clock_source_lp0oscdiv()
374 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_REFSEL_MASK; in _SI32_PLL_A_select_reference_clock_source_ext0osc()
388 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_REFSEL_MASK; in _SI32_PLL_A_select_reference_clock_source_usb0osc()
[all …]
DSI32_AES_B_Type.c116 basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_KEYCPEN_MASK; in _SI32_AES_B_disable_key_capture()
142 basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_EDMD_MASK; in _SI32_AES_B_select_decryption_mode()
170 basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_SWMDEN_MASK; in _SI32_AES_B_select_dma_mode()
196 basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_BEN_MASK; in _SI32_AES_B_exit_bypass_hardware_mode()
209 basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_XOREN_MASK; in _SI32_AES_B_select_xor_path_none()
222 basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_XOREN_MASK; in _SI32_AES_B_select_xor_path_input()
236 basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_XOREN_MASK; in _SI32_AES_B_select_xor_path_output()
263 basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_HCTREN_MASK; in _SI32_AES_B_exit_counter_mode()
289 basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_HCBCEN_MASK; in _SI32_AES_B_exit_cipher_block_chaining_mode()
302 basePointer->CONTROL_CLR = SI32_AES_B_CONTROL_KEYSIZE_MASK; in _SI32_AES_B_select_key_size_128()
[all …]
DSI32_PLL_A_Type.h256 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_OUTMD_MASK;\
271 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_OUTMD_MASK;\
299 (basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_OUTMD_MASK)
325 (basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_EDGSEL_MASK)
351 (basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_DITHEN_MASK)
377 (basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_STALL_MASK)
422 (basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_REFSEL_MASK)
435 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_REFSEL_MASK;\
450 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_REFSEL_MASK;\
465 basePointer->CONTROL_CLR = SI32_PLL_A_CONTROL_REFSEL_MASK;\
[all …]
DSI32_LPTIMER_A_Type.c90 basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_CMD_MASK; in _SI32_LPTIMER_A_select_free_run_mode()
103 basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_CMD_MASK; in _SI32_LPTIMER_A_select_rising_edge_increment_mode()
117 basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_CMD_MASK; in _SI32_LPTIMER_A_select_falling_edge_increment_mode()
149 basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_EXTSEL_MASK; in _SI32_LPTIMER_A_select_timer_source()
288 basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_OVFIEN_MASK; in _SI32_LPTIMER_A_disable_overflow_interrupt()
327 basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_CMPIEN_MASK; in _SI32_LPTIMER_A_disable_compare_interrupt()
366 basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_OVFTMD_MASK; in _SI32_LPTIMER_A_disable_output_toggle_upon_overflow()
392 basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_CMPTMD_MASK; in _SI32_LPTIMER_A_disable_output_toggle_upon_compare()
418 basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_CMPRSTEN_MASK; in _SI32_LPTIMER_A_disable_timer_reset_upon_compare()
444 basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_DBGMD_MASK; in _SI32_LPTIMER_A_disable_stall_in_debug_mode()
[all …]
DSI32_EPCACH_A_Type.c294 basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_COUTST_MASK; in _SI32_EPCACH_A_clear_output_state()
346 basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_CPCAPEN_MASK; in _SI32_EPCACH_A_disable_positive_edge_input_capture()
372 basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_CNCAPEN_MASK; in _SI32_EPCACH_A_disable_negative_edge_input_capture()
398 basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_YPHST_MASK; in _SI32_EPCACH_A_select_differential_y_phase_state_low()
424 basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_ACTIVEPH_MASK; in _SI32_EPCACH_A_select_active_y_phase()
450 basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_XPHST_MASK; in _SI32_EPCACH_A_select_differential_x_phase_state_low()
489 basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_CCIEN_MASK; in _SI32_EPCACH_A_disable_capture_compare_interrupt()
528 basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_CCDEN_MASK; in _SI32_EPCACH_A_disable_capture_compare_dma_request()
554 basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_CCSEN_MASK; in _SI32_EPCACH_A_disable_capture_compare_sync_signal()
580 basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_CIOVFIEN_MASK; in _SI32_EPCACH_A_disable_intermediate_overflow_interrupt()
[all …]
DSI32_UART_A_Type.c1007 basePointer->CONTROL_CLR = SI32_UART_A_CONTROL_RFRMERI_MASK; in _SI32_UART_A_clear_rx_frame_error_interrupt()
1033 basePointer->CONTROL_CLR = SI32_UART_A_CONTROL_RPARERI_MASK; in _SI32_UART_A_clear_rx_parity_error_interrupt()
1059 basePointer->CONTROL_CLR = SI32_UART_A_CONTROL_ROREI_MASK; in _SI32_UART_A_clear_rx_overrun_error_interrupt()
1085 basePointer->CONTROL_CLR = SI32_UART_A_CONTROL_RDREQI_MASK; in _SI32_UART_A_clear_rx_data_request_interrupt()
1115 basePointer->CONTROL_CLR = SI32_UART_A_CONTROL_RERIEN_MASK; in _SI32_UART_A_disable_rx_error_interrupts()
1154 basePointer->CONTROL_CLR = SI32_UART_A_CONTROL_RDREQIEN_MASK; in _SI32_UART_A_disable_rx_data_request_interrupt()
1180 basePointer->CONTROL_CLR = SI32_UART_A_CONTROL_MATMD_MASK; in _SI32_UART_A_exit_match_mode()
1193 basePointer->CONTROL_CLR = SI32_UART_A_CONTROL_MATMD_MASK; in _SI32_UART_A_enter_match_mode_store_byte()
1207 basePointer->CONTROL_CLR = SI32_UART_A_CONTROL_MATMD_MASK; in _SI32_UART_A_enter_match_mode_generate_frame_error()
1247 basePointer->CONTROL_CLR = SI32_UART_A_CONTROL_RABDEN_MASK; in _SI32_UART_A_disable_rx_autobaud()
[all …]
DSI32_LPTIMER_A_Type.h128 (basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_CMD_MASK)
141 basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_CMD_MASK;\
156 basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_CMD_MASK;\
195 basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_EXTSEL_MASK;\
351 (basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_OVFIEN_MASK)
390 (basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_CMPIEN_MASK)
429 (basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_OVFTMD_MASK)
455 (basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_CMPTMD_MASK)
481 (basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_CMPRSTEN_MASK)
507 (basePointer->CONTROL_CLR = SI32_LPTIMER_A_CONTROL_DBGMD_MASK)
[all …]
DSI32_EPCACH_A_Type.h368 (basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_COUTST_MASK)
423 (basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_CPCAPEN_MASK)
449 (basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_CNCAPEN_MASK)
479 (basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_YPHST_MASK)
505 (basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_ACTIVEPH_MASK)
531 (basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_XPHST_MASK)
570 (basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_CCIEN_MASK)
609 (basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_CCDEN_MASK)
635 (basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_CCSEN_MASK)
661 (basePointer->CONTROL_CLR = SI32_EPCACH_A_CONTROL_CIOVFIEN_MASK)
[all …]
DSI32_USART_B_Type.c1281 basePointer->CONTROL_CLR = SI32_USART_B_CONTROL_RFRMERI_MASK; in _SI32_USART_B_clear_rx_frame_error_interrupt()
1307 basePointer->CONTROL_CLR = SI32_USART_B_CONTROL_RPARERI_MASK; in _SI32_USART_B_clear_rx_parity_error_interrupt()
1333 basePointer->CONTROL_CLR = SI32_USART_B_CONTROL_ROREI_MASK; in _SI32_USART_B_clear_rx_overrun_error_interrupt()
1359 basePointer->CONTROL_CLR = SI32_USART_B_CONTROL_RDREQI_MASK; in _SI32_USART_B_clear_rx_data_request_interrupt()
1389 basePointer->CONTROL_CLR = SI32_USART_B_CONTROL_RERIEN_MASK; in _SI32_USART_B_disable_rx_error_interrupts()
1428 basePointer->CONTROL_CLR = SI32_USART_B_CONTROL_RDREQIEN_MASK; in _SI32_USART_B_disable_rx_data_request_interrupt()
1454 basePointer->CONTROL_CLR = SI32_USART_B_CONTROL_MATMD_MASK; in _SI32_USART_B_exit_match_mode()
1467 basePointer->CONTROL_CLR = SI32_USART_B_CONTROL_MATMD_MASK; in _SI32_USART_B_enter_match_mode_store_byte()
1481 basePointer->CONTROL_CLR = SI32_USART_B_CONTROL_MATMD_MASK; in _SI32_USART_B_enter_match_mode_generate_frame_error()
1521 basePointer->CONTROL_CLR = SI32_USART_B_CONTROL_RABDEN_MASK; in _SI32_USART_B_disable_rx_autobaud()
[all …]
DSI32_I2C_A_Type.c148 basePointer->CONTROL_CLR = SI32_I2C_A_CONTROL_ACK_MASK; in _SI32_I2C_A_send_nack()
200 basePointer->CONTROL_CLR = SI32_I2C_A_CONTROL_STO_MASK; in _SI32_I2C_A_clear_stop()
239 basePointer->CONTROL_CLR = SI32_I2C_A_CONTROL_STA_MASK; in _SI32_I2C_A_clear_start()
291 basePointer->CONTROL_CLR = SI32_I2C_A_CONTROL_STOI_MASK; in _SI32_I2C_A_clear_stop_interrupt()
317 basePointer->CONTROL_CLR = SI32_I2C_A_CONTROL_ACKI_MASK; in _SI32_I2C_A_clear_ack_interrupt()
343 basePointer->CONTROL_CLR = SI32_I2C_A_CONTROL_RXI_MASK; in _SI32_I2C_A_clear_rx_interrupt()
369 basePointer->CONTROL_CLR = SI32_I2C_A_CONTROL_TXI_MASK; in _SI32_I2C_A_clear_tx_interrupt()
395 basePointer->CONTROL_CLR = SI32_I2C_A_CONTROL_STAI_MASK; in _SI32_I2C_A_clear_start_interrupt()
421 basePointer->CONTROL_CLR = SI32_I2C_A_CONTROL_ARBLI_MASK; in _SI32_I2C_A_clear_arblost_interrupt()
447 basePointer->CONTROL_CLR = SI32_I2C_A_CONTROL_T0I_MASK; in _SI32_I2C_A_clear_timer0_interrupt()
[all …]
DSI32_USART_A_Type.c1254 basePointer->CONTROL_CLR = SI32_USART_A_CONTROL_RFRMERI_MASK; in _SI32_USART_A_clear_rx_frame_error_interrupt()
1280 basePointer->CONTROL_CLR = SI32_USART_A_CONTROL_RPARERI_MASK; in _SI32_USART_A_clear_rx_parity_error_interrupt()
1306 basePointer->CONTROL_CLR = SI32_USART_A_CONTROL_ROREI_MASK; in _SI32_USART_A_clear_rx_overrun_error_interrupt()
1332 basePointer->CONTROL_CLR = SI32_USART_A_CONTROL_RDREQI_MASK; in _SI32_USART_A_clear_rx_data_request_interrupt()
1362 basePointer->CONTROL_CLR = SI32_USART_A_CONTROL_RERIEN_MASK; in _SI32_USART_A_disable_rx_error_interrupts()
1401 basePointer->CONTROL_CLR = SI32_USART_A_CONTROL_RDREQIEN_MASK; in _SI32_USART_A_disable_rx_data_request_interrupt()
1427 basePointer->CONTROL_CLR = SI32_USART_A_CONTROL_MATMD_MASK; in _SI32_USART_A_exit_match_mode()
1440 basePointer->CONTROL_CLR = SI32_USART_A_CONTROL_MATMD_MASK; in _SI32_USART_A_enter_match_mode_store_byte()
1454 basePointer->CONTROL_CLR = SI32_USART_A_CONTROL_MATMD_MASK; in _SI32_USART_A_enter_match_mode_generate_frame_error()
1494 basePointer->CONTROL_CLR = SI32_USART_A_CONTROL_RABDEN_MASK; in _SI32_USART_A_disable_rx_autobaud()
[all …]
DSI32_DTM_A_Type.c101 basePointer->CONTROL_CLR = SI32_DTM_A_CONTROL_STCOUNT_MASK; in _SI32_DTM_A_set_active_state_counter()
133 basePointer->CONTROL_CLR = SI32_DTM_A_CONTROL_ST_MASK; in _SI32_DTM_A_set_active_state()
179 basePointer->CONTROL_CLR = SI32_DTM_A_CONTROL_INHSSEL_MASK; in _SI32_DTM_A_set_inhibit_signal_selection()
236 basePointer->CONTROL_CLR = SI32_DTM_A_CONTROL_DBGMD_MASK; in _SI32_DTM_A_disable_stall_in_debug_mode()
292 basePointer->CONTROL_CLR = SI32_DTM_A_CONTROL_DTMINH_MASK; in _SI32_DTM_A_disable_module_inhibit()
306 basePointer->CONTROL_CLR = SI32_DTM_A_CONTROL_TOERRI_MASK; in _SI32_DTM_A_clear_timeout_error_interrupt()
334 basePointer->CONTROL_CLR = SI32_DTM_A_CONTROL_DMAERRI_MASK; in _SI32_DTM_A_clear_dma_error_interrupt()
362 basePointer->CONTROL_CLR = SI32_DTM_A_CONTROL_DTMI_MASK; in _SI32_DTM_A_clear_module_interrupt()
390 basePointer->CONTROL_CLR = SI32_DTM_A_CONTROL_TOERRI_MASK in _SI32_DTM_A_clear_all_interrupts()
437 basePointer->CONTROL_CLR = SI32_DTM_A_CONTROL_DTMEN_MASK; in _SI32_DTM_A_disable_module()

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