Searched refs:CONTROL0_SET (Results 1 – 9 of 9) sorted by relevance
99 basePointer->CONTROL0_SET = in _SI32_PBCFG_A_select_interrupt_0_pin()126 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0POL_MASK; in _SI32_PBCFG_A_set_interrupt_0_polarity_high()152 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0MD_EDGE_U32 | in _SI32_PBCFG_A_select_interrupt_0_rising_edge_mode()166 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0MD_EDGE_U32; in _SI32_PBCFG_A_select_interrupt_0_falling_edge_mode()180 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0MD_DUAL_EDGE_U32; in _SI32_PBCFG_A_select_interrupt_0_dual_edge_mode()193 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0EN_MASK; in _SI32_PBCFG_A_enable_interrupt_0()224 basePointer->CONTROL0_SET = in _SI32_PBCFG_A_select_interrupt_1_pin()251 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1POL_MASK; in _SI32_PBCFG_A_set_interrupt_1_polarity_high()277 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1MD_EDGE_U32 | in _SI32_PBCFG_A_select_interrupt_1_rising_edge_mode()291 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1MD_EDGE_U32; in _SI32_PBCFG_A_select_interrupt_1_falling_edge_mode()[all …]
152 basePointer->CONTROL0_SET =\180 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0POL_MASK)206 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0MD_EDGE_U32 | \221 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0MD_EDGE_U32;\236 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0MD_DUAL_EDGE_U32)249 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0EN_MASK)286 basePointer->CONTROL0_SET =\314 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1POL_MASK)340 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1MD_EDGE_U32 | \355 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1MD_EDGE_U32;\[all …]
761 volatile uint32_t CONTROL0_SET; member
103 basePointer->CONTROL0_SET = in _SI32_PBCFG_A_select_interrupt_0_pin()130 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0POL_MASK; in _SI32_PBCFG_A_set_interrupt_0_polarity_high()156 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0MD_MASK; in _SI32_PBCFG_A_select_interrupt_0_sensitivity_edge()169 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0EN_MASK; in _SI32_PBCFG_A_enable_interrupt_0()200 basePointer->CONTROL0_SET = in _SI32_PBCFG_A_select_interrupt_1_pin()227 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1POL_MASK; in _SI32_PBCFG_A_set_interrupt_1_polarity_high()253 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1MD_MASK; in _SI32_PBCFG_A_select_interrupt_1_sensitivity_edge()266 basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1EN_MASK; in _SI32_PBCFG_A_enable_interrupt_1()295 basePointer->CONTROL0_SET = in _SI32_PBCFG_A_set_pulse_generator_timer()
165 basePointer->CONTROL0_SET =\193 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0POL_MASK)219 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0MD_MASK)232 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0EN_MASK)269 basePointer->CONTROL0_SET =\297 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1POL_MASK)323 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1MD_MASK)336 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1EN_MASK)369 basePointer->CONTROL0_SET =\
1312 volatile uint32_t CONTROL0_SET; member
163 basePointer->CONTROL0_SET =\191 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0POL_MASK)217 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0MD_MASK)230 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT0EN_MASK)267 basePointer->CONTROL0_SET =\295 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1POL_MASK)321 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1MD_MASK)334 (basePointer->CONTROL0_SET = SI32_PBCFG_A_CONTROL0_INT1EN_MASK)367 basePointer->CONTROL0_SET =\
