Searched refs:CONTROL0_CLR (Results 1 – 9 of 9) sorted by relevance
98 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0SEL_MASK; in _SI32_PBCFG_A_select_interrupt_0_pin()113 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0POL_MASK; in _SI32_PBCFG_A_set_interrupt_0_polarity_low()139 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0MD_MASK; in _SI32_PBCFG_A_select_interrupt_0_level_mode()167 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0POL_MASK; in _SI32_PBCFG_A_select_interrupt_0_falling_edge_mode()206 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0EN_MASK; in _SI32_PBCFG_A_disable_interrupt_0()223 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1SEL_MASK; in _SI32_PBCFG_A_select_interrupt_1_pin()238 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1POL_MASK; in _SI32_PBCFG_A_set_interrupt_1_polarity_low()264 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1MD_MASK; in _SI32_PBCFG_A_select_interrupt_1_level_mode()292 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1POL_MASK; in _SI32_PBCFG_A_select_interrupt_1_falling_edge_mode()331 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1EN_MASK; in _SI32_PBCFG_A_disable_interrupt_1()[all …]
151 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0SEL_MASK;\167 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0POL_MASK)193 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0MD_MASK)222 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0POL_MASK;\262 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0EN_MASK)285 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1SEL_MASK;\301 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1POL_MASK)327 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1MD_MASK)356 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1POL_MASK;\396 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1EN_MASK)[all …]
762 volatile uint32_t CONTROL0_CLR; member
102 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0SEL_MASK; in _SI32_PBCFG_A_select_interrupt_0_pin()117 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0POL_MASK; in _SI32_PBCFG_A_set_interrupt_0_polarity_low()143 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0MD_MASK; in _SI32_PBCFG_A_select_interrupt_0_sensitivity_level()182 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0EN_MASK; in _SI32_PBCFG_A_disable_interrupt_0()199 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1SEL_MASK; in _SI32_PBCFG_A_select_interrupt_1_pin()214 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1POL_MASK; in _SI32_PBCFG_A_set_interrupt_1_polarity_low()240 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1MD_MASK; in _SI32_PBCFG_A_select_interrupt_1_sensitivity_level()279 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1EN_MASK; in _SI32_PBCFG_A_disable_interrupt_1()294 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_PGTIMER_MASK; in _SI32_PBCFG_A_set_pulse_generator_timer()
164 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0SEL_MASK;\180 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0POL_MASK)206 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0MD_MASK)245 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0EN_MASK)268 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1SEL_MASK;\284 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1POL_MASK)310 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1MD_MASK)349 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1EN_MASK)368 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_PGTIMER_MASK;\
1313 volatile uint32_t CONTROL0_CLR; member
162 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0SEL_MASK;\178 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0POL_MASK)204 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0MD_MASK)243 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT0EN_MASK)266 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1SEL_MASK;\282 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1POL_MASK)308 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1MD_MASK)347 (basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_INT1EN_MASK)366 basePointer->CONTROL0_CLR = SI32_PBCFG_A_CONTROL0_PGTIMER_MASK;\
