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Searched refs:CONFIG_SET (Results 1 – 25 of 69) sorted by relevance

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/hal_silabs-latest/si32/si32Hal/SI32_Modules/
DSI32_TIMER_A_Type.c96 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LCLK_APB_U32; in _SI32_TIMER_A_select_low_clock_source_apb_clock()
110 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LCLK_EXTOSCN_U32; in _SI32_TIMER_A_select_low_clock_source_external_oscillator()
124 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LCLK_TIMER_CLKDIV_U32; in _SI32_TIMER_A_select_low_clock_source_timer_clock_divider()
138 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LCLK_CT_FALLING_EDGE_U32; in _SI32_TIMER_A_select_low_clock_source_external_ct_pin()
151 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LMSTREN_MASK; in _SI32_TIMER_A_enable_low_clock_master_synchronization()
177 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_SPLITEN_MASK; in _SI32_TIMER_A_select_split_timer_mode()
203 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LEXIEN_MASK; in _SI32_TIMER_A_enable_low_extra_interrupt()
229 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LOVFIEN_MASK; in _SI32_TIMER_A_enable_low_overflow_interrupt()
269 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LMD_AUTO_RELOAD_U32; in _SI32_TIMER_A_select_low_auto_reload_mode()
283 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LMD_UP_DOWN_U32; in _SI32_TIMER_A_select_low_up_down_mode()
[all …]
DSI32_TIMER_A_Type.h137 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LCLK_APB_U32;\
152 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LCLK_EXTOSCN_U32;\
167 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LCLK_TIMER_CLKDIV_U32;\
182 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LCLK_CT_FALLING_EDGE_U32;\
196 (basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LMSTREN_MASK)
222 (basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_SPLITEN_MASK)
248 (basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LEXIEN_MASK)
274 (basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LOVFIEN_MASK)
314 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LMD_AUTO_RELOAD_U32;\
329 basePointer->CONFIG_SET = SI32_TIMER_A_CONFIG_LMD_UP_DOWN_U32;\
[all …]
DSI32_SPI_A_Type.c548 basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_RFRQIEN_ENABLED_U32; in _SI32_SPI_A_enable_rx_fifo_read_request_interrupt()
587 basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_RFORIEN_ENABLED_U32; in _SI32_SPI_A_enable_rx_fifo_overrun_interrupt()
626 basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_TFRQIEN_ENABLED_U32; in _SI32_SPI_A_enable_tx_fifo_write_request_interrupt()
665 basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_TFORIEN_ENABLED_U32; in _SI32_SPI_A_enable_tx_fifo_overrun_interrupt()
704 basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_SLVSELIEN_ENABLED_U32; in _SI32_SPI_A_enable_slave_selected_interrupt()
743 basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_MDFIEN_ENABLED_U32; in _SI32_SPI_A_enable_mode_fault_interrupt()
782 basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_URIEN_ENABLED_U32; in _SI32_SPI_A_enable_underrun_interrupt()
821 basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_SREIEN_ENABLED_U32; in _SI32_SPI_A_enable_shift_register_empty_interrupt()
860 basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_SPIEN_ENABLED_U32; in _SI32_SPI_A_enable_module()
886 basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_MSTEN_ENABLED_U32; in _SI32_SPI_A_select_master_mode()
[all …]
DSI32_SPI_B_Type.c551 basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_RFRQIEN_ENABLED_U32; in _SI32_SPI_B_enable_rx_fifo_read_request_interrupt()
590 basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_RFORIEN_ENABLED_U32; in _SI32_SPI_B_enable_rx_fifo_overrun_interrupt()
629 basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_TFRQIEN_ENABLED_U32; in _SI32_SPI_B_enable_tx_fifo_write_request_interrupt()
668 basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_TFORIEN_ENABLED_U32; in _SI32_SPI_B_enable_tx_fifo_overrun_interrupt()
707 basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_SLVSELIEN_ENABLED_U32; in _SI32_SPI_B_enable_slave_selected_interrupt()
746 basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_MDFIEN_ENABLED_U32; in _SI32_SPI_B_enable_mode_fault_interrupt()
785 basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_URIEN_ENABLED_U32; in _SI32_SPI_B_enable_underrun_interrupt()
824 basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_SREIEN_ENABLED_U32; in _SI32_SPI_B_enable_shift_register_empty_interrupt()
863 basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_SPIEN_ENABLED_U32; in _SI32_SPI_B_enable_module()
889 basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_MSTEN_ENABLED_U32; in _SI32_SPI_B_select_master_mode()
[all …]
DSI32_SPI_A_Type.h678 (basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_RFRQIEN_ENABLED_U32)
717 (basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_RFORIEN_ENABLED_U32)
756 (basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_TFRQIEN_ENABLED_U32)
795 (basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_TFORIEN_ENABLED_U32)
834 (basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_SLVSELIEN_ENABLED_U32)
873 (basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_MDFIEN_ENABLED_U32)
912 (basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_URIEN_ENABLED_U32)
951 (basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_SREIEN_ENABLED_U32)
990 (basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_SPIEN_ENABLED_U32)
1016 (basePointer->CONFIG_SET = SI32_SPI_A_CONFIG_MSTEN_ENABLED_U32)
[all …]
DSI32_LCD_A_Type.h153 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_LCDEN_MASK;\
154 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_RTCCEN_MASK;\
230 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_BIASEN_MASK;\
255 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_BIASEN_MASK;\
280 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_BIASEN_MASK;\
301 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_CPBEN_MASK;\
324 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_BIASEN_MASK;\
328 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_CPBEN_MASK;\
330 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_CPACEN_MASK;\
354 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_BIASEN_MASK;\
[all …]
DSI32_LCD_A_Type.c101 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_LCDEN_MASK; in _SI32_LCD_A_enable_module()
102 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_RTCCEN_MASK; in _SI32_LCD_A_enable_module()
177 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_BIASEN_MASK; in _SI32_LCD_A_select_2_mux_mode()
202 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_BIASEN_MASK; in _SI32_LCD_A_select_3_mux_mode()
227 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_BIASEN_MASK; in _SI32_LCD_A_select_4_mux_mode()
247 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_CPBEN_MASK; in _SI32_LCD_A_select_auto_contrast_bypass_mode()
270 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_BIASEN_MASK; in _SI32_LCD_A_select_auto_contrast_minimum_contrast_mode()
276 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_CPBEN_MASK; in _SI32_LCD_A_select_auto_contrast_minimum_contrast_mode()
279 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_CPACEN_MASK; in _SI32_LCD_A_select_auto_contrast_minimum_contrast_mode()
302 basePointer->CONFIG_SET = SI32_LCD_A_CONFIG_BIASEN_MASK; in _SI32_LCD_A_select_auto_contrast_constant_contrast_mode()
[all …]
DSI32_SPI_B_Type.h680 (basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_RFRQIEN_ENABLED_U32)
719 (basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_RFORIEN_ENABLED_U32)
758 (basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_TFRQIEN_ENABLED_U32)
797 (basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_TFORIEN_ENABLED_U32)
836 (basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_SLVSELIEN_ENABLED_U32)
875 (basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_MDFIEN_ENABLED_U32)
914 (basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_URIEN_ENABLED_U32)
953 (basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_SREIEN_ENABLED_U32)
992 (basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_SPIEN_ENABLED_U32)
1018 (basePointer->CONFIG_SET = SI32_SPI_B_CONFIG_MSTEN_ENABLED_U32)
[all …]
DSI32_RTC_B_Type.c103 basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_ALM0AREN_ENABLED_U32; in _SI32_RTC_B_enable_alarm0_auto_reset()
129 basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_RUN_START_U32; in _SI32_RTC_B_start_timer()
155 basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_MCLKEN_ENABLED_U32; in _SI32_RTC_B_enable_missing_clock_detector()
181 basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_ASEN_ENABLED_U32; in _SI32_RTC_B_enable_autostep()
210 basePointer->CONFIG_SET = (rtclc << SI32_RTC_B_CONFIG_RTCLC_SHIFT); in _SI32_RTC_B_set_rtc_load_capacitance()
223 basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_BDEN_ENABLED_U32; in _SI32_RTC_B_enable_bias_doubler()
249 basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_CRYSEN_MASK; in _SI32_RTC_B_enable_crystal_oscillator()
275 basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_AGCEN_ENABLED_U32; in _SI32_RTC_B_enable_auto_gain_control()
301 basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_ALM0EN_ENABLED_U32; in _SI32_RTC_B_enable_alarm0()
340 basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_ALM1EN_ENABLED_U32; in _SI32_RTC_B_enable_alarm1()
[all …]
DSI32_RTC_B_Type.h158 (basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_ALM0AREN_ENABLED_U32)
184 (basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_RUN_START_U32)
210 (basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_MCLKEN_ENABLED_U32)
236 (basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_ASEN_ENABLED_U32)
269 basePointer->CONFIG_SET = (rtclc << SI32_RTC_B_CONFIG_RTCLC_SHIFT);\
283 (basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_BDEN_ENABLED_U32)
309 (basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_CRYSEN_MASK)
335 (basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_AGCEN_ENABLED_U32)
361 (basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_ALM0EN_ENABLED_U32)
400 (basePointer->CONFIG_SET = SI32_RTC_B_CONFIG_ALM1EN_ENABLED_U32)
[all …]
DSI32_RTC_A_Type.c103 basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_ALM0AREN_ENABLED_U32; in _SI32_RTC_A_enable_alarm0_auto_reset()
129 basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_RUN_START_U32; in _SI32_RTC_A_start_timer()
155 basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_MCLKEN_ENABLED_U32; in _SI32_RTC_A_enable_missing_clock_detector()
181 basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_ASEN_ENABLED_U32; in _SI32_RTC_A_enable_autostep()
210 basePointer->CONFIG_SET = (rtclc << SI32_RTC_A_CONFIG_RTCLC_SHIFT); in _SI32_RTC_A_set_rtc_load_capacitance()
223 basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_BDEN_ENABLED_U32; in _SI32_RTC_A_enable_bias_doubler()
249 basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_CRYSEN_MASK; in _SI32_RTC_A_enable_crystal_oscillator()
275 basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_AGCEN_ENABLED_U32; in _SI32_RTC_A_enable_auto_gain_control()
301 basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_ALM0EN_ENABLED_U32; in _SI32_RTC_A_enable_alarm0()
340 basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_ALM1EN_ENABLED_U32; in _SI32_RTC_A_enable_alarm1()
[all …]
DSI32_RTC_A_Type.h158 (basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_ALM0AREN_ENABLED_U32)
184 (basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_RUN_START_U32)
210 (basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_MCLKEN_ENABLED_U32)
236 (basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_ASEN_ENABLED_U32)
269 basePointer->CONFIG_SET = (rtclc << SI32_RTC_A_CONFIG_RTCLC_SHIFT);\
283 (basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_BDEN_ENABLED_U32)
309 (basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_CRYSEN_MASK)
335 (basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_AGCEN_ENABLED_U32)
361 (basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_ALM0EN_ENABLED_U32)
400 (basePointer->CONFIG_SET = SI32_RTC_A_CONFIG_ALM1EN_ENABLED_U32)
[all …]
DSI32_USART_B_Type.c105 basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RSTRTEN_ENABLED_U32; in _SI32_USART_B_enable_rx_start_bit()
131 basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RPAREN_ENABLED_U32; in _SI32_USART_B_enable_rx_parity_bit()
157 basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RSTPEN_ENABLED_U32; in _SI32_USART_B_enable_rx_stop_bit()
188 basePointer->CONFIG_SET = bits << SI32_USART_B_CONFIG_RSTPMD_SHIFT; in _SI32_USART_B_select_rx_stop_bits()
205 basePointer->CONFIG_SET = parity << SI32_USART_B_CONFIG_RPARMD_SHIFT; in _SI32_USART_B_select_rx_parity()
223 basePointer->CONFIG_SET = (length - 5) << SI32_USART_B_CONFIG_RDATLN_SHIFT; in _SI32_USART_B_select_rx_data_length()
236 basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RSCEN_ENABLED_U32; in _SI32_USART_B_enable_rx_smartcard_parity_response()
262 basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RIRDAEN_ENABLED_U32; in _SI32_USART_B_enable_rx_irda_mode()
288 basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RINVEN_ENABLED_U32; in _SI32_USART_B_enable_rx_signal_inversion()
327 basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RSYNCEN_ENABLED_U32; in _SI32_USART_B_select_rx_synchronous_mode()
[all …]
DSI32_USART_A_Type.c104 basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RSTRTEN_ENABLED_U32; in _SI32_USART_A_enable_rx_start_bit()
130 basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RPAREN_ENABLED_U32; in _SI32_USART_A_enable_rx_parity_bit()
156 basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RSTPEN_ENABLED_U32; in _SI32_USART_A_enable_rx_stop_bit()
187 basePointer->CONFIG_SET = bits << SI32_USART_A_CONFIG_RSTPMD_SHIFT; in _SI32_USART_A_select_rx_stop_bits()
204 basePointer->CONFIG_SET = parity << SI32_USART_A_CONFIG_RPARMD_SHIFT; in _SI32_USART_A_select_rx_parity()
222 basePointer->CONFIG_SET = (length - 5) << SI32_USART_A_CONFIG_RDATLN_SHIFT; in _SI32_USART_A_select_rx_data_length()
235 basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RSCEN_ENABLED_U32; in _SI32_USART_A_enable_rx_smartcard_parity_response()
261 basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RIRDAEN_ENABLED_U32; in _SI32_USART_A_enable_rx_irda_mode()
287 basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RINVEN_ENABLED_U32; in _SI32_USART_A_enable_rx_signal_inversion()
326 basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RSYNCEN_ENABLED_U32; in _SI32_USART_A_select_rx_synchronous_mode()
[all …]
DSI32_UART_A_Type.c104 basePointer->CONFIG_SET = SI32_UART_A_CONFIG_RSTRTEN_ENABLED_U32; in _SI32_UART_A_enable_rx_start_bit()
130 basePointer->CONFIG_SET = SI32_UART_A_CONFIG_RPAREN_ENABLED_U32; in _SI32_UART_A_enable_rx_parity_bit()
156 basePointer->CONFIG_SET = SI32_UART_A_CONFIG_RSTPEN_ENABLED_U32; in _SI32_UART_A_enable_rx_stop_bit()
187 basePointer->CONFIG_SET = bits << SI32_UART_A_CONFIG_RSTPMD_SHIFT; in _SI32_UART_A_select_rx_stop_bits()
204 basePointer->CONFIG_SET = parity << SI32_UART_A_CONFIG_RPARMD_SHIFT; in _SI32_UART_A_select_rx_parity()
222 basePointer->CONFIG_SET = (length - 5) << SI32_UART_A_CONFIG_RDATLN_SHIFT; in _SI32_UART_A_select_rx_data_length()
235 basePointer->CONFIG_SET = SI32_UART_A_CONFIG_RSCEN_ENABLED_U32; in _SI32_UART_A_enable_rx_smartcard_parity_response()
261 basePointer->CONFIG_SET = SI32_UART_A_CONFIG_RIRDAEN_ENABLED_U32; in _SI32_UART_A_enable_rx_irda_mode()
287 basePointer->CONFIG_SET = SI32_UART_A_CONFIG_RINVEN_ENABLED_U32; in _SI32_UART_A_enable_rx_signal_inversion()
313 basePointer->CONFIG_SET = SI32_UART_A_CONFIG_TSTRTEN_ENABLED_U32; in _SI32_UART_A_enable_tx_start_bit()
[all …]
DSI32_USART_A_Type.h154 (basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RSTRTEN_ENABLED_U32)
180 (basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RPAREN_ENABLED_U32)
206 (basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RSTPEN_ENABLED_U32)
243 basePointer->CONFIG_SET = bits << SI32_USART_A_CONFIG_RSTPMD_SHIFT;\
267 basePointer->CONFIG_SET = parity << SI32_USART_A_CONFIG_RPARMD_SHIFT;\
292 basePointer->CONFIG_SET = (length - 5) << SI32_USART_A_CONFIG_RDATLN_SHIFT;\
306 (basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RSCEN_ENABLED_U32)
332 (basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RIRDAEN_ENABLED_U32)
358 (basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RINVEN_ENABLED_U32)
397 (basePointer->CONFIG_SET = SI32_USART_A_CONFIG_RSYNCEN_ENABLED_U32)
[all …]
DSI32_USART_B_Type.h154 (basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RSTRTEN_ENABLED_U32)
180 (basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RPAREN_ENABLED_U32)
206 (basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RSTPEN_ENABLED_U32)
243 basePointer->CONFIG_SET = bits << SI32_USART_B_CONFIG_RSTPMD_SHIFT;\
267 basePointer->CONFIG_SET = parity << SI32_USART_B_CONFIG_RPARMD_SHIFT;\
292 basePointer->CONFIG_SET = (length - 5) << SI32_USART_B_CONFIG_RDATLN_SHIFT;\
306 (basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RSCEN_ENABLED_U32)
332 (basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RIRDAEN_ENABLED_U32)
358 (basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RINVEN_ENABLED_U32)
397 (basePointer->CONFIG_SET = SI32_USART_B_CONFIG_RSYNCEN_ENABLED_U32)
[all …]
DSI32_UART_A_Type.h154 (basePointer->CONFIG_SET = SI32_UART_A_CONFIG_RSTRTEN_ENABLED_U32)
180 (basePointer->CONFIG_SET = SI32_UART_A_CONFIG_RPAREN_ENABLED_U32)
206 (basePointer->CONFIG_SET = SI32_UART_A_CONFIG_RSTPEN_ENABLED_U32)
243 basePointer->CONFIG_SET = bits << SI32_UART_A_CONFIG_RSTPMD_SHIFT;\
267 basePointer->CONFIG_SET = parity << SI32_UART_A_CONFIG_RPARMD_SHIFT;\
292 basePointer->CONFIG_SET = (length - 5) << SI32_UART_A_CONFIG_RDATLN_SHIFT;\
306 (basePointer->CONFIG_SET = SI32_UART_A_CONFIG_RSCEN_ENABLED_U32)
332 (basePointer->CONFIG_SET = SI32_UART_A_CONFIG_RIRDAEN_ENABLED_U32)
358 (basePointer->CONFIG_SET = SI32_UART_A_CONFIG_RINVEN_ENABLED_U32)
384 (basePointer->CONFIG_SET = SI32_UART_A_CONFIG_TSTRTEN_ENABLED_U32)
[all …]
DSI32_I2C_A_Type.c931 basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_STOIEN_ENABLED_U32; in _SI32_I2C_A_enable_stop_interrupt()
970 basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_ACKIEN_ENABLED_U32; in _SI32_I2C_A_enable_ack_interrupt()
1009 basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_RXIEN_ENABLED_U32; in _SI32_I2C_A_enable_rx_interrupt()
1048 basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_TXIEN_ENABLED_U32; in _SI32_I2C_A_enable_tx_interrupt()
1087 basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_STAIEN_ENABLED_U32; in _SI32_I2C_A_enable_start_interrupt()
1126 basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_ARBLIEN_MASK; in _SI32_I2C_A_enable_arblost_interrupt()
1166 basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_T0IEN_ENABLED_U32; in _SI32_I2C_A_enable_timer0_interrupt()
1206 basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_T1IEN_ENABLED_U32; in _SI32_I2C_A_enable_timer1_interrupt()
1246 basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_T2IEN_ENABLED_U32; in _SI32_I2C_A_enable_timer2_interrupt()
1286 basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_T3IEN_ENABLED_U32; in _SI32_I2C_A_enable_timer3_interrupt()
[all …]
DSI32_UART_B_Type.c108 basePointer->CONFIG_SET = SI32_UART_B_CONFIG_RSTRTEN_ENABLED_U32; in _SI32_UART_B_enable_rx_start_bit()
134 basePointer->CONFIG_SET = SI32_UART_B_CONFIG_RPAREN_ENABLED_U32; in _SI32_UART_B_enable_rx_parity_bit()
160 basePointer->CONFIG_SET = SI32_UART_B_CONFIG_RSTPEN_ENABLED_U32; in _SI32_UART_B_enable_rx_stop_bit()
191 basePointer->CONFIG_SET = bits << SI32_UART_B_CONFIG_RSTPMD_SHIFT; in _SI32_UART_B_select_rx_stop_bits()
208 basePointer->CONFIG_SET = parity << SI32_UART_B_CONFIG_RPARMD_SHIFT; in _SI32_UART_B_select_rx_parity()
226 basePointer->CONFIG_SET = (length - 5) << SI32_UART_B_CONFIG_RDATLN_SHIFT; in _SI32_UART_B_select_rx_data_length()
239 basePointer->CONFIG_SET = SI32_UART_B_CONFIG_RIRDAEN_ENABLED_U32; in _SI32_UART_B_enable_rx_irda_mode()
265 basePointer->CONFIG_SET = SI32_UART_B_CONFIG_RINVEN_ENABLED_U32; in _SI32_UART_B_enable_rx_signal_inversion()
291 basePointer->CONFIG_SET = SI32_UART_B_CONFIG_TSTRTEN_ENABLED_U32; in _SI32_UART_B_enable_tx_start_bit()
317 basePointer->CONFIG_SET = SI32_UART_B_CONFIG_TPAREN_ENABLED_U32; in _SI32_UART_B_enable_tx_parity_bit()
[all …]
DSI32_FLASHCTRL_A_Type.c94 basePointer->CONFIG_SET = mode; in _SI32_FLASHCTRL_A_select_flash_speed_mode()
108 basePointer->CONFIG_SET = SI32_FLASHCTRL_A_CONFIG_RDSEN_ENABLED_U32; in _SI32_FLASHCTRL_A_enter_read_store_mode()
137 basePointer->CONFIG_SET = SI32_FLASHCTRL_A_CONFIG_DPFEN_ENABLED_U32; in _SI32_FLASHCTRL_A_enable_data_prefetch()
179 basePointer->CONFIG_SET = SI32_FLASHCTRL_A_CONFIG_PFINH_ACTIVE_U32; in _SI32_FLASHCTRL_A_disable_prefetch()
197 basePointer->CONFIG_SET = SI32_FLASHCTRL_A_CONFIG_SQWEN_MASK; in _SI32_FLASHCTRL_A_enter_multi_byte_write_mode()
227 basePointer->CONFIG_SET = SI32_FLASHCTRL_A_CONFIG_ERASEEN_ENABLED_U32; in _SI32_FLASHCTRL_A_enter_flash_erase_mode()
DSI32_I2C_A_Type.h1044 (basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_STOIEN_ENABLED_U32)
1083 (basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_ACKIEN_ENABLED_U32)
1122 (basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_RXIEN_ENABLED_U32)
1161 (basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_TXIEN_ENABLED_U32)
1200 (basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_STAIEN_ENABLED_U32)
1239 (basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_ARBLIEN_MASK)
1281 (basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_T0IEN_ENABLED_U32)
1323 (basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_T1IEN_ENABLED_U32)
1365 (basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_T2IEN_ENABLED_U32)
1407 (basePointer->CONFIG_SET = SI32_I2C_A_CONFIG_T3IEN_ENABLED_U32)
[all …]
DSI32_EMIFIF_A_Type.h152 (basePointer->CONFIG_SET = SI32_EMIFIF_A_CONFIG_BUSWIDTH_MASK)
165 (basePointer->CONFIG_SET = SI32_EMIFIF_A_CONFIG_MUXMD_MASK)
191 (basePointer->CONFIG_SET = SI32_EMIFIF_A_CONFIG_ASEN_MASK)
217 (basePointer->CONFIG_SET = SI32_EMIFIF_A_CONFIG_ROEN_MASK)
256 (basePointer->CONFIG_SET = SI32_EMIFIF_A_CONFIG_WDHINH_MASK)
269 (basePointer->CONFIG_SET = SI32_EMIFIF_A_CONFIG_DELAYOE_MASK)
295 (basePointer->CONFIG_SET = SI32_EMIFIF_A_CONFIG_KLREN_MASK)
DSI32_FLASHCTRL_A_Type.h128 basePointer->CONFIG_SET = mode;\
145 (basePointer->CONFIG_SET = SI32_FLASHCTRL_A_CONFIG_RDSEN_ENABLED_U32)
178 (basePointer->CONFIG_SET = SI32_FLASHCTRL_A_CONFIG_DPFEN_ENABLED_U32)
226 (basePointer->CONFIG_SET = SI32_FLASHCTRL_A_CONFIG_PFINH_ACTIVE_U32)
246 (basePointer->CONFIG_SET = SI32_FLASHCTRL_A_CONFIG_SQWEN_MASK)
280 (basePointer->CONFIG_SET = SI32_FLASHCTRL_A_CONFIG_ERASEEN_ENABLED_U32)
DSI32_UART_B_Type.h161 (basePointer->CONFIG_SET = SI32_UART_B_CONFIG_RSTRTEN_ENABLED_U32)
187 (basePointer->CONFIG_SET = SI32_UART_B_CONFIG_RPAREN_ENABLED_U32)
213 (basePointer->CONFIG_SET = SI32_UART_B_CONFIG_RSTPEN_ENABLED_U32)
250 basePointer->CONFIG_SET = bits << SI32_UART_B_CONFIG_RSTPMD_SHIFT;\
274 basePointer->CONFIG_SET = parity << SI32_UART_B_CONFIG_RPARMD_SHIFT;\
299 basePointer->CONFIG_SET = (length - 5) << SI32_UART_B_CONFIG_RDATLN_SHIFT;\
313 (basePointer->CONFIG_SET = SI32_UART_B_CONFIG_RIRDAEN_ENABLED_U32)
339 (basePointer->CONFIG_SET = SI32_UART_B_CONFIG_RINVEN_ENABLED_U32)
365 (basePointer->CONFIG_SET = SI32_UART_B_CONFIG_TSTRTEN_ENABLED_U32)
391 (basePointer->CONFIG_SET = SI32_UART_B_CONFIG_TPAREN_ENABLED_U32)
[all …]

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