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Searched refs:CONFIG_CLR (Results 1 – 25 of 69) sorted by relevance

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/hal_silabs-latest/si32/si32Hal/SI32_Modules/
DSI32_TIMER_A_Type.c95 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LCLK_MASK; in _SI32_TIMER_A_select_low_clock_source_apb_clock()
109 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LCLK_MASK; in _SI32_TIMER_A_select_low_clock_source_external_oscillator()
123 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LCLK_MASK; in _SI32_TIMER_A_select_low_clock_source_timer_clock_divider()
137 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LCLK_MASK; in _SI32_TIMER_A_select_low_clock_source_external_ct_pin()
164 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LMSTREN_MASK; in _SI32_TIMER_A_disable_low_clock_master_synchronization()
190 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_SPLITEN_MASK; in _SI32_TIMER_A_select_single_timer_mode()
216 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LEXIEN_MASK; in _SI32_TIMER_A_disable_low_extra_interrupt()
242 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LOVFIEN_MASK; in _SI32_TIMER_A_disable_low_overflow_interrupt()
268 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LMD_MASK; in _SI32_TIMER_A_select_low_auto_reload_mode()
282 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LMD_MASK; in _SI32_TIMER_A_select_low_up_down_mode()
[all …]
DSI32_TIMER_A_Type.h136 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LCLK_MASK;\
151 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LCLK_MASK;\
166 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LCLK_MASK;\
181 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LCLK_MASK;\
209 (basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LMSTREN_MASK)
235 (basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_SPLITEN_MASK)
261 (basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LEXIEN_MASK)
287 (basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LOVFIEN_MASK)
313 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LMD_MASK;\
328 basePointer->CONFIG_CLR = SI32_TIMER_A_CONFIG_LMD_MASK;\
[all …]
DSI32_SPI_A_Type.c561 basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_RFRQIEN_MASK; in _SI32_SPI_A_disable_rx_fifo_read_request_interrupt()
600 basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_RFORIEN_MASK; in _SI32_SPI_A_disable_rx_fifo_overrun_interrupt()
639 basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_TFRQIEN_MASK; in _SI32_SPI_A_disable_tx_fifo_write_request_interrupt()
678 basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_TFORIEN_MASK; in _SI32_SPI_A_disable_tx_fifo_overrun_interrupt()
717 basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_SLVSELIEN_MASK; in _SI32_SPI_A_disable_slave_selected_interrupt()
756 basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_MDFIEN_MASK; in _SI32_SPI_A_disable_mode_fault_interrupt()
795 basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_URIEN_MASK; in _SI32_SPI_A_disable_underrun_interrupt()
834 basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_SREIEN_MASK; in _SI32_SPI_A_disable_shift_register_empty_interrupt()
873 basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_SPIEN_MASK; in _SI32_SPI_A_disable_module()
899 basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_MSTEN_MASK; in _SI32_SPI_A_select_slave_mode()
[all …]
DSI32_SPI_B_Type.c564 basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_RFRQIEN_MASK; in _SI32_SPI_B_disable_rx_fifo_read_request_interrupt()
603 basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_RFORIEN_MASK; in _SI32_SPI_B_disable_rx_fifo_overrun_interrupt()
642 basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_TFRQIEN_MASK; in _SI32_SPI_B_disable_tx_fifo_write_request_interrupt()
681 basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_TFORIEN_MASK; in _SI32_SPI_B_disable_tx_fifo_overrun_interrupt()
720 basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_SLVSELIEN_MASK; in _SI32_SPI_B_disable_slave_selected_interrupt()
759 basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_MDFIEN_MASK; in _SI32_SPI_B_disable_mode_fault_interrupt()
798 basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_URIEN_MASK; in _SI32_SPI_B_disable_underrun_interrupt()
837 basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_SREIEN_MASK; in _SI32_SPI_B_disable_shift_register_empty_interrupt()
876 basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_SPIEN_MASK; in _SI32_SPI_B_disable_module()
902 basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_MSTEN_MASK; in _SI32_SPI_B_select_slave_mode()
[all …]
DSI32_SPI_A_Type.h691 (basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_RFRQIEN_MASK)
730 (basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_RFORIEN_MASK)
769 (basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_TFRQIEN_MASK)
808 (basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_TFORIEN_MASK)
847 (basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_SLVSELIEN_MASK)
886 (basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_MDFIEN_MASK)
925 (basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_URIEN_MASK)
964 (basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_SREIEN_MASK)
1003 (basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_SPIEN_MASK)
1029 (basePointer->CONFIG_CLR = SI32_SPI_A_CONFIG_MSTEN_MASK)
[all …]
DSI32_RTC_B_Type.c116 basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_ALM0AREN_MASK; in _SI32_RTC_B_disable_alarm0_auto_reset()
142 basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_RUN_MASK; in _SI32_RTC_B_stop_timer()
168 basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_MCLKEN_MASK; in _SI32_RTC_B_disable_missing_clock_detector()
194 basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_ASEN_MASK; in _SI32_RTC_B_disable_autostep()
209 basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_RTCLC_MASK; in _SI32_RTC_B_set_rtc_load_capacitance()
236 basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_BDEN_MASK; in _SI32_RTC_B_disable_bias_doubler()
262 basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_CRYSEN_MASK; in _SI32_RTC_B_disable_crystal_oscillator()
288 basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_AGCEN_MASK; in _SI32_RTC_B_disable_auto_gain_control()
314 basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_ALM0EN_MASK; in _SI32_RTC_B_disable_alarm0()
353 basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_ALM1EN_MASK; in _SI32_RTC_B_disable_alarm1()
[all …]
DSI32_LCD_A_Type.h168 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_LCDEN_MASK;\
169 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_RTCCEN_MASK;\
299 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPFPDEN_MASK;\
303 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPACEN_MASK;\
326 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPFPDEN_MASK;\
358 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPBEN_MASK;\
388 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPBEN_MASK;\
390 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPACEN_MASK;\
460 (basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPFPDEN_MASK)
486 (basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_MCDEN_MASK)
[all …]
DSI32_RTC_B_Type.h171 (basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_ALM0AREN_MASK)
197 (basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_RUN_MASK)
223 (basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_MCLKEN_MASK)
249 (basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_ASEN_MASK)
268 basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_RTCLC_MASK;\
296 (basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_BDEN_MASK)
322 (basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_CRYSEN_MASK)
348 (basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_AGCEN_MASK)
374 (basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_ALM0EN_MASK)
413 (basePointer->CONFIG_CLR = SI32_RTC_B_CONFIG_ALM1EN_MASK)
[all …]
DSI32_SPI_B_Type.h693 (basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_RFRQIEN_MASK)
732 (basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_RFORIEN_MASK)
771 (basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_TFRQIEN_MASK)
810 (basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_TFORIEN_MASK)
849 (basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_SLVSELIEN_MASK)
888 (basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_MDFIEN_MASK)
927 (basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_URIEN_MASK)
966 (basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_SREIEN_MASK)
1005 (basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_SPIEN_MASK)
1031 (basePointer->CONFIG_CLR = SI32_SPI_B_CONFIG_MSTEN_MASK)
[all …]
DSI32_LCD_A_Type.c115 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_LCDEN_MASK; in _SI32_LCD_A_disable_module()
116 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_RTCCEN_MASK; in _SI32_LCD_A_disable_module()
244 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPFPDEN_MASK; in _SI32_LCD_A_select_auto_contrast_bypass_mode()
250 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPACEN_MASK; in _SI32_LCD_A_select_auto_contrast_bypass_mode()
273 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPFPDEN_MASK; in _SI32_LCD_A_select_auto_contrast_minimum_contrast_mode()
308 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPBEN_MASK; in _SI32_LCD_A_select_auto_contrast_constant_contrast_mode()
340 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPBEN_MASK; in _SI32_LCD_A_select_auto_contrast_auto_bypass_mode()
343 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPACEN_MASK; in _SI32_LCD_A_select_auto_contrast_auto_bypass_mode()
404 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_CPFPDEN_MASK; in _SI32_LCD_A_disable_charge_pump_full_drive_mode()
430 basePointer->CONFIG_CLR = SI32_LCD_A_CONFIG_MCDEN_MASK; in _SI32_LCD_A_disable_lcd_missing_clock_detector()
[all …]
DSI32_RTC_A_Type.c116 basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_ALM0AREN_MASK; in _SI32_RTC_A_disable_alarm0_auto_reset()
142 basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_RUN_MASK; in _SI32_RTC_A_stop_timer()
168 basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_MCLKEN_MASK; in _SI32_RTC_A_disable_missing_clock_detector()
194 basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_ASEN_MASK; in _SI32_RTC_A_disable_autostep()
209 basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_RTCLC_MASK; in _SI32_RTC_A_set_rtc_load_capacitance()
236 basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_BDEN_MASK; in _SI32_RTC_A_disable_bias_doubler()
262 basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_CRYSEN_MASK; in _SI32_RTC_A_disable_crystal_oscillator()
288 basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_AGCEN_MASK; in _SI32_RTC_A_disable_auto_gain_control()
314 basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_ALM0EN_MASK; in _SI32_RTC_A_disable_alarm0()
353 basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_ALM1EN_MASK; in _SI32_RTC_A_disable_alarm1()
[all …]
DSI32_RTC_A_Type.h171 (basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_ALM0AREN_MASK)
197 (basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_RUN_MASK)
223 (basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_MCLKEN_MASK)
249 (basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_ASEN_MASK)
268 basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_RTCLC_MASK;\
296 (basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_BDEN_MASK)
322 (basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_CRYSEN_MASK)
348 (basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_AGCEN_MASK)
374 (basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_ALM0EN_MASK)
413 (basePointer->CONFIG_CLR = SI32_RTC_A_CONFIG_ALM1EN_MASK)
[all …]
DSI32_USART_B_Type.c118 basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RSTRTEN_MASK; in _SI32_USART_B_disable_rx_start_bit()
144 basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RPAREN_MASK; in _SI32_USART_B_disable_rx_parity_bit()
170 basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RSTPEN_MASK; in _SI32_USART_B_disable_rx_stop_bit()
187 basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RSTPMD_MASK; in _SI32_USART_B_select_rx_stop_bits()
204 basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RPARMD_MASK; in _SI32_USART_B_select_rx_parity()
222 basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RDATLN_MASK; in _SI32_USART_B_select_rx_data_length()
249 basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RSCEN_MASK; in _SI32_USART_B_disable_rx_smartcard_parity_response()
275 basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RIRDAEN_MASK; in _SI32_USART_B_disable_rx_irda_mode()
301 basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RINVEN_MASK; in _SI32_USART_B_disable_rx_signal_inversion()
314 basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RSYNCEN_MASK; in _SI32_USART_B_select_rx_asynchronous_mode()
[all …]
DSI32_USART_A_Type.c117 basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RSTRTEN_MASK; in _SI32_USART_A_disable_rx_start_bit()
143 basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RPAREN_MASK; in _SI32_USART_A_disable_rx_parity_bit()
169 basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RSTPEN_MASK; in _SI32_USART_A_disable_rx_stop_bit()
186 basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RSTPMD_MASK; in _SI32_USART_A_select_rx_stop_bits()
203 basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RPARMD_MASK; in _SI32_USART_A_select_rx_parity()
221 basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RDATLN_MASK; in _SI32_USART_A_select_rx_data_length()
248 basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RSCEN_MASK; in _SI32_USART_A_disable_rx_smartcard_parity_response()
274 basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RIRDAEN_MASK; in _SI32_USART_A_disable_rx_irda_mode()
300 basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RINVEN_MASK; in _SI32_USART_A_disable_rx_signal_inversion()
313 basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RSYNCEN_MASK; in _SI32_USART_A_select_rx_asynchronous_mode()
[all …]
DSI32_UART_A_Type.c117 basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RSTRTEN_MASK; in _SI32_UART_A_disable_rx_start_bit()
143 basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RPAREN_MASK; in _SI32_UART_A_disable_rx_parity_bit()
169 basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RSTPEN_MASK; in _SI32_UART_A_disable_rx_stop_bit()
186 basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RSTPMD_MASK; in _SI32_UART_A_select_rx_stop_bits()
203 basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RPARMD_MASK; in _SI32_UART_A_select_rx_parity()
221 basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RDATLN_MASK; in _SI32_UART_A_select_rx_data_length()
248 basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RSCEN_MASK; in _SI32_UART_A_disable_rx_smartcard_parity_response()
274 basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RIRDAEN_MASK; in _SI32_UART_A_disable_rx_irda_mode()
300 basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RINVEN_MASK; in _SI32_UART_A_disable_rx_signal_inversion()
326 basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_TSTRTEN_MASK; in _SI32_UART_A_disable_tx_start_bit()
[all …]
DSI32_USART_A_Type.h167 (basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RSTRTEN_MASK)
193 (basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RPAREN_MASK)
219 (basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RSTPEN_MASK)
242 basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RSTPMD_MASK;\
266 basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RPARMD_MASK;\
291 basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RDATLN_MASK;\
319 (basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RSCEN_MASK)
345 (basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RIRDAEN_MASK)
371 (basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RINVEN_MASK)
384 (basePointer->CONFIG_CLR = SI32_USART_A_CONFIG_RSYNCEN_MASK)
[all …]
DSI32_USART_B_Type.h167 (basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RSTRTEN_MASK)
193 (basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RPAREN_MASK)
219 (basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RSTPEN_MASK)
242 basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RSTPMD_MASK;\
266 basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RPARMD_MASK;\
291 basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RDATLN_MASK;\
319 (basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RSCEN_MASK)
345 (basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RIRDAEN_MASK)
371 (basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RINVEN_MASK)
384 (basePointer->CONFIG_CLR = SI32_USART_B_CONFIG_RSYNCEN_MASK)
[all …]
DSI32_UART_A_Type.h167 (basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RSTRTEN_MASK)
193 (basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RPAREN_MASK)
219 (basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RSTPEN_MASK)
242 basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RSTPMD_MASK;\
266 basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RPARMD_MASK;\
291 basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RDATLN_MASK;\
319 (basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RSCEN_MASK)
345 (basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RIRDAEN_MASK)
371 (basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_RINVEN_MASK)
397 (basePointer->CONFIG_CLR = SI32_UART_A_CONFIG_TSTRTEN_MASK)
[all …]
DSI32_I2C_A_Type.c944 basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_STOIEN_MASK; in _SI32_I2C_A_disable_stop_interrupt()
983 basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_ACKIEN_MASK; in _SI32_I2C_A_disable_ack_interrupt()
1022 basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_RXIEN_MASK; in _SI32_I2C_A_disable_rx_interrupt()
1061 basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_TXIEN_MASK; in _SI32_I2C_A_disable_tx_interrupt()
1100 basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_STAIEN_MASK; in _SI32_I2C_A_disable_start_interrupt()
1139 basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_ARBLIEN_MASK; in _SI32_I2C_A_disable_arblost_interrupt()
1179 basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_T0IEN_MASK; in _SI32_I2C_A_disable_timer0_interrupt()
1219 basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_T1IEN_MASK; in _SI32_I2C_A_disable_timer1_interrupt()
1259 basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_T2IEN_MASK; in _SI32_I2C_A_disable_timer2_interrupt()
1299 basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_T3IEN_MASK; in _SI32_I2C_A_disable_timer3_interrupt()
[all …]
DSI32_UART_B_Type.c121 basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RSTRTEN_MASK; in _SI32_UART_B_disable_rx_start_bit()
147 basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RPAREN_MASK; in _SI32_UART_B_disable_rx_parity_bit()
173 basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RSTPEN_MASK; in _SI32_UART_B_disable_rx_stop_bit()
190 basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RSTPMD_MASK; in _SI32_UART_B_select_rx_stop_bits()
207 basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RPARMD_MASK; in _SI32_UART_B_select_rx_parity()
225 basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RDATLN_MASK; in _SI32_UART_B_select_rx_data_length()
252 basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RIRDAEN_MASK; in _SI32_UART_B_disable_rx_irda_mode()
278 basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RINVEN_MASK; in _SI32_UART_B_disable_rx_signal_inversion()
304 basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_TSTRTEN_MASK; in _SI32_UART_B_disable_tx_start_bit()
330 basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_TPAREN_MASK; in _SI32_UART_B_disable_tx_parity_bit()
[all …]
DSI32_FLASHCTRL_A_Type.c93 basePointer->CONFIG_CLR = SI32_FLASHCTRL_A_CONFIG_SPMD_MASK; in _SI32_FLASHCTRL_A_select_flash_speed_mode()
123 basePointer->CONFIG_CLR = SI32_FLASHCTRL_A_CONFIG_RDSEN_MASK; in _SI32_FLASHCTRL_A_exit_read_store_mode()
151 basePointer->CONFIG_CLR = SI32_FLASHCTRL_A_CONFIG_DPFEN_MASK; in _SI32_FLASHCTRL_A_disable_data_prefetch()
165 basePointer->CONFIG_CLR = SI32_FLASHCTRL_A_CONFIG_PFINH_MASK; in _SI32_FLASHCTRL_A_enable_prefetch()
212 basePointer->CONFIG_CLR = SI32_FLASHCTRL_A_CONFIG_SQWEN_MASK; in _SI32_FLASHCTRL_A_exit_multi_byte_write_mode()
242 basePointer->CONFIG_CLR = SI32_FLASHCTRL_A_CONFIG_ERASEEN_MASK; in _SI32_FLASHCTRL_A_exit_flash_erase_mode()
DSI32_I2C_A_Type.h1057 (basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_STOIEN_MASK)
1096 (basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_ACKIEN_MASK)
1135 (basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_RXIEN_MASK)
1174 (basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_TXIEN_MASK)
1213 (basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_STAIEN_MASK)
1252 (basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_ARBLIEN_MASK)
1294 (basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_T0IEN_MASK)
1336 (basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_T1IEN_MASK)
1378 (basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_T2IEN_MASK)
1420 (basePointer->CONFIG_CLR = SI32_I2C_A_CONFIG_T3IEN_MASK)
[all …]
DSI32_EMIFIF_A_Type.h139 (basePointer->CONFIG_CLR = SI32_EMIFIF_A_CONFIG_BUSWIDTH_MASK)
178 (basePointer->CONFIG_CLR = SI32_EMIFIF_A_CONFIG_MUXMD_MASK)
204 (basePointer->CONFIG_CLR = SI32_EMIFIF_A_CONFIG_ASEN_MASK)
230 (basePointer->CONFIG_CLR = SI32_EMIFIF_A_CONFIG_ROEN_MASK)
243 (basePointer->CONFIG_CLR = SI32_EMIFIF_A_CONFIG_WDHINH_MASK)
282 (basePointer->CONFIG_CLR = SI32_EMIFIF_A_CONFIG_DELAYOE_MASK)
308 (basePointer->CONFIG_CLR = SI32_EMIFIF_A_CONFIG_KLREN_MASK)
DSI32_FLASHCTRL_A_Type.h127 basePointer->CONFIG_CLR = SI32_FLASHCTRL_A_CONFIG_SPMD_MASK;\
162 (basePointer->CONFIG_CLR = SI32_FLASHCTRL_A_CONFIG_RDSEN_MASK)
194 (basePointer->CONFIG_CLR = SI32_FLASHCTRL_A_CONFIG_DPFEN_MASK)
210 (basePointer->CONFIG_CLR = SI32_FLASHCTRL_A_CONFIG_PFINH_MASK)
263 (basePointer->CONFIG_CLR = SI32_FLASHCTRL_A_CONFIG_SQWEN_MASK)
297 (basePointer->CONFIG_CLR = SI32_FLASHCTRL_A_CONFIG_ERASEEN_MASK)
DSI32_UART_B_Type.h174 (basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RSTRTEN_MASK)
200 (basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RPAREN_MASK)
226 (basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RSTPEN_MASK)
249 basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RSTPMD_MASK;\
273 basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RPARMD_MASK;\
298 basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RDATLN_MASK;\
326 (basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RIRDAEN_MASK)
352 (basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_RINVEN_MASK)
378 (basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_TSTRTEN_MASK)
404 (basePointer->CONFIG_CLR = SI32_UART_B_CONFIG_TPAREN_MASK)
[all …]

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