Searched refs:CLK_ENABLE_SET_REG1 (Results 1 – 3 of 3) sorted by relevance
1189 pCLK->CLK_ENABLE_SET_REG1 = flags; in clk_peripheral_clk_enable1()1516 pCLK->CLK_ENABLE_SET_REG1 = QSPI_2_M4_SOC_SYNC; in clk_qspi_2_clk_config()2506 pCLK->CLK_ENABLE_SET_REG1 = (USART1_SCLK_ENABLE | USART1_PCLK_ENABLE); in clk_peripheral_clk_enable()2515 pCLK->CLK_ENABLE_SET_REG1 = (USART2_SCLK_ENABLE | USART2_PCLK_ENABLE); in clk_peripheral_clk_enable()2544 pCLK->CLK_ENABLE_SET_REG1 = CT_CLK_ENABLE; in clk_peripheral_clk_enable()2546 pCLK->CLK_ENABLE_SET_REG1 = CT_PCLK_ENABLE; in clk_peripheral_clk_enable()2554 pCLK->CLK_ENABLE_SET_REG1 = SD_MEM_INTF_CLK_ENABLE; in clk_peripheral_clk_enable()2558 pCLK->CLK_ENABLE_SET_REG1 = (CCI_CLK_ENABLE | CCI_HCLK_ENABLE); in clk_peripheral_clk_enable()2561 pCLK->CLK_ENABLE_SET_REG1 = CCI_PCLK_ENABLE; in clk_peripheral_clk_enable()2585 pCLK->CLK_ENABLE_SET_REG1 = (QSPI_2_CLK_ENABLE | QSPI_2_HCLK_ENABLE); in clk_peripheral_clk_enable()[all …]
57 pCLK->CLK_ENABLE_SET_REG1 = ULPSS_CLK_ENABLE; in ulpss_clock_config()
9896 __IOM unsigned int CLK_ENABLE_SET_REG1; /*!< (@ 0x00000000) Clock Enable Set member
