1 /*******************************************************************************
2 * @file rsi_pll.h
3 *******************************************************************************
4 * # License
5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
6 *******************************************************************************
7 *
8 * SPDX-License-Identifier: Zlib
9 *
10 * The licensor of this software is Silicon Laboratories Inc.
11 *
12 * This software is provided 'as-is', without any express or implied
13 * warranty. In no event will the authors be held liable for any damages
14 * arising from the use of this software.
15 *
16 * Permission is granted to anyone to use this software for any purpose,
17 * including commercial applications, and to alter it and redistribute it
18 * freely, subject to the following restrictions:
19 *
20 * 1. The origin of this software must not be misrepresented; you must not
21 * claim that you wrote the original software. If you use this software
22 * in a product, an acknowledgment in the product documentation would be
23 * appreciated but is not required.
24 * 2. Altered source versions must be plainly marked as such, and must not be
25 * misrepresented as being the original software.
26 * 3. This notice may not be removed or altered from any source distribution.
27 *
28 ******************************************************************************/
29
30 /**
31 * Includes
32 */
33 #ifndef __RSI_PLL_H__
34 #define __RSI_PLL_H__
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 #include "rsi_ccp_common.h"
41 #include "rsi_error.h"
42 #include "rsi_ipmu.h"
43 #include "rsi_reg_spi.h"
44
45 #define MISC_CFG_MISC_CTRL (*((uint32_t volatile *)(MISC_CONFIG_BASE + 0x14)))
46
47 typedef void (*cdDelay)(uint32_t delay);
48
49 #define CCI_SYNC_MODE BIT(16) /* Enables CCI_SYNC_MODE */
50 /*M4 Clock configuration base address */
51
52 /*SET Reg 1 SET / CLR*/
53 #define USART1_PCLK_ENABLE BIT(0) /* Enables USART1_PCLK_ENABLE */
54 #define USART1_SCLK_ENABLE BIT(1) /* Enables USART1_SCLK_ENABLE */
55 #define USART2_PCLK_ENABLE BIT(2) /* Enables USART2_PCLK_ENABLE */
56 #define USART2_SCLK_ENABLE BIT(3) /* Enables USART2_SCLK_ENABLE */
57 #if defined(SLI_SI917B0) || defined(SLI_SI915)
58 #define QSPI_2_CLK_ENABLE BIT(4) /* Enables QSPI_CLK_ENABLE */
59 #define QSPI_2_HCLK_ENABLE BIT(5) /* Enables QSPI_HCLK_ENABLE */
60 #define QSPI_2_M4_SOC_SYNC BIT(6) /* Enables QSPI_M4_SOC_SYNC */
61 #define QSPI_2_CLK_ONEHOT_ENABLE BIT(7) /* Enables QSPI_CLK_ONEHOT_ENABLE */
62 #endif
63 #define CT_CLK_ENABLE BIT(9) /* Enables CT_CLK_ENABLE */
64 #define CT_PCLK_ENABLE BIT(10) /* Enables CT_PCLK_ENABLE */
65 #define ICACHE_CLK_ENABLE BIT(11) /* Enables ICACHE_CLK_ENABLE */
66 #define ICACHE_CLK_2X_ENABLE BIT(12) /* Enables ICACHE_CLK_2X_ENABLE */
67 #define RPDMA_HCLK_ENABLE BIT(13) /* Enables RPDMA_HCLK_ENABLE */
68 #define SOC_PLL_SPI_CLK_ENABLE BIT(14) /* Enables SOC_PLL_SPI_CLK_ENABLE */
69 #define IID_CLK_ENABLE BIT(16) /* Enables IID_CLK_ENABLE */
70 #define SDIO_SYS_HCLK_ENABLE BIT(17) /* Enables SDIO_SYS_HCLK_ENABLE */
71 #define CRC_CLK_ENABLE_M4 BIT(18) /* Enables CRC_CLK_ENABLE_M4 */
72 #define M4SS_UM_CLK_STATIC_EN BIT(19) /* Enables M4SS_UM_CLK_STATIC_EN */
73 #define ETH_HCLK_ENABLE BIT(21) /* Enables ETH_HCLK_ENABLE */
74 #define HWRNG_PCLK_ENABLE BIT(22) /* Enables HWRNG_PCLK_ENABLE */
75 #define GNSS_MEM_CLK_ENABLE BIT(23) /* Enables GNSS_MEM_CLK_ENABLE */
76 #define CCI_PCLK_ENABLE BIT(24) /* Enables CCI_PCLK_ENABLE */
77 #define CCI_HCLK_ENABLE BIT(25) /* Enables CCI_HCLK_ENABLE */
78 #define CCI_CLK_ENABLE BIT(26) /* Enables CCI_CLK_ENABLE */
79 #define MASK_HOST_CLK_WAIT_FIX BIT(27) /* Enables MASK_HOST_CLK_WAIT_FIX */
80 #define MASK31_HOST_CLK_CNT BIT(28) /* Enables MASK31_HOST_CLK_CNT */
81 #define SD_MEM_INTF_CLK_ENABLE \
82 BIT(29) /* Static Clock gating Enable for sd_mem_intf clk1'b1 => Clock is enabled1'b0 => Invalid*/
83 #define MASK_HOST_CLK_AVAILABLE_FIX BIT(30) /* Enables MASK_HOST_CLK_AVAILABLE_FIX */
84 #define ULPSS_CLK_ENABLE BIT(31) /* Enables ULPSS_CLK_ENABLE */
85
86 /*SER Reg2 SET / CLR*/
87 #define GEN_SPI_MST1_HCLK_ENABLE BIT(0) /* Enables GEN_SPI_MST1_HCLK_ENABLE */
88 #define CAN1_PCLK_ENABLE BIT(2) /* Enables CAN1_PCLK_ENABLE */
89 #define CAN1_CLK_ENABLE BIT(3) /* Enables CAN1_CLK_ENABLE */
90 #define UDMA_HCLK_ENABLE BIT(6) /* Enables UDMA_HCLK_ENABLE */
91 #define I2C_BUS_CLK_ENABLE BIT(7) /* Enables I2C_1_BUS_CLK_ENABLE */
92 #define I2C_2_BUS_CLK_ENABLE BIT(8) /* Enables I2C_2_BUS_CLK_ENABLE */
93 #define SSI_SLV_PCLK_ENABLE BIT(9) /* Enables SSI_SLV_PCLK_ENABLE */
94 #define SSI_SLV_SCLK_ENABLE BIT(10) /* Enables SSI_SLV_SCLK_ENABLE */
95 #define QSPI_CLK_ENABLE BIT(11) /* Enables QSPI_CLK_ENABLE */
96 #define QSPI_HCLK_ENABLE BIT(12) /* Enables QSPI_HCLK_ENABLE */
97 #define I2SM_SCLK_ENABLE BIT(13) /* Enables I2SM_SCLK_ENABLE */
98 #define I2SM_INTF_SCLK_ENABLE BIT(14) /* Enables I2SM_INTF_SCLK_ENABLE */
99 #define I2SM_PCLK_ENABLE BIT(15) /* Enables I2SM_PCLK_ENABLE */
100 #define QE_PCLK_ENABLE BIT(17) /* Enables QE_PCLK_ENABLE */
101 #define MCPWM_PCLK_ENABLE BIT(18) /* Enables MCPWM_PCLK_ENABLE */
102 #define SGPIO_PCLK_ENABLE BIT(20) /* Enables SGPIO_PCLK_ENABLE */
103 #define EGPIO_PCLK_ENABLE BIT(21) /* Enables EGPIO_PCLK_ENABLE */
104 #define ARM_CLK_ENABLE BIT(22) /* Enables ARM_CLK_ENABLE */
105 #define SSI_MST_PCLK_ENABLE BIT(23) /* Enables SSI_MST_PCLK_ENABLE */
106 #define SSI_MST_SCLK_ENABLE BIT(24) /* Enables SSI_MST_SCLK_ENABLE */
107 #define MEM2_CLK_ENABLE BIT(25) /* Enables MEM2_CLK_ENABLE */
108 #define MEM_CLK_ULP_ENABLE BIT(26) /* Enables MEM_CLK_ULP_ENABLE */
109 #define ROM_CLK_ENABLE BIT(27) /* Enables ROM_CLK_ENABLE */
110 #define PLL_INTF_CLK_ENABLE BIT(28) /* Enables PLL_INTF_CLK_ENABLE */
111 #define SEMAPHORE_CLK_ENABLE BIT(29) /* Enables SEMAPHORE_CLK_ENABLE */
112 #define TOT_CLK_ENABLE BIT(30) /* Enables TOT_CLK_ENABLE */
113 #define RMII_SOFT_RESET BIT(31) /* Enables RMII_SOFT_RESET */
114
115 /*SET Reg 3 SET / CLR*/
116 #define BUS_CLK_ENABLE BIT(0) /* Enables BUS_CLK_ENABLE */
117 #define M4_CORE_CLK_ENABLE BIT(1) /* Enables M4_CORE_CLK_ENABLE */
118 #define CM_BUS_CLK_ENABLE BIT(2) /* Enables CM_BUS_CLK_ENABLE */
119 #define MISC_CONFIG_PCLK_ENABLE BIT(4) /* Enables MISC_CONFIG_PCLK_ENABLE */
120 #define EFUSE_CLK_ENABLE BIT(5) /* Enables EFUSE_CLK_ENABLE */
121 #define ICM_CLK_ENABLE BIT(6) /* Enables ICM_CLK_ENABLE */
122 #define MEM1_CLK_ENABLE BIT(7) /* Enables MEM1_CLK_ENABLE */
123 #define MEM3_CLK_ENABLE BIT(8) /* Enables MEM3_CLK_ENABLE */
124 #define USB_PHY_CLK_IN_ENABLE BIT(12) /* Enables USB_PHY_CLK_IN_ENABLE */
125 #define QSPI_CLK_ONEHOT_ENABLE BIT(13) /* Enables QSPI_CLK_ONEHOT_ENABLE */
126 #define QSPI_M4_SOC_SYNC BIT(14) /* Enables QSPI_M4_SOC_SYNC */
127 #define EGPIO_CLK_ENABLE BIT(16) /* Enables EGPIO_CLK_ENABLE */
128 #define I2C_CLK_ENABLE BIT(17) /* Enables I2C_CLK_ENABLE */
129 #define I2C_2_CLK_ENABLE BIT(18) /* Enables I2C_2_CLK_ENABLE */
130 #define EFUSE_PCLK_ENABLE BIT(19) /* Enables EFUSE_PCLK_ENABLE */
131 #define SGPIO_CLK_ENABLE BIT(20) /* Enables SGPIO_CLK_ENABLE */
132 #define TASS_M4SS_64K_SWITCH_CLK_ENABLE BIT(21) /* Enables TASS_M4SS_64K_SWITCH_CLK_ENABLE */
133 #define TASS_M4SS_128K_SWITCH_CLK_ENABLE BIT(22) /* Enables TASS_M4SS_128K_SWITCH_CLK_ENABLE */
134 #define TASS_M4SS_SDIO_SWITCH_CLK_ENABLE BIT(23) /* Enables TASS_M4SS_SDIO_SWITCH_CLK_ENABLE */
135 #define TASS_M4SS_USB_SWITCH_CLK_ENABLE BIT(24) /* Enables TASS_M4SS_USB_SWITCH_CLK_ENABLE */
136 #define ROM_MISC_STATIC_ENABLE BIT(25) /* Enables ROM_MISC_STATIC_ENABLE */
137 #define M4_SOC_CLK_FOR_OTHER_ENABLE BIT(26) /* Enables M4_SOC_CLK_FOR_OTHER_ENABLE */
138 #define ICACHE_ENABLE BIT(27) /* Enables ICACHE_ENABLE */
139
140 /*DYN_CLK_GATE_DISABLE_REG */
141
142 #define SDIO_SYS_HCLK_DYN_CTRL_DISABLE BIT(0) /* Enables SDIO_SYS_HCLK_DYN_CTRL_DISABLE */
143 #define BUS_CLK_DYN_CTRL_DISABLE BIT(1) /* Enables BUS_CLK_DYN_CTRL_DISABLE */
144 #define GPDMA_HCLK_DYN_CTRL_DISABLE BIT(4) /* Enables GPDMA_HCLK_DYN_CTRL_DISABLE */
145 #define EGPIO_PCLK_DYN_CTRL_DISABLE BIT(5) /* Enables EGPIO_PCLK_DYN_CTRL_DISABLE */
146 #define SGPIO_PCLK_DYN_CTRL_DISABLE BIT(6) /* Enables SGPIO_PCLK_DYN_CTRL_DISABLE */
147 #define TOT_CLK_DYN_CTRL_DISABLE BIT(7) /* Enables TOT_CLK_DYN_CTRL_DISABLE */
148 #define HWRNG_PCLK_DYN_CTRL_DISABLE BIT(8) /* Enables HWRNG_PCLK_DYN_CTRL_DISABLE */
149 #define USART1_SCLK_DYN_CTRL_DISABLE BIT(9) /* Enables USART1_SCLK_DYN_CTRL_DISABLE */
150 #define USART1_PCLK_DYN_CTRL_DISABLE BIT(10) /* Enables USART1_PCLK_DYN_CTRL_DISABLE */
151 #define USART2_SCLK_DYN_CTRL_DISABLE BIT(11) /* Enables USART2_SCLK_DYN_CTRL_DISABLE */
152 #define USART2_PCLK_DYN_CTRL_DISABLE BIT(12) /* Enables USART2_PCLK_DYN_CTRL_DISABLE */
153 #define SSI_SLV_SCLK_DYN_CTRL_DISABLE BIT(15) /* Enables SSI_SLV_SCLK_DYN_CTRL_DISABLE */
154 #define SSI_SLV_PCLK_DYN_CTRL_DISABLE BIT(16) /* Enables SSI_SLV_PCLK_DYN_CTRL_DISABLE */
155 #define I2SM_INTF_SCLK_DYN_CTRL_DISABLE BIT(18) /* Enables I2SM_INTF_SCLK_DYN_CTRL_DISABLE */
156 #define SEMAPHORE_CLK_DYN_CTRL_DISABLE BIT(19) /* Enables SEMAPHORE_CLK_DYN_CTRL_DISABLE */
157 #define ARM_CLK_DYN_CTRL_DISABLE BIT(20) /* Enables ARM_CLK_DYN_CTRL_DISABLE */
158 #define SSI_MST_SCLK_DYN_CTRL_DISABLE BIT(21) /* Enables SSI_MST_SCLK_DYN_CTRL_DISABLE */
159 #define MEM1_CLK_DYN_CTRL_DISABLE BIT(22) /* Enables MEM1_CLK_DYN_CTRL_DISABLE */
160 #define MEM2_CLK_DYN_CTRL_DISABLE BIT(23) /* Enables MEM2_CLK_DYN_CTRL_DISABLE */
161 #define MEM_CLK_ULP_DYN_CTRL_DISABLE BIT(24) /* Enables MEM_CLK_ULP_DYN_CTRL_DISABLE */
162 #define MEM3_CLK_DYN_CTRL_DISABLE BIT(25) /* Enables MEM3_CLK_DYN_CTRL_DISABLE */
163 #define SSI_MST_PCLK_DYN_CTRL_DISABLE BIT(28) /* Enables SSI_MST_PCLK_DYN_CTRL_DISABLE */
164 #define ICACHE_DYN_GATING_DISABLE BIT(29) /* Enables ICACHE_DYN_GATING_DISABLE */
165 #define CCI_PCLK_DYN_CTRL_DISABLE BIT(30) /* Enables CCI_PCLK_DYN_CTRL_DISABLE */
166 #define MISC_CONFIG_PCLK_DYN_CTRL_DISABLE BIT(31) /* Enables MISC_CONFIG_PCLK_DYN_CTRL_DISABLE */
167
168 /*DYN_CLK_GATE_DISABLE_REG2 */
169 #define SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE BIT(0) /* Enables SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE */
170 #define I2C_BUS_DYN_CTRL_DISABLE BIT(1) /* Enables I2C_BUS_DYN_CTRL_DISABLE */
171 #define I2C_2_BUS_CLK_DYN_CTRL_DISABLE BIT(2) /* Enables I2C_2_BUS_CLK_DYN_CTRL_DISABLE */
172 #define CT_PCLK_DYN_CTRL_DISABLE BIT(3) /* Enables SCT_PCLK_DYN_CTRL_DISABLE */
173 #define CAN1_PCLK_DYN_CTRL_DISABLE BIT(4) /* Enables CAN1_PCLK_DYN_CTRL_DISABLE */
174 #define I2SM_PCLK_DYN_CTRL_DISABLE BIT(5) /* Enables I2SM_PCLK_DYN_CTRL_DISABLE */
175 #define EFUSE_CLK_DYN_CTRL_DISABLE BIT(6) /* Enables EFUSE_CLK_DYN_CTRL_DISABLE */
176 #define EFUSE_PCLK_DYN_CTRL_DISABLE BIT(7) /* Enables EFUSE_PCLK_DYN_CTRL_DISABLE */
177 #define PWR_CTRL_CLK_DYN_CTRL_DISABLE BIT(8) /* Enables PWR_CTRL_CLK_DYN_CTRL_DISABLE */
178
179 /*SOC_Pll Clock frequency checks */
180 #define SOC_PLL_MIN_FREQUECY 1000000 /* Minimum frequency for SOC_PLL*/
181 #define SOC_PLL_MAX_FREQUECY 300000000 /* Maximum frequency for SOC_PLL*/
182
183 /*SOC_Pll Clock frequency checks */
184 #define INTF_PLL_MIN_FREQUECY 1000000 /* Minimum frequency for SOC_PLL*/
185 #define INTF_PLL_MAX_FREQUECY 300000000 /* Maximum frequency for SOC_PLL*/
186
187 #define I2S_DCO_FREQ1 73728000 /* i2s_dco_freq1*/
188 #define I2S_DCO_FREQ2 67737600 /* i2s_dco_freq2*/
189
190 /*SOCPLL_MACRO_REG_ACCESS*/
191 #define SOCPLLMACROREG1 0x00 /* Address for SOCPLLMACROREG1 register Access*/
192 #define SOCPLLMACROREG2 0x01 /* Address for SOCPLLMACROREG2 register Access*/
193 #define SOCPLLMACROREG3 0x02 /* Address for SOCPLLMACROREG3 register Access*/
194 #define SOCPLLMACROREG4 0x03 /* Address for SOCPLLMACROREG4 register Access*/
195 #define SOCPLLMACROREG5 0x04 /* Address for SOCPLLMACROREG5 register Access*/
196
197 /*SOCPLLMACROREG*/
198 #define LDO_PROG_SOCPLL (0xE000) /* Mask value for LDO_PROG_SOCPLL*/
199 #define LDO_PROG_INTFPLL (0x1C00) /* Mask value for LDO_PROG_INTFPLL*/
200 #define LDO_PROG_I2SPLL (0x0380) /* Mask value for LDO_PROG_I2SPLL*/
201
202 /* SOC_PLL_REG_ACCESS */
203 #define SOC_PLL_500_CTRL_REG1 0x10 /* Address for SOC_PLL_500_CTRL_REG1 register Access*/
204 #define SOC_PLL_500_CTRL_REG2 0x11 /* Address for SOC_PLL_500_CTRL_REG2 register Access*/
205 #define SOC_PLL_500_CTRL_REG3 0x12 /* Address for SOC_PLL_500_CTRL_REG3 register Access*/
206 #define SOC_PLL_500_CTRL_REG4 0x13 /* Address for SOC_PLL_500_CTRL_REG4 register Access*/
207 #define SOC_PLL_500_CTRL_REG5 0x14 /* Address for SOC_PLL_500_CTRL_REG5 register Access*/
208 #define SOC_PLL_500_CTRL_REG6 0x15 /* Address for SOC_PLL_500_CTRL_REG6 register Access*/
209 #define SOC_PLL_500_CTRL_REG7 0x16 /* Address for SOC_PLL_500_CTRL_REG7 register Access*/
210 #define SOC_PLL_500_CTRL_REG8 0x17 /* Address for SOC_PLL_500_CTRL_REG8 register Access*/
211 #define SOC_PLL_500_CTRL_REG9 0x18 /* Address for SOC_PLL_500_CTRL_REG9 register Access*/
212 #define SOC_PLL_500_CTRL_REG10 0x19 /* Address for SOC_PLL_500_CTRL_REG10 register Access*/
213 #define SOC_PLL_500_CTRL_REG11 0x1A /* Address for SOC_PLL_500_CTRL_REG11 register Access*/
214 #define SOC_PLL_500_CTRL_REG12 0x1B /* Address for SOC_PLL_500_CTRL_REG12 register Access*/
215 #define SOC_PLL_500_CTRL_REG13 0x1C /* Address for SOC_PLL_500_CTRL_REG13 register Access*/
216
217 /* INTF_PLL_REG_ACCESS */
218 #define INTF_PLL_500_CTRL_REG1 0x20 /* Address for INTF_PLL_500_CTRL_REG1 register Access*/
219 #define INTF_PLL_500_CTRL_REG2 0x21 /* Address for INTF_PLL_500_CTRL_REG2 register Access*/
220 #define INTF_PLL_500_CTRL_REG3 0x22 /* Address for INTF_PLL_500_CTRL_REG3 register Access*/
221 #define INTF_PLL_500_CTRL_REG4 0x23 /* Address for INTF_PLL_500_CTRL_REG4 register Access*/
222 #define INTF_PLL_500_CTRL_REG5 0x24 /* Address for INTF_PLL_500_CTRL_REG5 register Access*/
223 #define INTF_PLL_500_CTRL_REG6 0x25 /* Address for INTF_PLL_500_CTRL_REG6 register Access*/
224 #define INTF_PLL_500_CTRL_REG7 0x26 /* Address for INTF_PLL_500_CTRL_REG7 register Access*/
225 #define INTF_PLL_500_CTRL_REG8 0x27 /* Address for INTF_PLL_500_CTRL_REG8 register Access*/
226 #define INTF_PLL_500_CTRL_REG9 0x28 /* Address for INTF_PLL_500_CTRL_REG9 register Access*/
227 #define INTF_PLL_500_CTRL_REG10 0x29 /* Address for INTF_PLL_500_CTRL_REG10 register Access*/
228 #define INTF_PLL_500_CTRL_REG11 0x2A /* Address for INTF_PLL_500_CTRL_REG11 register Access*/
229 #define INTF_PLL_500_CTRL_REG12 0x2B /* Address for INTF_PLL_500_CTRL_REG12 register Access*/
230 #define INTF_PLL_500_CTRL_REG13 0x2C /* Address for INTF_PLL_500_CTRL_REG13 register Access*/
231
232 /* I2S_PLL_REG_ACCESS */
233 #define I2S_PLL_CTRL_REG1 0x30 /* Address for I2S_PLL_CTRL_REG1 register Access*/
234 #define I2S_PLL_CTRL_REG2 0x31 /* Address for I2S_PLL_CTRL_REG2 register Access*/
235 #define I2S_PLL_CTRL_REG3 0x32 /* Address for I2S_PLL_CTRL_REG3 register Access*/
236 #define I2S_PLL_CTRL_REG4 0x33 /* Address for I2S_PLL_CTRL_REG4 register Access*/
237 #define I2S_PLL_CTRL_REG5 0x34 /* Address for I2S_PLL_CTRL_REG5 register Access*/
238 #define I2S_PLL_CTRL_REG6 0x35 /* Address for I2S_PLL_CTRL_REG6 register Access*/
239 #define I2S_PLL_CTRL_REG7 0x36 /* Address for I2S_PLL_CTRL_REG7 register Access*/
240 #define I2S_PLL_CTRL_REG8 0x37 /* Address for I2S_PLL_CTRL_REG8 register Access*/
241 #define I2S_PLL_CTRL_REG9 0x38 /* Address for I2S_PLL_CTRL_REG9 register Access*/
242 #define I2S_PLL_CTRL_REG10 0x39 /* Address for I2S_PLL_CTRL_REG10 register Access*/
243 #define I2S_PLL_CTRL_REG11 0x3A /* Address for I2S_PLL_CTRL_REG11 register Access*/
244 #define I2S_PLL_CTRL_REG12 0x3B /* Address for I2S_PLL_CTRL_REG12 register Access*/
245 #define I2S_PLL_CTRL_REG13 0x3C /* Address for I2S_PLL_CTRL_REG13 register Access*/
246
247 /* AFE_PLL_CTRL_REG_REG_ACCESS */
248 #define AFEPLLCTRLREG1 0x07 /* Address for AFEPLLCTRLREG1 register Access*/
249 #define AFEPLLCTRLREG2 0x08 /* Address for AFEPLLCTRLREG1 register Access*/
250
251 #define MEMS_REF_CLK_ENABLE BIT(6)
252
253 /*SOC_PLL_500_CTRL_REG1/INTF_PLL_500_CTRL_REG1/I2S_PLL_CTRL_REG_1 */
254 #define DCO_FIX_SEL_MASK (0x0003) /* Mask value for DCO_FIX_SEL_MASK*/
255 #define PLL_500_BYPASS BIT(2) /* Enables PLL_500_BYPASS */
256 #define PLL_500_CLK_ENABLE BIT(3) /* Enables PLL_500_CLK_ENABLE */
257 #define PLL_500_PD BIT(4) /* Enables PLL_500_PD */
258 #define PLL_500_RST BIT(5) /* Enables PLL_500_RST */
259 #define PLL_500_M_MASK (0xFFC0) /* Mask value for PLL_500_M_MASK*/
260 /*I2S_PLL_CTRL_REG_1*/
261 #define I2S_PLL_CLK_ENABLE BIT(2) /* Enables I2S_PLL_CLK_ENABLE */
262 #define I2S_PLL_BYPASS BIT(3) /* Enables I2S_PLL_BYPASS */
263
264 /*SOC_PLL_500_CTRL_REG2/INTF_PLL_500_CTRL_REG 2 */
265 #define PLL_500_N_MASK (0x01F8) /* Mask value for PLL_500_N_MASK*/
266 #define PLL_500_P_MASK (0xFE00) /* Mask value for PLL_500_P_MASK*/
267
268 /*I2S_PLL_CTRL_REG_2*/
269 #define N_DIV_MASK (0x00FE) /* Mask value for N_DIV_MASK*/
270 #define P_DIV2_MASK (0x0700) /* Mask value for P_DIV2_MASK*/
271 #define P_DIV1_MASK (0xF800) /* Mask value for P_DIV1_MASK*/
272
273 /*SOC_PLL_500_CTRL_REG3/INTF_PLL_500_CTRL_REG_3/ I2S_PLL_CTRL_REG_3 */
274 #define FCW_F_MASK (0xFFFC) /* Mask value for FCW_F_MASK*/
275
276 /*SOC_PLL_500_CTRL_REG_4/INTF_PLL_500_CTRL_REG_4 */
277 #define LDO_BY_PASS BIT(1) /* Enables LDO_BY_PASS */
278 #define SD_CLK_SEL_MASK (0x000C) /* Mask value for SD_CLK_SEL_MASK*/
279 #define SD_LEN BIT(4) /* Enables SD_LEN */
280 #define FILTER_TYPE BIT(5) /* Enables FILTER_TYPE */
281 #define BETA_MASK (0x07C0) /* Mask value for BETA_MASK*/
282 #define ALPHA_MASK (0xF800) /* Mask value for ALPHA_MASK*/
283 /*SOC_PLL_500_CTRL_REG_5/INTF_PLL_500_CTRL_REG_5/ I2S_PLL_CTRL_REG_5 */
284 #define LOCK_LIMIT_MASK (0x3FFF) /* Mask value for LOCK_LIMIT_MASK*/
285 #define ENABLE_PHASE_LOCK_DETECT BIT(14) /* Enables ENABLE_PHASE_LOCK_DETECT */
286 #define ENABLE_FREQ_LOCK_DETECT BIT(15) /* Enables ENABLE_FREQ_LOCK_DETECT */
287 /*SOC_PLL_500_CTRL_REG_6/INTF_PLL_500_CTRL_REG_6/ I2S_PLL_CTRL_REG_6 */
288 #define RETIMER_COUNT_MASK (0x00F0) /* Mask value for RETIMER_COUNT_MASK*/
289 #define TDC_PWRSAV_COUNT_MASK (0x7F00) /* Mask value for TDC_PWRSAV_COUNT_MASK*/
290 #define TDC_PWRSAV_EN BIT(15) /* Enables TDC_PWRSAV_EN */
291
292 /*SOC_PLL_500_CTRL_REG_7/INTF_PLL_500_CTRL_REG_7/ I2S_PLL_CTRL_REG_7*/
293 #define SPI_INP_RD_EN BIT(4) /* Enables SPI_INP_RD_EN */
294 #define OCW_MANUAL_MASK (0xFFE0) /* Mask value for OCW_MANUAL_MASK */
295 #define DCO_TESTMODE BIT(15) /* Enables DCO_TESTMODE */
296
297 /*SOC_PLL_500_CTRL_REG_8/INTF_PLL_500_CTRL_REG_8/I2S_PLL_CTRL_REG_8 */
298 #define ISOLATION_ENABLE BIT(0) /* Enables ISOLATION_ENABLE */
299 #define BYPASS_ISO_GEN BIT(1) /* Enables BYPASS_ISO_GEN */
300 #define BYPASS_LOCK_FLAG BIT(2) /* Enables BYPASS_LOCK_FLAG */
301 #define BYPASS_PWR_GOOD BIT(3) /* Enables BYPASS_PWR_GOOD */
302 #define LOCK_COUNT_LIMIT_FREQ_MASK (0x00F0) /* Mask value for LOCK_COUNT_LIMIT_FREQ_MASK */
303 #define LOCK_COUNT_LIMIT_PHASE_MASK (0xFF00) /* Mask value for LOCK_COUNT_LIMIT_PHASE_MASK*/
304
305 /*SOC_PLL_500_CTRL_REG_9/INTF_PLL_500_CTRL_REG_9/ I2S_PLL_CTRL_REG_9 */
306 #define MM_COUNT_LIMIT_MASK (0x3FC0) /* Mask value for MM_COUNT_LIMIT_MASK */
307 #define BYPASS_LOCK_PLL BIT(14) /* Enables BYPASS_LOCK_PLL */
308 #define MANUAL_LOCK_ENABLE BIT(15) /* Enables MANUAL_LOCK_ENABLE */
309
310 /*SOC_PLL_500_CTRL_REG_10/INTF_PLL_500_CTRL_REG_10/ I2S_PLL_CTRL_REG_10 */
311 #define CKR_TEST_EN BIT(3) /* Enables CKR_TEST_EN */
312 #define SELOUT_SA_RETIMER BIT(4) /* Enables SELOUT_SA_RETIMER */
313 #define EN_STD_RETIMER BIT(5) /* Enables EN_STD_RETIMER */
314 #define EN_SA_RETIMER BIT(6) /* Enables EN_SA_RETIMER */
315 #define RETIMER_PWRSAV_COUNT2_MASK (0x0780) /* Mask value for RETIMER_PWRSAV_COUNT2_MASK */
316 #define RETIMER_PWRSAV_COUNT1_MASK (0x7800) /* Mask value for RETIMER_PWRSAV_COUNT1_MASK */
317 #define RETIMER_PWRSAV_EN BIT(15) /* Enables RETIMER_PWRSAV_EN */
318
319 /*SOC_PLL_500_CTRL_REG_11/INTF_PLL_500_CTRL_REG_11/ I2S_PLL_CTRL_REG_11 */
320 #define PU_SD_DIV BIT(1) /* Enables PU_SD_DIV */
321 #define PU_POST_DIV BIT(2) /* Enables PU_POST_DIV */
322 #define PU_INP_DIV BIT(3) /* Enables PU_INP_DIV */
323 #define PU_INDO BIT(4) /* Enables PU_INDO */
324 #define PU_RETIMER BIT(5) /* Enables PU_RETIMER */
325 #define PU_TDC BIT(6) /* Enables PU_TDC */
326 #define PU_DCO BIT(7) /* Enables PU_DCO */
327 #define PU_DIGITAL_TOP BIT(8) /* Enables PU_DIGITAL_TOP */
328 #define RESETN_SD_DIV BIT(9) /* Enables RESETN_SD_DIV */
329 #define RESETN_INP_DIV BIT(10) /* Enables RESETN_INP_DIV */
330 #define RESETN_POST_DIV BIT(11) /* Enables RESETN_POST_DIV */
331 #define RESETN_RETIMER BIT(12) /* Enables RESETN_RETIMER */
332 #define RESETN_LOCK_DETECT BIT(13) /* Enables RESETN_LOCK_DETECT */
333 #define RESETN_LOOP BIT(14) /* Enables RESETN_LOOP */
334 #define RESETN_TDC BIT(15) /* Enables RESETN_TDC */
335
336 /*SOC_PLL_500_CTRL_REG_12/INTF_PLL_500_CTRL_REG_12/ I2S_PLL_CTRL_REG_12 */
337 #define DELTF_MASK (0x003E) /* Mask value for DELTF_MASK */
338 #define DELTR_MASK (0x07C0) /* Mask value for DELTR_MASK */
339 #define TV_MASK (0XF800) /* Mask value for TV_MASK */
340
341 /*SOC_PLL_500_CTRL_REG_13/INTF_PLL_500_CTRL_REG_13/ I2S_PLL_CTRL_REG_13*/
342 #define OCW_MASK (0x3FF0) /* Mask value for OCW_MASK */
343 #define LOCK_FLAG_PHASE BIT(14) /* Enables LOCK_FLAG_PHASE */
344 #define LOCK_FLAG_FREQ BIT(15) /* Enables LOCK_FLAG_FREQ */
345
346 /*SOC Clock division factor checks */
347 #define SOC_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for SOC clock*/
348 #define SOC_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for SOC clock*/
349
350 /*SDMEM Clock division factor checks */
351 #define SDMEM_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for SD_MEM clock*/
352 #define SDMEM_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for SD_MEM clock*/
353
354 /*CT Clock division factor checks */
355 #define CT_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for CT clock*/
356 #define CT_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for CT clock*/
357
358 /*I2S Clock division factor checks */
359 #define I2S_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for I2S clock*/
360 #define I2S_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for I2S clock*/
361
362 /*USB Clock division factor checks */
363 #define USB_MAX_CLK_DIVISION_FACTOR 3 /* Maximum division factor value for USB clock*/
364 #define USB_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for USB clock*/
365
366 /*CAN Clock division factor checks */
367 #define CAN_MAX_CLK_DIVISION_FACTOR 255 /* Maximum division factor value for CAN clock*/
368 #define CAN_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for CAN clock*/
369
370 /*I2S Clock division factor checks */
371 #define MCU_CLKOUT_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for MCU_CLKOUT clock*/
372 #define MCU_CLKOUT_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for MCU_CLKOUT clock*/
373 #define MCU_CLKOUT_SEL_MAX 15 /* Maximum Seletion value for MCU_CLKOUT clock source*/
374
375 /*QSPI Clock Division factor checks */
376 #define QSPI_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for QSPI clock*/
377 #define QSPI_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for QSPI clock*/
378
379 /*USART Clock Division factor checks */
380 #define USART_MAX_CLK_DIVISION_FACTOR 15 /* Maximum division factor value for USART clock*/
381 #define USART_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for USART clock*/
382
383 /*SSI Clock Division factor checks */
384 #define SSI_MAX_CLK_DIVISION_FACTOR 15 /* Maximum division factor value for SSI clock*/
385 #define SSI_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for SSI clock*/
386
387 /*CCI Clock Division factor checks */
388 #define CCI_MAX_CLK_DIVISION_FACTOR 15 /* Maximum division factor value for CCI clock*/
389 #define CCI_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for CCI clock*/
390
391 /*PLL_INTF Clock Division factor checks */
392 #define PLL_INTF_MAX_CLK_DIVISION_FACTOR 15 /* Maximum division factor value for PLL_INTF clock*/
393 #define PLL_INTF_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for PLL_INTF clock*/
394
395 /*Sleep Clock selection checks */
396 #define SLP_MAX_SEL 3 /* Maximum Seletion value for Sleep clock source*/
397 #define SLP_MIN_SEL 0 /* Minimum Seletion value for Sleep clock source*/
398
399 #define MAX_SLP_CYCLES 3 /* Maximum Cycles for Sleep clock*/
400 #define MIN_SLP_CYCLES 0 /* Minimum Cycles for Sleep clock*/
401
402 #define MISC_CFG_MISC_CTRL1 (*((uint32_t volatile *)(MISC_CONFIG_BASE + 0x44))) /* address of MISC_CFG_MISC_CTRL1 */
403 #define I2S_MASTER_SLAVE_MODE (1 << 23) /* Sets I2S/I2S PCM master mode */
404
405 #define MCU_ULP_40MHZ_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP 40MHZ CLK*/
406 #define MCU_ULP_DOUBLER_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP DOUBLER CLK*/
407 #define MCU_ULP_20MHZ_RING_OSC_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP 20MHZ_RING_OSC CLK*/
408 #define MCU_ULP_MHZ_RC_CLK_EN_TRUN_ON_DELAY 2 /* delay to enable the ULP MHZ_RC CLK*/
409 #define MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_1 500 /* delay to enable the ULP 32KHZ_XTAL CLK*/
410 #define MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_2 1500 /* delay to enable the ULP 32KHZ_XTAL CLK*/
411 #define MCU_ULP_32KHZ_RO_CLK_EN_TRUN_ON_DELAY 250 /* delay to enable the ULP 32KHZ_RO CLK*/
412 #define MCU_ULP_32KHZ_RC_CLK_EN_TRUN_ON_DELAY 150 /* delay to enable the ULP 32KHZ_RC CLK*/
413
414 /**
415 *@brief Reference clock selection
416 **/
417 typedef enum REF_CLK_ENABLE {
418 MCU_ULP_40MHZ_CLK_EN, /*!< Enables ULP_40MHZ_CLK when it is passed */
419 MCU_ULP_DOUBLER_CLK_EN, /*!< Enables ULP_DOUBLER_CLK when it is passed */
420 MCU_ULP_20MHZ_RING_OSC_CLK_EN, /*!< Enables ULP_20MHZ_RING_OSC_CLK when it is passed */
421 MCU_ULP_MHZ_RC_CLK_EN, /*!< Enables ULP_MHZ_RC_CLK when it is passed */
422 MCU_ULP_32KHZ_XTAL_CLK_EN, /*!< Enables ULP_32KHZ_XTAL_CLK when it is passed */
423 MCU_ULP_32KHZ_RO_CLK_EN, /*!< Enables ULP_32KHZ_RO_CLK when it is passed */
424 MCU_ULP_32KHZ_RC_CLK_EN /*!< Enables ULP_32KHZ_RC_CLK when it is passed */
425 } REF_CLK_ENABLE_T;
426 /**
427 *@brief list of peripherals, particular clock that to be enabled
428 **/
429 typedef enum PERIPHERALS_CLK {
430 USART1_CLK, /*!< Enables or Disables USART1 Peripheral clock when it is passed */
431 USART2_CLK, /*!< Enables or Disables USART2 Master Peripheral clock when it is passed */
432 SSIMST_CLK, /*!< Enables or Disables SSI Master Peripheral clock when it is passed */
433 SSISLAVE_CLK, /*!< Enables or Disables SSI Slave Peripheral clock when it is passed */
434 CT_CLK, /*!< Enables or Disables CT Peripheral clock when it is passed */
435 SD_MEM_CLK, /*!< Enables or Disables SD_MEM Peripheral clock when it is passed */
436 CCI_CLK, /*!< Enables or Disables CCI Peripheral clock when it is passed */
437 QSPI_CLK, /*!< Enables or Disables QSPI Peripheral clock when it is passed */
438 RPDMA_CLK, /*!< Enables or Disables RPDMA Peripheral clock when it is passed */
439 UDMA_CLK, /*!< Enables or Disables UDMA Peripheral clock when it is passed */
440 PWM_CLK, /*!< Enables or Disables PWM Peripheral clock when it is passed */
441 CAN_CLK, /*!< Enables or Disables CAN Peripheral clock when it is passed */
442 GSPI_CLK, /*!< Enables or Disables GSPI Peripheral clock when it is passed */
443 EGPIO_CLK, /*!< Enables or Disables EGPIO Peripheral clock when it is passed */
444 ETHERNET_CLK, /*!< Enables or Disables ETHERNET Peripheral clock when it is passed */
445 MCUCLKOUT_CLK, /*!< Enables or Disables MCUCLKOUT Peripheral clock when it is passed */
446 HWRNG_CLK, /*!< Enables or Disables HWRNG Peripheral clock when it is passed */
447 I2SM_CLK, /*!< Enables or Disables I2SM Peripheral clock when it is passed */
448 #if defined(SLI_SI917B0) || defined(SLI_SI915)
449 QSPI_2_CLK, /*!< Enables or Disables QSPI 2 Peripheral clock when it is passed */
450 #endif
451 } PERIPHERALS_CLK_T;
452
453 /**
454 *@brief PLL selection types
455 **/
456 typedef enum PLL_TYPE {
457 SOC_PLL, /*!<SOC_PLL type selection*/
458 INFT_PLL, /*!<INFT_PLL type selection, maintaining for backward compatibility*/
459 INTF_PLL = INFT_PLL, /*!<INTF_PLL type selection*/
460 I2S_PLL /*!<I2S_PLL type selection*/
461 } PLL_TYPE_T;
462 /**
463 *@brief list of possible values of UART instances
464 **/
465 typedef enum EN_USART {
466 USART1 = 0, /*!<USART1 instance selection*/
467 USART2 = 1, /*!<USART2 instance selection*/
468 } EN_USART_T;
469 /**
470 *@brief list of possible values of I2C instances
471 **/
472 typedef enum EN_I2C {
473 I2C1_INSTAN = 0, /*!<I2C 1 instance selection*/
474 I2C2_INSTAN = 1 /*!<I2C 2 instance selection*/
475 } EN_I2C_T;
476
477 /**
478 *@brief enum values for proccessor and peripheral clk
479 **/
480 typedef enum SRC_TYPE {
481 ULP_PROCESSOR_CLK = 0, /*!< ULP_PROCESSOR_CLK selection*/
482 ULP_PERIPHERAL_CLK = 1 /*!< ULP_PERIPHERAL_CLK selection*/
483
484 } SRC_TYPE_T;
485 /**
486 *@brief M4 SOC input clock sources selection
487 **/
488 typedef enum M4_SOC_CLK_SRC_SEL {
489 M4_ULPREFCLK = 0, /*!< M4_ULPREFCLK selection*/
490 M4_RESERVED = 1, /*!< RESERVED*/
491 M4_SOCPLLCLK = 2, /*!< M4_SOCPLLCLK selection*/
492 M4_MODEMPLLCLK1 = 3, /*!< M4_MODEMPLLCLK1 selection*/
493 M4_INTFPLLCLK = 4, /*!< M4_INTFPLLCLK selection*/
494 M4_SLEEPCLK = 5, /*!< M4_SLEEPCLK selection*/
495 } M4_SOC_CLK_SRC_SEL_T;
496 /**
497 *@brief QSPI Input clock source selection
498 **/
499 typedef enum QSPI_CLK_SRC_SEL {
500 QSPI_ULPREFCLK = 0, /*!< QSPI_ULPREFCLK selection*/
501 QSPI_MODELPLLCLK2 = 1, /*!< QSPI_MODELPLLCLK2 selection*/
502 QSPI_INTFPLLCLK = 2, /*!< QSPI_INTFPLLCLK selection*/
503 QSPI_SOCPLLCLK = 3, /*!< QSPI_SOCPLLCLK selection*/
504 M4_SOCCLKNOSWLSYNCCLKTREEGATED = 4 /*!< M4_SOCCLKNOSWLSYNCCLKTREEGATED selection*/
505 } QSPI_CLK_SRC_SEL_T;
506
507 /**
508 *@brief Clock enable type
509 **/
510 typedef enum CLK_ENABLE {
511 ENABLE_DYN_CLK, /*!< Dynamic clock enable for the peripherals*/
512 ENABLE_STATIC_CLK /*!< Static clock enable for the peripherals*/
513 } CLK_ENABLE_T;
514 /**
515 *@brief USART Input clock source selection
516 **/
517 typedef enum USART_CLK_SRC_SEL {
518 USART_ULPREFCLK = 0, /*!< USART_ULPREFCLK selection*/
519 USART_SOCPLLCLK = 1, /*!< USART_SOCPLLCLK selection*/
520 USART_MODELPLLCLK2 = 2, /*!< USART_MODELPLLCLK2 selection*/
521 USART_INTFPLLCLK = 3, /*!< USART_INTFPLLCLK selection*/
522 M4_SOCCLKFOROTHERCLOCKS = 4, /*!< M4_SOCCLKFOROTHERCLOCKS selection*/
523 } USART_CLK_SRC_SEL_T;
524
525 /**
526 *@brief USART Fractional clock selection
527 **/
528 typedef enum USART_SCLK_FRAC_SEL {
529 USART_FRACTIONAL_DIVIDER, /*!< Fractional Divider selected i.e clk_out = clk_in/ (sclk_div_fac+0.5)*/
530 USART_CLOCK_SWALLOW, /*!< Clock Swallow selected i.e clk_out = clk_in/ sclk_div_fac*/
531 } USART_SCLK_FRAC_SEL_T;
532
533 /**
534 *@brief SSI Input clock source selection
535 **/
536 typedef enum SSI_MST_CLK_SRC_SEL {
537 SSI_ULPREFCLK = 0, /*!< SSI_ULPREFCLK selection*/
538 SSI_SOCPLLCLK = 1, /*!< SSI_SOCPLLCLK selection*/
539 SSI_MODEMPLLCLK1 = 2, /*!< SSI_MODEMPLLCLK1 selection*/
540 SSI_INTFPLLCLK = 3, /*!< SSI_INTFPLLCLK selection*/
541 SSI_MODELPLLCLK2 = 4, /*!< SSI_MODELPLLCLK2 selection*/
542 M4_SOCCLKFOROTHERCLKS = 5, /*!< M4_SOCCLKFOROTHERCLKS selection*/
543 } SSI_MST_CLK_SRC_SEL_T;
544 /**
545 *@brief SD_MEM Input clock source selection
546 **/
547 typedef enum SDMEM_CLK_SRC_SEL {
548 SDMEM_SOCPLLCLK = 0, /*!< SDMEM_SOCPLLCLK selection*/
549 SDMEM_MODEMPLLCLK1 = 1, /*!< SDMEM_MODEMPLLCLK1 selection*/
550 SDMEM_INTFPLLCLK = 2, /*!< SDMEM_INTFPLLCLK selection*/
551 M4_SOCCLKFOROTHERCLKSSDMEM = 3, /*!< M4_SOCCLKFOROTHERCLKSSDMEM selection*/
552 } SDMEM_CLK_SRC_SEL_T;
553 /**
554 *@brief CT Input clock source selection
555 **/
556 /*CT Input clock source selection*/
557 typedef enum CT_CLK_SRC_SEL {
558 CT_ULPREFCLK = 0, /*!< CT_ULPREFCLK selection*/
559 CT_INTFPLLCLK = 1, /*!< CT_INTFPLLCLK selection*/
560 CT_SOCPLLCLK = 2, /*!< CT_SOCPLLCLK selection*/
561 M4_SOCCLKFOROTHERCLKSCT = 3, /*!< M4_SOCCLKFOROTHERCLKSCT selection*/
562 } CT_CLK_SRC_SEL_T;
563 /**
564 *@brief GSPI Input clock source selection
565 **/
566
567 typedef enum GSPI_CLK_SRC_SEL {
568 GSPI_M4_SOC_CLK_FOR_OTHER_CLKS, /*!< GSPI_M4_SOC_CLK_FOR_OTHER_CLKS selection*/
569 GSPI_ULP_REF_CLK, /*!< GSPI_ULP_REF_CLK selection*/
570 GSPI_SOC_PLL_CLK, /*!< GSPI_SOC_PLL_CLK selection*/
571 GSPI_MODEM_PLL_CLK2, /*!< GSPI_MODEM_PLL_CLK2 selection*/
572 GSPI_INTF_PLL_CLK, /*!< GSPI_INTF_PLL_CLK selection*/
573 } GSPI_CLK_SRC_SEL_T;
574 /**
575 *@brief MCU_CLKOUT Input clock source selection
576 **/
577
578 typedef enum MCU_CLKOUT_SRC_SEL {
579 MCUCLKOUT_ULP_MHZ_RC_CLK, /*!< MCUCLKOUT_ULP_MHZ_RC_CLK selection*/
580 MCUCLKOUT_RF_REF_CLK, /*!< MCUCLKOUT_RF_REF_CLK selection*/
581 MCUCLKOUT_MEMS_REF_CLK, /*!< MCUCLKOUT_MEMS_REF_CLK selection*/
582 MCUCLKOUT_ULP_20MHZ_RINGOSC_CLK, /*!< MCUCLKOUT_ULP_20MHZ_RINGOSC_CLK selection*/
583 MCUCLKOUT_ULP_DOUBLER_CLK, /*!< MCUCLKOUT_ULP_DOUBLER_CLK selection*/
584 MCUCLKOUT_ULP_32KHZ_RC_CLK, /*!< MCUCLKOUT_ULP_32KHZ_RC_CLK selection*/
585 MCUCLKOUT_ULP_32KHZ_XTAL_CLK, /*!< MCUCLKOUT_ULP_32KHZ_XTAL_CLK selection*/
586 MCUCLKOUT_ULP_32KHZ_RO_CLK, /*!< MCUCLKOUT_ULP_32KHZ_RO_CLK selection*/
587 MCUCLKOUT_INTF_PLL_CLK, /*!< MCUCLKOUT_INTF_PLL_CLK selection*/
588 MCUCLKOUT_MODEM_PLL_CLK1, /*!< MCUCLKOUT_MODEM_PLL_CLK1 selection*/
589 MCUCLKOUT_MODEM_PLL_CLK2, /*!< MCUCLKOUT_MODEM_PLL_CLK2 selection*/
590 MCUCLKOUT_SOC_PLL_CLK, /*!< MCUCLKOUT_SOC_PLL_CLK selection*/
591 MCUCLKOUT_I2S_PLL_CLK, /*!< MCUCLKOUT_I2S_PLL_CLK selection*/
592 MCUCLKOUT_USB_PLL_CLK, /*!< MCUCLKOUT_USB_PLL_CLK selection*/
593 } MCU_CLKOUT_SRC_SEL_T;
594 /**
595 *@brief Ethernet Input clock source selection
596 **/
597 typedef enum ETHERNET_CLK_SRC_SEL {
598 ETH_INTF_PLL_CLK, /*!< ETH_INTF_PLL_CLK selection*/
599 ETH_SOC_PLL_CLK, /*!< ETH_SOC_PLL_CLK selection*/
600 } ETHERNET_CLK_SRC_SEL_T;
601 /**
602 *@brief USB Input clock source selection
603 **/
604 typedef enum USB_CLK_SRC_SEL {
605 USB_MEMS_REF_CLK = 0, /*!< USB_MEMS_REF_CLK selection*/
606 USB_REFERENCE_CLK = 1, /*!< USB_REFERENCE_CLK selection*/
607 USB_PLL_CLK = 2 /*!< USB_PLL_CLK selection*/
608 } USB_CLK_SRC_SEL_T;
609 /**
610 *@brief Sleep Clk Input clock source selection
611 **/
612 typedef enum SLEEP_CLK_SRC_SEL {
613 SLP_ULP_32KHZ_RC_CLK = 0, /*!< SLP_ULP_32KHZ_RC_CLK selection*/
614 SLP_ULP_32KHZ_XTAL_CLK = 1, /*!< SLP_ULP_32KHZ_XTAL_CLK selection*/
615 SLP_CLK_GATED = 2, /*!< Default Sleep Clk Gated*/
616 SLP_ULP_32KHZ_RO_CLK = 3 /*!< SLP_ULP_32KHZ_RO_CLK selection*/
617 } SLEEP_CLK_SRC_SEL_T;
618 /**
619 *@brief CCI Input clock source selection
620 **/
621 typedef enum CCI_CLK_SRC_SEL {
622 CCI_M4_SOC_CLK_FOR_OTHER_CLKS, /*!< CCI_M4_SOC_CLK_FOR_OTHER_CLKS selection*/
623 CCI_INTF_PLL_CLK, /*!< CCI_INTF_PLL_CLK selection*/
624 CCI_M4_SOC_CLK_NO_SWL_SYNC_CLK_TREE /*!< CCI_M4_SOC_CLK_NO_SWL_SYNC_CLK_TREE selection*/
625 } CCI_CLK_SRC_SEL_T;
626 /**
627 *@brief I2S Input clock source selection
628 **/
629 typedef enum I2S_CLK_SRC_SEL {
630 I2S_PLLCLK = 0, /*!< I2S_PLLCLK selection*/
631 I2S_M4SOCCLKFOROTHERS = 1, /*!< I2S_M4SOCCLKFOROTHERS selection*/
632 } I2S_CLK_SRC_SEL_T;
633
634 /**
635 *@brief M4ss Reference Input clock source selection
636 **/
637 typedef enum M4SS_REF_CLK_SEL {
638 ULP_MHZ_RC_BYP_CLK = 1, /*!< ULP_MHZ_RC_BYP_CLK selection*/
639 ULP_MHZ_RC_CLK = 2, /*!< ULP_MHZ_RC_CLK selection*/
640 EXT_40MHZ_CLK = 3, /*!< EXT_40MHZ_CLK selection*/
641 MEMS_REF_CLK = 4, /*!< MEMS_REF_CLK selection*/
642 ULP_20MHZ_RINGOSC_CLK = 5, /*!< ULP_20MHZ_RINGOSC_CLK selection*/
643 ULP_DOUBLER_CLK = 6, /*!< ULP_DOUBLER_CLK selection*/
644 } M4SS_REF_CLK_SEL_T;
645
646 typedef enum CLK_PRESENT {
647 SOC_PLL_CLK_PRESENT, /*!< SOC CLock present */
648 INTF_PLL_CLK_PRESENT, /*!< INTF PLL clock present */
649 I2S_PLL_CLK_PRESENT, /*!< I2S PLL clock present */
650 MODEM_PLL_CLK_PRESENT, /*!< Modem PLL clock present */
651 } CLK_PRESENT_T;
652
_usdelay(uint32_t delayUs,cdDelay delayCb)653 STATIC INLINE void _usdelay(uint32_t delayUs, cdDelay delayCb)
654 {
655 if (delayCb != NULL) {
656 delayCb(delayUs);
657 }
658 }
659
660 rsi_error_t clk_i2s_pll_clk_set(const M4CLK_Type *pCLK);
661
662 boolean_t clk_check_pll_lock(PLL_TYPE_T pllType);
663
664 rsi_error_t clk_soc_pll_clk_enable(boolean_t clkEnable);
665
666 rsi_error_t clk_soc_pll_set_freq_div(const M4CLK_Type *pCLK,
667 boolean_t clk_en,
668 uint16_t divFactor,
669 uint16_t nFactor,
670 uint16_t mFactor,
671 uint16_t fcwF,
672 uint16_t dcoFixSel,
673 uint16_t ldoProg);
674
675 rsi_error_t clk_soc_pll_clk_set(const M4CLK_Type *pCLK);
676
677 rsi_error_t clk_soc_pll_clk_bypass_enable(boolean_t clkEnable);
678
679 rsi_error_t clk_soc_pll_clk_reset(void);
680
681 rsi_error_t clk_soc_pll_pd_enable(boolean_t en);
682
683 rsi_error_t clk_soc_pll_turn_off(void);
684
685 rsi_error_t clk_soc_pll_turn_on(void);
686
687 rsi_error_t clk_i2s_pll_clk_enable(boolean_t clkEnable);
688
689 rsi_error_t clk_i2s_pll_clk_bypass_enable(boolean_t clkEnable);
690
691 rsi_error_t clk_i2s_pll_pd_enable(boolean_t en);
692
693 rsi_error_t clk_i2s_pll_turn_off(void);
694
695 rsi_error_t clk_i2s_pll_turn_on(void);
696
697 rsi_error_t clk_i2s_pll_set_freq_div(const M4CLK_Type *pCLK,
698 uint16_t u16DivFactor1,
699 uint16_t u16DivFactor2,
700 uint16_t nFactor,
701 uint16_t mFactor,
702 uint16_t fcwF);
703
704 rsi_error_t clk_i2s_pll_clk_reset(void);
705
706 rsi_error_t clk_i2s_pll_clk_set(const M4CLK_Type *pCLK);
707
708 rsi_error_t clk_intf_pll_clk_enable(boolean_t clkEnable);
709
710 rsi_error_t clk_intf_pll_pd_enable(boolean_t en);
711
712 rsi_error_t clk_intf_pll_turn_off(void);
713
714 rsi_error_t clk_intf_pll_set_freq_div(const M4CLK_Type *pCLK,
715 boolean_t clk_en,
716 uint16_t divFactor,
717 uint16_t nFactor,
718 uint16_t mFactor,
719 uint16_t fcwF,
720 uint16_t dcoFixSel,
721 uint16_t ldoProg);
722
723 rsi_error_t clk_intf_pll_clk_bypass_enable(boolean_t clkEnable);
724
725 rsi_error_t clk_intf_pll_turn_on(void);
726
727 rsi_error_t clk_intf_pll_clk_reset(void);
728
729 rsi_error_t clk_intf_pll_clk_set(const M4CLK_Type *pCLK);
730
731 rsi_error_t clk_peripheral_clk_enable1(M4CLK_Type *pCLK, uint32_t flags);
732
733 rsi_error_t clk_peripheral_clk_disable1(M4CLK_Type *pCLK, uint32_t flags);
734
735 rsi_error_t clk_peripheral_clk_enable2(M4CLK_Type *pCLK, uint32_t flags);
736
737 rsi_error_t clk_peripheral_clk_disable2(M4CLK_Type *pCLK, uint32_t flags);
738
739 rsi_error_t clk_peripheral_clk_enable3(M4CLK_Type *pCLK, uint32_t flags);
740
741 rsi_error_t clk_peripheral_clk_disable3(M4CLK_Type *pCLK, uint32_t flags);
742
743 rsi_error_t clk_dynamic_clk_gate_disable(M4CLK_Type *pCLK, uint32_t flags);
744
745 rsi_error_t clk_dynamic_clk_gate_disable2(M4CLK_Type *pCLK, uint32_t flags);
746
747 rsi_error_t clk_dynamic_clk_gate_enable(M4CLK_Type *pCLK, uint32_t flags);
748
749 rsi_error_t clk_dynamic_clk_gate_enable2(M4CLK_Type *pCLK, uint32_t flags);
750
751 rsi_error_t clk_qspi_clk_config(M4CLK_Type *pCLK,
752 QSPI_CLK_SRC_SEL_T clkSource,
753 boolean_t swalloEn,
754 boolean_t OddDivEn,
755 uint32_t divFactor);
756 #if defined(SLI_SI917B0) || defined(SLI_SI915)
757 rsi_error_t clk_qspi_2_clk_config(M4CLK_Type *pCLK,
758 QSPI_CLK_SRC_SEL_T clkSource,
759 boolean_t swalloEn,
760 boolean_t OddDivEn,
761 uint32_t divFactor);
762 #endif
763 rsi_error_t clk_usart_clk_config(M4CLK_Type *pCLK,
764 CLK_ENABLE_T clkType,
765 boolean_t FracDivEn,
766 EN_USART_T enUsart,
767 USART_CLK_SRC_SEL_T clkSource,
768 uint32_t divFactor);
769
770 rsi_error_t clk_ssi_mst_clk_config(M4CLK_Type *pCLK,
771 CLK_ENABLE_T clkType,
772 SSI_MST_CLK_SRC_SEL_T clkSource,
773 uint32_t divFactor);
774
775 rsi_error_t clk_sd_mem_clk_config(M4CLK_Type *pCLK,
776 boolean_t swalloEn,
777 SDMEM_CLK_SRC_SEL_T clkSource,
778 uint32_t divFactor);
779
780 rsi_error_t clk_ct_clk_config(M4CLK_Type *pCLK, CT_CLK_SRC_SEL_T clkSource, uint32_t divFactor, CLK_ENABLE_T clkType);
781
782 rsi_error_t clk_cci_clk_config(M4CLK_Type *pCLK, CCI_CLK_SRC_SEL_T clkSource, uint32_t divFactor, CLK_ENABLE_T clkType);
783
784 rsi_error_t clk_i2s_clk_config(M4CLK_Type *pCLK, I2S_CLK_SRC_SEL_T clkSource, uint32_t divFactor);
785
786 rsi_error_t clk_mcu_clk_cut_config(M4CLK_Type *pCLK, MCU_CLKOUT_SRC_SEL_T clkSource, uint32_t divFactor);
787
788 rsi_error_t clk_can_clk_config(M4CLK_Type *pCLK, uint32_t divFactor, CLK_ENABLE_T clkType);
789
790 rsi_error_t clk_ethernet_clk_config(M4CLK_Type *pCLK,
791 boolean_t swalloEn,
792 ETHERNET_CLK_SRC_SEL_T clkSource,
793 uint32_t divFactor);
794
795 rsi_error_t clk_m4_soc_clk_div(M4CLK_Type *pCLK, uint32_t divFactor);
796
797 rsi_error_t clk_qspi_clk_div(M4CLK_Type *pCLK, boolean_t u8SwallowEn, boolean_t u8OddDivEn, uint32_t divFactor);
798
799 rsi_error_t clk_ct_clk_div(M4CLK_Type *pCLK, uint32_t divFactor);
800
801 rsi_error_t clk_ssi_mst_clk_div(M4CLK_Type *pCLK, uint32_t divFactor);
802
803 rsi_error_t clk_cci_clk_div(M4CLK_Type *pCLK, uint32_t divFactor);
804
805 rsi_error_t clk_i2s_clk_div(M4CLK_Type *pCLK, uint32_t divFactor);
806
807 rsi_error_t clk_sd_mem_clk_div(M4CLK_Type *pCLK, boolean_t u8SwallowEn, uint32_t divFactor);
808
809 rsi_error_t clk_usart_clk_div(M4CLK_Type *pCLK, EN_USART_T enUsart, boolean_t u8FracDivEn, uint32_t divFactor);
810
811 rsi_error_t RSI_CLK_CanClkDiv(M4CLK_Type *pCLK, uint16_t divFactor);
812
813 uint32_t clk_slp_clk_calib_config(M4CLK_Type *pCLK, uint8_t clkCycles);
814
815 rsi_error_t clk_gspi_clk_config(M4CLK_Type *pCLK, GSPI_CLK_SRC_SEL_T clkSel);
816
817 rsi_error_t clk_slp_clk_config(M4CLK_Type *pCLK, SLEEP_CLK_SRC_SEL_T clkSrc);
818
819 rsi_error_t clk_i2c_clk_config(M4CLK_Type *pCLK, boolean_t clkEnable, EN_I2C_T enI2C);
820
821 rsi_error_t clk_xtal_clk_config(uint8_t xtalPin);
822
823 rsi_error_t clk_usb_clk_config(M4CLK_Type *pCLK, USB_CLK_SRC_SEL_T clkSource, uint16_t divFactor);
824
825 rsi_error_t clk_peripheral_clk_enable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module, CLK_ENABLE_T clkType);
826
827 rsi_error_t clk_peripheral_clk_disable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module);
828
829 rsi_error_t clk_set_soc_pll_freq(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk);
830
831 rsi_error_t clk_set_intf_pll_freq(const M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk);
832
833 rsi_error_t ulpss_enable_ref_clks(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType, cdDelay delayFn);
834
835 rsi_error_t clk_set_i2s_pll_freq(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal);
836
837 static void _usdelay(uint32_t delayUs, cdDelay delayCb);
838
839 rsi_error_t ulpss_disable_ref_clks(REF_CLK_ENABLE_T clk_type);
840
841 void clk_config_pll_lock(boolean_t manual_lock, boolean_t bypass_manual_lock, uint8_t mm_count_limit);
842
843 void clk_config_pll_ref_clk(uint8_t ref_clk_src);
844 rsi_error_t clk_m4_soc_clk_config(M4CLK_Type *pCLK, M4_SOC_CLK_SRC_SEL_T clkSource, uint32_t divFactor);
845 uint32_t RSI_CLK_CheckPresent(const M4CLK_Type *pCLK, CLK_PRESENT_T clkPresent);
846 rsi_error_t clk_m4ss_ref_clk_config(const M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource);
847 rsi_error_t ulpss_disable_ref_clks(REF_CLK_ENABLE_T clk_type);
848
849 /*End of file not truncated*/
850
851 #ifdef __cplusplus
852 }
853 #endif
854 #endif // RSI_PLL_H
855
