Searched refs:CLK_CONFIG_REG2_b (Results 1 – 3 of 3) sorted by relevance
1442 pCLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL = OddDivEn ? ENABLE : DISABLE; in clk_qspi_clk_config()1743 pCLK->CLK_CONFIG_REG2_b.CCI_CLK_DIV_FAC = divFactor; in clk_cci_clk_config()1842 pCLK->CLK_CONFIG_REG2_b.CCI_CLK_DIV_FAC = divFactor; in clk_cci_clk_div()2170 pCLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL = 1; in clk_qspi_clk_div()2172 pCLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL = 0; in clk_qspi_clk_div()2250 pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; in clk_usart_clk_div()2252 pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; in clk_usart_clk_div()2254 pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); in clk_usart_clk_div()2257 pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 1; in clk_usart_clk_div()2259 pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 0; in clk_usart_clk_div()[all …]
103 src_clk_mux = M4CLK->CLK_CONFIG_REG2_b.USART1_SCLK_SEL; in RSI_CLK_GetBaseClock()144 div_fac = M4CLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC; in RSI_CLK_GetBaseClock()145 swallow_val = M4CLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL; in RSI_CLK_GetBaseClock()162 src_clk_mux = M4CLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL; in RSI_CLK_GetBaseClock()203 div_fac = M4CLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC; in RSI_CLK_GetBaseClock()204 swallow_val = M4CLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL; in RSI_CLK_GetBaseClock()367 div_fac = (M4CLK->CLK_CONFIG_REG2_b.CCI_CLK_DIV_FAC); in RSI_CLK_GetBaseClock()397 odd_div = (M4CLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL); in RSI_CLK_GetBaseClock()451 odd_div = (M4CLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL); in RSI_CLK_GetBaseClock()
10549 } CLK_CONFIG_REG2_b; member
