Searched refs:CLK_CONFIG_REG1_b (Results 1 – 3 of 3) sorted by relevance
221 src_clk_mux = M4CLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL; in RSI_CLK_GetBaseClock()265 div_fac = (M4CLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_DIV_FAC); in RSI_CLK_GetBaseClock()376 src_clk_mux = M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL; in RSI_CLK_GetBaseClock()395 swallow_val = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL); in RSI_CLK_GetBaseClock()396 div_fac = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_DIV_FAC); in RSI_CLK_GetBaseClock()449 swallow_val = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL); in RSI_CLK_GetBaseClock()450 div_fac = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_DIV_FAC); in RSI_CLK_GetBaseClock()484 src_clk_mux = M4CLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL; in RSI_CLK_GetBaseClock()528 src_clk_mux = M4CLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_SEL; in RSI_CLK_GetBaseClock()540 div_fac = (M4CLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_DIV_FAC); in RSI_CLK_GetBaseClock()[all …]
1390 pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL = clkSource; in clk_qspi_clk_config()1399 pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL = 0x01; in clk_qspi_clk_config()1409 pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL = 0x02; in clk_qspi_clk_config()1418 pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL = clkSource; in clk_qspi_clk_config()1437 pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); in clk_qspi_clk_config()1441 pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL = swalloEn ? ENABLE : DISABLE; in clk_qspi_clk_config()1577 pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x00; in clk_ssi_mst_clk_config()1585 pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x01; in clk_ssi_mst_clk_config()1593 pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x02; in clk_ssi_mst_clk_config()1601 pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x03; in clk_ssi_mst_clk_config()[all …]
10488 } CLK_CONFIG_REG1_b; member
