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Searched refs:CLKEN0_SET (Results 1 – 25 of 32) sorted by relevance

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/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_se.c322 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_executeCommand()
396 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in rootIsOutputMailboxValid()
450 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_getVersion()
509 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_getConfigStatusBits()
548 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_getOTPVersion()
586 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_isCommandCompleted()
615 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_readExecutedCommand()
652 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_readCommandResponse()
700 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_ackCommand()
Dem_emu.c730 CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0; in dpllState()
1768 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in EMU_RamPowerDown()
1821 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in EMU_RamPowerUp()
3345 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_DCDCBoostInit()
3395 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_EM01BoostPeakCurrentSet()
3449 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_DCDCBoostOutputVoltageSet()
3507 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_DCDCModeSet()
3583 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_DCDCInit()
3652 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_EM01PeakCurrentSet()
3713 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_DCDCSetPFMXModePeakCurrent()
[all …]
Dem_cmu.c1494 CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; in sli_em_cmu_HFXOSetForceEnable()
1511 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in sli_em_cmu_SYSTICEXTCLKENSet()
1535 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in sli_em_cmu_SYSTICEXTCLKENClear()
1587 CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; in CMU_ClockSelectSet()
1764 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in CMU_ClockSelectSet()
1777 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in CMU_ClockSelectSet()
2438 CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; in CMU_LF_ClockPrecisionGet()
2533 CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; in CMU_HFRCODPLLBandSet()
2671 CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; in CMU_DPLLLock()
2991 CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; in CMU_HFXOInit()
[all …]
/hal_silabs-latest/simplicity_sdk/platform/emlib/inc/
Dem_chip.h354 CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; in CHIP_Init()
367 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in CHIP_Init()
370 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in CHIP_Init()
407 CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; in CHIP_Init()
426 CMU->CLKEN0_SET = _CMU_CLKEN0_HFRCO0_MASK; in CHIP_Init()
Dem_syscfg.h59 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SYSCFG_readChipRev()
/hal_silabs-latest/gecko/emlib/src/
Dem_se.c315 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_executeCommand()
389 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in rootIsOutputMailboxValid()
443 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_getVersion()
502 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_getConfigStatusBits()
541 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_getOTPVersion()
579 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_isCommandCompleted()
608 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_readExecutedCommand()
645 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_readCommandResponse()
693 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SE_ackCommand()
Dem_emu.c724 CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0; in dpllState()
1713 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in EMU_RamPowerDown()
1766 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in EMU_RamPowerUp()
3290 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_DCDCBoostInit()
3334 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_EM01BoostPeakCurrentSet()
3412 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_DCDCModeSet()
3488 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_DCDCInit()
3557 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_EM01PeakCurrentSet()
3618 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_DCDCSetPFMXModePeakCurrent()
3657 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in EMU_DCDCSetPFMXTimeoutMaxCtrl()
Dem_cmu.c1470 CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; in sli_em_cmu_HFXOSetForceEnable()
1487 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in sli_em_cmu_SYSTICEXTCLKENSet()
1511 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in sli_em_cmu_SYSTICEXTCLKENClear()
1562 CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; in CMU_ClockSelectSet()
1739 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in CMU_ClockSelectSet()
1752 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in CMU_ClockSelectSet()
2409 CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; in CMU_LF_ClockPrecisionGet()
2504 CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; in CMU_HFRCODPLLBandSet()
2642 CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; in CMU_DPLLLock()
2962 CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; in CMU_HFXOInit()
[all …]
Dem_system.c74 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in SYSTEM_ChipRevisionGet()
/hal_silabs-latest/gecko/emlib/inc/
Dem_chip.h350 CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; in CHIP_Init()
363 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in CHIP_Init()
366 CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; in CHIP_Init()
403 CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; in CHIP_Init()
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Source/
Dsystem_efr32fg23.c223 CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; in SystemHFRCODPLLClockGet()
530 CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; in SystemHFRCOEM23ClockGet()
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Source/
Dsystem_efr32zg23.c223 CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; in SystemHFRCODPLLClockGet()
530 CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; in SystemHFRCOEM23ClockGet()
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Source/
Dsystem_efr32mg24.c223 CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; in SystemHFRCODPLLClockGet()
530 CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; in SystemHFRCOEM23ClockGet()
/hal_silabs-latest/simplicity_sdk/platform/service/power_manager/src/sleep_loop/
Dsl_power_manager_hal_s2.c195 CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; in sli_power_manager_init_hardware()
197 CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0; in sli_power_manager_init_hardware()
/hal_silabs-latest/simplicity_sdk/platform/security/sl_component/se_manager/src/
Dsli_se_manager_mailbox.c168 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in get_root_mailbox_output()
307 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in sli_se_mailbox_execute_command()
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Source/
Dsystem_efr32bg22.c223 CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; in SystemHFRCODPLLClockGet()
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Source/
Dsystem_efr32mg29.c223 CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; in SystemHFRCODPLLClockGet()
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Source/
Dsystem_efr32bg29.c223 CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; in SystemHFRCODPLLClockGet()
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Source/
Dsystem_efr32bg27.c223 CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; in SystemHFRCODPLLClockGet()
/hal_silabs-latest/simplicity_sdk/platform/service/hfxo_manager/src/
Dsl_hfxo_manager_hal_s2.c140 CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; in sli_hfxo_manager_init_hardware()
/hal_silabs-latest/simplicity_sdk/platform/service/sleeptimer/src/
Dsl_sleeptimer_hal_prortc.c452 CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; in sleeptimer_hal_get_clock_accuracy()
/hal_silabs-latest/simplicity_sdk/platform/peripheral/src/
Dsl_hal_system.c181 CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; in sl_hal_system_get_chip_revision()
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27_cmu.h105 …__IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 … member
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22_cmu.h106 …__IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 … member
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/
Defr32mg29_cmu.h106 …__IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 … member

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