1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_EPCACH_A_REGISTERS_H__ 27 #define __SI32_EPCACH_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_EPCACH_A_MODE_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Channel Output Function Select 42 volatile uint32_t COSEL: 2; 43 // PWM N-Bit Mode 44 volatile uint32_t PWMMD: 4; 45 // Differential Signal Generator Enable 46 volatile uint32_t DIFGEN: 1; 47 uint32_t reserved0: 1; 48 // Channel Operating Mode 49 volatile uint32_t CMD: 3; 50 uint32_t reserved1: 21; 51 }; 52 volatile uint32_t U32; 53 }; 54 }; 55 56 #define SI32_EPCACH_A_MODE_COSEL_MASK 0x00000003 57 #define SI32_EPCACH_A_MODE_COSEL_SHIFT 0 58 // Toggle the channel output at the next capture/compare, overflow, or intermediate 59 // event. 60 #define SI32_EPCACH_A_MODE_COSEL_TOGGLE_OUTPUT_VALUE 0 61 #define SI32_EPCACH_A_MODE_COSEL_TOGGLE_OUTPUT_U32 \ 62 (SI32_EPCACH_A_MODE_COSEL_TOGGLE_OUTPUT_VALUE << SI32_EPCACH_A_MODE_COSEL_SHIFT) 63 // Set the channel output at the next capture/compare, overflow, or intermediate 64 // event. 65 #define SI32_EPCACH_A_MODE_COSEL_SET_OUTPUT_VALUE 1 66 #define SI32_EPCACH_A_MODE_COSEL_SET_OUTPUT_U32 \ 67 (SI32_EPCACH_A_MODE_COSEL_SET_OUTPUT_VALUE << SI32_EPCACH_A_MODE_COSEL_SHIFT) 68 // Clear the output at the next capture/compare, overflow, or intermediate event. 69 #define SI32_EPCACH_A_MODE_COSEL_CLEAR_OUTPUT_VALUE 2 70 #define SI32_EPCACH_A_MODE_COSEL_CLEAR_OUTPUT_U32 \ 71 (SI32_EPCACH_A_MODE_COSEL_CLEAR_OUTPUT_VALUE << SI32_EPCACH_A_MODE_COSEL_SHIFT) 72 // Capture/Compare, overflow, or intermediate events do not control the output 73 // state. 74 #define SI32_EPCACH_A_MODE_COSEL_NO_CHANGE_VALUE 3 75 #define SI32_EPCACH_A_MODE_COSEL_NO_CHANGE_U32 \ 76 (SI32_EPCACH_A_MODE_COSEL_NO_CHANGE_VALUE << SI32_EPCACH_A_MODE_COSEL_SHIFT) 77 78 #define SI32_EPCACH_A_MODE_PWMMD_MASK 0x0000003C 79 #define SI32_EPCACH_A_MODE_PWMMD_SHIFT 2 80 81 #define SI32_EPCACH_A_MODE_DIFGEN_MASK 0x00000040 82 #define SI32_EPCACH_A_MODE_DIFGEN_SHIFT 6 83 // Disable the differential signal generator. The channel will output a single non- 84 // differential output. 85 #define SI32_EPCACH_A_MODE_DIFGEN_DISABLED_VALUE 0 86 #define SI32_EPCACH_A_MODE_DIFGEN_DISABLED_U32 \ 87 (SI32_EPCACH_A_MODE_DIFGEN_DISABLED_VALUE << SI32_EPCACH_A_MODE_DIFGEN_SHIFT) 88 // Enable the differential signal generator. The channel will output two 89 // differential outputs: X Phase (XPH) and Y Phase (YPH). 90 #define SI32_EPCACH_A_MODE_DIFGEN_ENABLED_VALUE 1 91 #define SI32_EPCACH_A_MODE_DIFGEN_ENABLED_U32 \ 92 (SI32_EPCACH_A_MODE_DIFGEN_ENABLED_VALUE << SI32_EPCACH_A_MODE_DIFGEN_SHIFT) 93 94 #define SI32_EPCACH_A_MODE_CMD_MASK 0x00000700 95 #define SI32_EPCACH_A_MODE_CMD_SHIFT 8 96 // Configure the channel for edge-aligned PWM mode. 97 #define SI32_EPCACH_A_MODE_CMD_EDGE_PWM_VALUE 0 98 #define SI32_EPCACH_A_MODE_CMD_EDGE_PWM_U32 \ 99 (SI32_EPCACH_A_MODE_CMD_EDGE_PWM_VALUE << SI32_EPCACH_A_MODE_CMD_SHIFT) 100 // Configure the channel for center-aligned PWM mode. 101 #define SI32_EPCACH_A_MODE_CMD_CENTER_ALIGNED_PWM_VALUE 1 102 #define SI32_EPCACH_A_MODE_CMD_CENTER_ALIGNED_PWM_U32 \ 103 (SI32_EPCACH_A_MODE_CMD_CENTER_ALIGNED_PWM_VALUE << SI32_EPCACH_A_MODE_CMD_SHIFT) 104 // Configure the channel for high-frequency/square-wave mode. 105 #define SI32_EPCACH_A_MODE_CMD_HF_SQUARE_WAVE_VALUE 2 106 #define SI32_EPCACH_A_MODE_CMD_HF_SQUARE_WAVE_U32 \ 107 (SI32_EPCACH_A_MODE_CMD_HF_SQUARE_WAVE_VALUE << SI32_EPCACH_A_MODE_CMD_SHIFT) 108 // Configure the channel for timer/capture mode. 109 #define SI32_EPCACH_A_MODE_CMD_TIMER_CAPTURE_VALUE 3 110 #define SI32_EPCACH_A_MODE_CMD_TIMER_CAPTURE_U32 \ 111 (SI32_EPCACH_A_MODE_CMD_TIMER_CAPTURE_VALUE << SI32_EPCACH_A_MODE_CMD_SHIFT) 112 // Configure the channel for n-bit edge-aligned PWM mode. 113 #define SI32_EPCACH_A_MODE_CMD_N_BIT_PWM_VALUE 4 114 #define SI32_EPCACH_A_MODE_CMD_N_BIT_PWM_U32 \ 115 (SI32_EPCACH_A_MODE_CMD_N_BIT_PWM_VALUE << SI32_EPCACH_A_MODE_CMD_SHIFT) 116 117 118 119 struct SI32_EPCACH_A_CONTROL_Struct 120 { 121 union 122 { 123 struct 124 { 125 // Channel Output State 126 volatile uint32_t COUTST: 1; 127 // Positive Edge Input Capture Enable 128 volatile uint32_t CPCAPEN: 1; 129 // Negative Edge Input Capture Enable 130 volatile uint32_t CNCAPEN: 1; 131 // Channel Register Update Complete Flag 132 volatile uint32_t CUPDCF: 1; 133 uint32_t reserved0: 1; 134 // Differential Y Phase State 135 volatile uint32_t YPHST: 1; 136 // Active Channel Select 137 volatile uint32_t ACTIVEPH: 1; 138 // Differential X Phase State 139 volatile uint32_t XPHST: 1; 140 // Capture/Compare Interrupt Enable 141 volatile uint32_t CCIEN: 1; 142 // Capture/Compare DMA Request Enable 143 volatile uint32_t CCDEN: 1; 144 // Capture/Compare Synchronization Signal Enable 145 volatile uint32_t CCSEN: 1; 146 // Intermediate Overflow Interrupt Enable 147 volatile uint32_t CIOVFIEN: 1; 148 // Intermediate Overflow DMA Request Enable 149 volatile uint32_t CIOVFDEN: 1; 150 // Intermediate Overflow Synchronization Signal Enable 151 volatile uint32_t CIOVFSEN: 1; 152 uint32_t reserved1: 18; 153 }; 154 volatile uint32_t U32; 155 }; 156 }; 157 158 #define SI32_EPCACH_A_CONTROL_COUTST_MASK 0x00000001 159 #define SI32_EPCACH_A_CONTROL_COUTST_SHIFT 0 160 // The channel output state is low. 161 #define SI32_EPCACH_A_CONTROL_COUTST_LOW_VALUE 0 162 #define SI32_EPCACH_A_CONTROL_COUTST_LOW_U32 \ 163 (SI32_EPCACH_A_CONTROL_COUTST_LOW_VALUE << SI32_EPCACH_A_CONTROL_COUTST_SHIFT) 164 // The channel output state is high. 165 #define SI32_EPCACH_A_CONTROL_COUTST_HIGH_VALUE 1 166 #define SI32_EPCACH_A_CONTROL_COUTST_HIGH_U32 \ 167 (SI32_EPCACH_A_CONTROL_COUTST_HIGH_VALUE << SI32_EPCACH_A_CONTROL_COUTST_SHIFT) 168 169 #define SI32_EPCACH_A_CONTROL_CPCAPEN_MASK 0x00000002 170 #define SI32_EPCACH_A_CONTROL_CPCAPEN_SHIFT 1 171 // Disable positive-edge input capture. 172 #define SI32_EPCACH_A_CONTROL_CPCAPEN_DISABLED_VALUE 0 173 #define SI32_EPCACH_A_CONTROL_CPCAPEN_DISABLED_U32 \ 174 (SI32_EPCACH_A_CONTROL_CPCAPEN_DISABLED_VALUE << SI32_EPCACH_A_CONTROL_CPCAPEN_SHIFT) 175 // Enable positive-edge input capture. 176 #define SI32_EPCACH_A_CONTROL_CPCAPEN_ENABLED_VALUE 1 177 #define SI32_EPCACH_A_CONTROL_CPCAPEN_ENABLED_U32 \ 178 (SI32_EPCACH_A_CONTROL_CPCAPEN_ENABLED_VALUE << SI32_EPCACH_A_CONTROL_CPCAPEN_SHIFT) 179 180 #define SI32_EPCACH_A_CONTROL_CNCAPEN_MASK 0x00000004 181 #define SI32_EPCACH_A_CONTROL_CNCAPEN_SHIFT 2 182 // Disable negative-edge input capture. 183 #define SI32_EPCACH_A_CONTROL_CNCAPEN_DISABLED_VALUE 0 184 #define SI32_EPCACH_A_CONTROL_CNCAPEN_DISABLED_U32 \ 185 (SI32_EPCACH_A_CONTROL_CNCAPEN_DISABLED_VALUE << SI32_EPCACH_A_CONTROL_CNCAPEN_SHIFT) 186 // Enable negative-edge input capture. 187 #define SI32_EPCACH_A_CONTROL_CNCAPEN_ENABLED_VALUE 1 188 #define SI32_EPCACH_A_CONTROL_CNCAPEN_ENABLED_U32 \ 189 (SI32_EPCACH_A_CONTROL_CNCAPEN_ENABLED_VALUE << SI32_EPCACH_A_CONTROL_CNCAPEN_SHIFT) 190 191 #define SI32_EPCACH_A_CONTROL_CUPDCF_MASK 0x00000008 192 #define SI32_EPCACH_A_CONTROL_CUPDCF_SHIFT 3 193 // A EPCA channel register update completed or is not pending. 194 #define SI32_EPCACH_A_CONTROL_CUPDCF_NOT_SET_VALUE 0 195 #define SI32_EPCACH_A_CONTROL_CUPDCF_NOT_SET_U32 \ 196 (SI32_EPCACH_A_CONTROL_CUPDCF_NOT_SET_VALUE << SI32_EPCACH_A_CONTROL_CUPDCF_SHIFT) 197 // A EPCA channel register update has not completed and is still pending. 198 #define SI32_EPCACH_A_CONTROL_CUPDCF_SET_VALUE 1 199 #define SI32_EPCACH_A_CONTROL_CUPDCF_SET_U32 \ 200 (SI32_EPCACH_A_CONTROL_CUPDCF_SET_VALUE << SI32_EPCACH_A_CONTROL_CUPDCF_SHIFT) 201 202 #define SI32_EPCACH_A_CONTROL_YPHST_MASK 0x00000020 203 #define SI32_EPCACH_A_CONTROL_YPHST_SHIFT 5 204 // Set the Y Phase output state to low. 205 #define SI32_EPCACH_A_CONTROL_YPHST_LOW_VALUE 0 206 #define SI32_EPCACH_A_CONTROL_YPHST_LOW_U32 \ 207 (SI32_EPCACH_A_CONTROL_YPHST_LOW_VALUE << SI32_EPCACH_A_CONTROL_YPHST_SHIFT) 208 // Set the Y Phase output state to high. 209 #define SI32_EPCACH_A_CONTROL_YPHST_HIGH_VALUE 1 210 #define SI32_EPCACH_A_CONTROL_YPHST_HIGH_U32 \ 211 (SI32_EPCACH_A_CONTROL_YPHST_HIGH_VALUE << SI32_EPCACH_A_CONTROL_YPHST_SHIFT) 212 213 #define SI32_EPCACH_A_CONTROL_ACTIVEPH_MASK 0x00000040 214 #define SI32_EPCACH_A_CONTROL_ACTIVEPH_SHIFT 6 215 // The Y Phase is active and X Phase is inactive. 216 #define SI32_EPCACH_A_CONTROL_ACTIVEPH_YACTIVE_VALUE 0 217 #define SI32_EPCACH_A_CONTROL_ACTIVEPH_YACTIVE_U32 \ 218 (SI32_EPCACH_A_CONTROL_ACTIVEPH_YACTIVE_VALUE << SI32_EPCACH_A_CONTROL_ACTIVEPH_SHIFT) 219 // The X Phase is active and Y Phase is inactive. 220 #define SI32_EPCACH_A_CONTROL_ACTIVEPH_XACTIVE_VALUE 1 221 #define SI32_EPCACH_A_CONTROL_ACTIVEPH_XACTIVE_U32 \ 222 (SI32_EPCACH_A_CONTROL_ACTIVEPH_XACTIVE_VALUE << SI32_EPCACH_A_CONTROL_ACTIVEPH_SHIFT) 223 224 #define SI32_EPCACH_A_CONTROL_XPHST_MASK 0x00000080 225 #define SI32_EPCACH_A_CONTROL_XPHST_SHIFT 7 226 // Set the X Phase output state to low. 227 #define SI32_EPCACH_A_CONTROL_XPHST_LOW_VALUE 0 228 #define SI32_EPCACH_A_CONTROL_XPHST_LOW_U32 \ 229 (SI32_EPCACH_A_CONTROL_XPHST_LOW_VALUE << SI32_EPCACH_A_CONTROL_XPHST_SHIFT) 230 // Set the X Phase output state to high. 231 #define SI32_EPCACH_A_CONTROL_XPHST_HIGH_VALUE 1 232 #define SI32_EPCACH_A_CONTROL_XPHST_HIGH_U32 \ 233 (SI32_EPCACH_A_CONTROL_XPHST_HIGH_VALUE << SI32_EPCACH_A_CONTROL_XPHST_SHIFT) 234 235 #define SI32_EPCACH_A_CONTROL_CCIEN_MASK 0x00000100 236 #define SI32_EPCACH_A_CONTROL_CCIEN_SHIFT 8 237 // Disable the channel capture/compare interrupt. 238 #define SI32_EPCACH_A_CONTROL_CCIEN_DISABLED_VALUE 0 239 #define SI32_EPCACH_A_CONTROL_CCIEN_DISABLED_U32 \ 240 (SI32_EPCACH_A_CONTROL_CCIEN_DISABLED_VALUE << SI32_EPCACH_A_CONTROL_CCIEN_SHIFT) 241 // Enable the channel capture/compare interrupt. 242 #define SI32_EPCACH_A_CONTROL_CCIEN_ENABLED_VALUE 1 243 #define SI32_EPCACH_A_CONTROL_CCIEN_ENABLED_U32 \ 244 (SI32_EPCACH_A_CONTROL_CCIEN_ENABLED_VALUE << SI32_EPCACH_A_CONTROL_CCIEN_SHIFT) 245 246 #define SI32_EPCACH_A_CONTROL_CCDEN_MASK 0x00000200 247 #define SI32_EPCACH_A_CONTROL_CCDEN_SHIFT 9 248 // Do not request DMA data when a channel capture/compare event occurs. 249 #define SI32_EPCACH_A_CONTROL_CCDEN_DISABLED_VALUE 0 250 #define SI32_EPCACH_A_CONTROL_CCDEN_DISABLED_U32 \ 251 (SI32_EPCACH_A_CONTROL_CCDEN_DISABLED_VALUE << SI32_EPCACH_A_CONTROL_CCDEN_SHIFT) 252 // Request DMA data when a channel capture/compare event occurs. 253 #define SI32_EPCACH_A_CONTROL_CCDEN_ENABLED_VALUE 1 254 #define SI32_EPCACH_A_CONTROL_CCDEN_ENABLED_U32 \ 255 (SI32_EPCACH_A_CONTROL_CCDEN_ENABLED_VALUE << SI32_EPCACH_A_CONTROL_CCDEN_SHIFT) 256 257 #define SI32_EPCACH_A_CONTROL_CCSEN_MASK 0x00000400 258 #define SI32_EPCACH_A_CONTROL_CCSEN_SHIFT 10 259 // Do not send a synchronization signal when a channel capture/compare event 260 // occurs. 261 #define SI32_EPCACH_A_CONTROL_CCSEN_DISABLED_VALUE 0 262 #define SI32_EPCACH_A_CONTROL_CCSEN_DISABLED_U32 \ 263 (SI32_EPCACH_A_CONTROL_CCSEN_DISABLED_VALUE << SI32_EPCACH_A_CONTROL_CCSEN_SHIFT) 264 // Send a synchronization signal when a channel capture/compare event occurs. 265 #define SI32_EPCACH_A_CONTROL_CCSEN_ENABLED_VALUE 1 266 #define SI32_EPCACH_A_CONTROL_CCSEN_ENABLED_U32 \ 267 (SI32_EPCACH_A_CONTROL_CCSEN_ENABLED_VALUE << SI32_EPCACH_A_CONTROL_CCSEN_SHIFT) 268 269 #define SI32_EPCACH_A_CONTROL_CIOVFIEN_MASK 0x00000800 270 #define SI32_EPCACH_A_CONTROL_CIOVFIEN_SHIFT 11 271 // Disable the channel intermediate overflow interrupt. 272 #define SI32_EPCACH_A_CONTROL_CIOVFIEN_DISABLED_VALUE 0 273 #define SI32_EPCACH_A_CONTROL_CIOVFIEN_DISABLED_U32 \ 274 (SI32_EPCACH_A_CONTROL_CIOVFIEN_DISABLED_VALUE << SI32_EPCACH_A_CONTROL_CIOVFIEN_SHIFT) 275 // Enable the channel intermediate overflow interrupt. 276 #define SI32_EPCACH_A_CONTROL_CIOVFIEN_ENABLED_VALUE 1 277 #define SI32_EPCACH_A_CONTROL_CIOVFIEN_ENABLED_U32 \ 278 (SI32_EPCACH_A_CONTROL_CIOVFIEN_ENABLED_VALUE << SI32_EPCACH_A_CONTROL_CIOVFIEN_SHIFT) 279 280 #define SI32_EPCACH_A_CONTROL_CIOVFDEN_MASK 0x00001000 281 #define SI32_EPCACH_A_CONTROL_CIOVFDEN_SHIFT 12 282 // Do not request DMA data when a channel intermediate overflow event occurs. 283 #define SI32_EPCACH_A_CONTROL_CIOVFDEN_DISABLED_VALUE 0 284 #define SI32_EPCACH_A_CONTROL_CIOVFDEN_DISABLED_U32 \ 285 (SI32_EPCACH_A_CONTROL_CIOVFDEN_DISABLED_VALUE << SI32_EPCACH_A_CONTROL_CIOVFDEN_SHIFT) 286 // Request DMA data when a channel intermediate overflow event occurs. 287 #define SI32_EPCACH_A_CONTROL_CIOVFDEN_ENABLED_VALUE 1 288 #define SI32_EPCACH_A_CONTROL_CIOVFDEN_ENABLED_U32 \ 289 (SI32_EPCACH_A_CONTROL_CIOVFDEN_ENABLED_VALUE << SI32_EPCACH_A_CONTROL_CIOVFDEN_SHIFT) 290 291 #define SI32_EPCACH_A_CONTROL_CIOVFSEN_MASK 0x00002000 292 #define SI32_EPCACH_A_CONTROL_CIOVFSEN_SHIFT 13 293 // Do not send a synchronization signal when a channel intermediate overflow event 294 // occurs. 295 #define SI32_EPCACH_A_CONTROL_CIOVFSEN_DISABLED_VALUE 0 296 #define SI32_EPCACH_A_CONTROL_CIOVFSEN_DISABLED_U32 \ 297 (SI32_EPCACH_A_CONTROL_CIOVFSEN_DISABLED_VALUE << SI32_EPCACH_A_CONTROL_CIOVFSEN_SHIFT) 298 // Send a synchronization signal when a channel intermediate overflow occurs. 299 #define SI32_EPCACH_A_CONTROL_CIOVFSEN_ENABLED_VALUE 1 300 #define SI32_EPCACH_A_CONTROL_CIOVFSEN_ENABLED_U32 \ 301 (SI32_EPCACH_A_CONTROL_CIOVFSEN_ENABLED_VALUE << SI32_EPCACH_A_CONTROL_CIOVFSEN_SHIFT) 302 303 304 305 struct SI32_EPCACH_A_CCAPV_Struct 306 { 307 union 308 { 309 struct 310 { 311 // Channel Compare Value 312 volatile uint32_t CCAPV_BITS: 18; 313 uint32_t reserved0: 14; 314 }; 315 volatile uint32_t U32; 316 }; 317 }; 318 319 #define SI32_EPCACH_A_CCAPV_CCAPV_MASK 0x0003FFFF 320 #define SI32_EPCACH_A_CCAPV_CCAPV_SHIFT 0 321 322 323 324 struct SI32_EPCACH_A_CCAPVUPD_Struct 325 { 326 union 327 { 328 struct 329 { 330 // Channel Compare Update Value 331 volatile uint32_t CCAPVUPD_BITS: 18; 332 uint32_t reserved0: 14; 333 }; 334 volatile uint32_t U32; 335 }; 336 }; 337 338 #define SI32_EPCACH_A_CCAPVUPD_CCAPVUPD_MASK 0x0003FFFF 339 #define SI32_EPCACH_A_CCAPVUPD_CCAPVUPD_SHIFT 0 340 341 342 343 typedef struct SI32_EPCACH_A_Struct 344 { 345 struct SI32_EPCACH_A_MODE_Struct MODE ; // Base Address + 0x0 346 uint32_t reserved0; 347 uint32_t reserved1; 348 uint32_t reserved2; 349 struct SI32_EPCACH_A_CONTROL_Struct CONTROL ; // Base Address + 0x10 350 volatile uint32_t CONTROL_SET; 351 volatile uint32_t CONTROL_CLR; 352 uint32_t reserved3; 353 struct SI32_EPCACH_A_CCAPV_Struct CCAPV ; // Base Address + 0x20 354 uint32_t reserved4; 355 uint32_t reserved5; 356 uint32_t reserved6; 357 struct SI32_EPCACH_A_CCAPVUPD_Struct CCAPVUPD ; // Base Address + 0x30 358 uint32_t reserved7; 359 uint32_t reserved8; 360 uint32_t reserved9; 361 } SI32_EPCACH_A_Type; 362 363 #ifdef __cplusplus 364 } 365 #endif 366 367 #endif // __SI32_EPCACH_A_REGISTERS_H__ 368 369 //-eof-------------------------------------------------------------------------- 370 371
