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Searched refs:BUS_RegMaskedWrite (Results 1 – 22 of 22) sorted by relevance

/hal_silabs-latest/gecko/emlib/src/
Dem_gpio.c126 BUS_RegMaskedWrite(&GPIO->P[port].CTRL, in GPIO_DriveStrengthSet()
199 BUS_RegMaskedWrite(&GPIO->EXTIPSELL, in GPIO_ExtIntConfig()
207 BUS_RegMaskedWrite(&GPIO->EXTIPSELH, in GPIO_ExtIntConfig()
212 BUS_RegMaskedWrite(&GPIO->EXTIPSELH, in GPIO_ExtIntConfig()
227 BUS_RegMaskedWrite(&GPIO->EXTIPINSELL, in GPIO_ExtIntConfig()
234 BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, in GPIO_ExtIntConfig()
241 BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, in GPIO_ExtIntConfig()
369 BUS_RegMaskedWrite(&(GPIO->P[port].MODEL), 0xFu << (pin * 4), (uint32_t)mode << (pin * 4)); in GPIO_PinModeSet()
371 …BUS_RegMaskedWrite(&(GPIO->P[port].MODEH), 0xFu << ((pin - 8) * 4), (uint32_t)mode << ((pin - 8) *… in GPIO_PinModeSet()
Dem_acmp.c270 BUS_RegMaskedWrite(&acmp->INPUTCTRL, _ACMP_INPUTCTRL_POSSEL_MASK, in ACMP_CapsenseChannelSet()
274 BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_POSSEL_MASK, in ACMP_CapsenseChannelSet()
471 BUS_RegMaskedWrite(&acmp->CTRL, _ACMP_CTRL_GPIOINV_MASK, in ACMP_GPIOSetup()
609 BUS_RegMaskedWrite(&acmp->INPUTCTRL, _ACMP_INPUTCTRL_VREFDIV_MASK, in ACMP_Init()
673 BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VASEL_MASK, in ACMP_VASetup()
675 BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVA_MASK, in ACMP_VASetup()
677 BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVA_MASK, in ACMP_VASetup()
699 BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VBSEL_MASK, in ACMP_VBSetup()
701 BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVB_MASK, in ACMP_VBSetup()
703 BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVB_MASK, in ACMP_VBSetup()
Dem_lcd.c1178 BUS_RegMaskedWrite(segmentRegister, 0xF << bitShift, biasLevel << bitShift); in LCD_BiasSegmentSet()
1232 BUS_RegMaskedWrite(comRegister, 0xF << bitShift, biasLevel << bitShift); in LCD_BiasComSet()
1239 BUS_RegMaskedWrite(&(LCD->SEGD4L), 0xF << bitShift, biasLevel << bitShift); in LCD_BiasComSet()
Dem_msc.c1999 BUS_RegMaskedWrite(&SYSCFG->DMEM0PORTMAPSEL, in MSC_DmemPortMapSet()
2033 BUS_RegMaskedWrite(&DMEM->CTRL, in MSC_PortSetPriority()
2039 BUS_RegMaskedWrite(&DMEM0->CTRL, in MSC_PortSetPriority()
2042 BUS_RegMaskedWrite(&DMEM1->CTRL, in MSC_PortSetPriority()
Dem_cmu.c2989 BUS_RegMaskedWrite(&HFXO0->BUFOUTTRIM, in CMU_HFXOInit()
3002 BUS_RegMaskedWrite(&HFXO0->LOWPWRCTRL, in CMU_HFXOInit()
3028 BUS_RegMaskedWrite((volatile uint32_t*)(HFXO0_BASE + 0x38U), in CMU_HFXOInit()
3111 BUS_RegMaskedWrite((volatile uint32_t *)(HFXO0_BASE + 0x34U), in CMU_HFXOInit()
3175 BUS_RegMaskedWrite(&HFXO0->BUFOUTCTRL, in CMU_HFXOStartCrystalSharingLeader()
3254 BUS_RegMaskedWrite(&HFXO0->CTRL, mask, value); in CMU_HFXOCrystalSharingFollowerInit()
3270 BUS_RegMaskedWrite(&(PRS->ASYNC_CH[prsAsyncCh].CTRL), mask, value); in CMU_HFXOCrystalSharingFollowerInit()
3344 BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); in CMU_HFXOCTuneSet()
3348 BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxoCtrlBkup); in CMU_HFXOCTuneSet()
3397 BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); in CMU_HFXOCTuneGet()
[all …]
Dem_i2c.c287 BUS_RegMaskedWrite(&i2c->CTRL, in I2C_BusFreqSet()
Dem_can.c587 BUS_RegMaskedWrite(&can->STATUS, _CAN_STATUS_LEC_MASK, 0x7); in CAN_SendMessage()
Dem_adc.c426 BUS_RegMaskedWrite(&adc->CTRL, in ADC_Init()
Dem_emu.c3344 BUS_RegMaskedWrite(&DCDC->BSTEM01CTRL, in EMU_EM01BoostPeakCurrentSet()
3576 BUS_RegMaskedWrite(&DCDC->EM01CTRL0, in EMU_EM01PeakCurrentSet()
/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_gpio.c126 BUS_RegMaskedWrite(&GPIO->P[port].CTRL, in GPIO_DriveStrengthSet()
199 BUS_RegMaskedWrite(&GPIO->EXTIPSELL, in GPIO_ExtIntConfig()
207 BUS_RegMaskedWrite(&GPIO->EXTIPSELH, in GPIO_ExtIntConfig()
212 BUS_RegMaskedWrite(&GPIO->EXTIPSELH, in GPIO_ExtIntConfig()
227 BUS_RegMaskedWrite(&GPIO->EXTIPINSELL, in GPIO_ExtIntConfig()
234 BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, in GPIO_ExtIntConfig()
241 BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, in GPIO_ExtIntConfig()
369 BUS_RegMaskedWrite(&(GPIO->P[port].MODEL), 0xFu << (pin * 4), (uint32_t)mode << (pin * 4)); in GPIO_PinModeSet()
371 …BUS_RegMaskedWrite(&(GPIO->P[port].MODEH), 0xFu << ((pin - 8) * 4), (uint32_t)mode << ((pin - 8) *… in GPIO_PinModeSet()
Dem_acmp.c270 BUS_RegMaskedWrite(&acmp->INPUTCTRL, _ACMP_INPUTCTRL_POSSEL_MASK, in ACMP_CapsenseChannelSet()
274 BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_POSSEL_MASK, in ACMP_CapsenseChannelSet()
471 BUS_RegMaskedWrite(&acmp->CTRL, _ACMP_CTRL_GPIOINV_MASK, in ACMP_GPIOSetup()
609 BUS_RegMaskedWrite(&acmp->INPUTCTRL, _ACMP_INPUTCTRL_VREFDIV_MASK, in ACMP_Init()
673 BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VASEL_MASK, in ACMP_VASetup()
675 BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVA_MASK, in ACMP_VASetup()
677 BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVA_MASK, in ACMP_VASetup()
699 BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VBSEL_MASK, in ACMP_VBSetup()
701 BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVB_MASK, in ACMP_VBSetup()
703 BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVB_MASK, in ACMP_VBSetup()
Dem_lcd.c1178 BUS_RegMaskedWrite(segmentRegister, 0xF << bitShift, biasLevel << bitShift); in LCD_BiasSegmentSet()
1232 BUS_RegMaskedWrite(comRegister, 0xF << bitShift, biasLevel << bitShift); in LCD_BiasComSet()
1239 BUS_RegMaskedWrite(&(LCD->SEGD4L), 0xF << bitShift, biasLevel << bitShift); in LCD_BiasComSet()
Dem_msc.c2005 BUS_RegMaskedWrite(&SYSCFG->DMEM0PORTMAPSEL, in MSC_DmemPortMapSet()
2039 BUS_RegMaskedWrite(&DMEM->CTRL, in MSC_PortSetPriority()
2045 BUS_RegMaskedWrite(&DMEM0->CTRL, in MSC_PortSetPriority()
2048 BUS_RegMaskedWrite(&DMEM1->CTRL, in MSC_PortSetPriority()
Dem_cmu.c3018 BUS_RegMaskedWrite(&HFXO0->BUFOUTTRIM, in CMU_HFXOInit()
3031 BUS_RegMaskedWrite(&HFXO0->LOWPWRCTRL, in CMU_HFXOInit()
3056 BUS_RegMaskedWrite((volatile uint32_t*)(HFXO0_BASE + 0x38U), in CMU_HFXOInit()
3139 BUS_RegMaskedWrite((volatile uint32_t *)(HFXO0_BASE + 0x34U), in CMU_HFXOInit()
3203 BUS_RegMaskedWrite(&HFXO0->BUFOUTCTRL, in CMU_HFXOStartCrystalSharingLeader()
3282 BUS_RegMaskedWrite(&HFXO0->CTRL, mask, value); in CMU_HFXOCrystalSharingFollowerInit()
3298 BUS_RegMaskedWrite(&(PRS->ASYNC_CH[prsAsyncCh].CTRL), mask, value); in CMU_HFXOCrystalSharingFollowerInit()
3372 BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); in CMU_HFXOCTuneSet()
3376 BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxoCtrlBkup); in CMU_HFXOCTuneSet()
3425 BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); in CMU_HFXOCTuneGet()
[all …]
Dem_emu.c3357 BUS_RegMaskedWrite(&DCDC->CTRL, in EMU_DCDCBoostInit()
3405 BUS_RegMaskedWrite(&DCDC->BSTEM01CTRL, in EMU_EM01BoostPeakCurrentSet()
3459 BUS_RegMaskedWrite(&DCDC->CTRL, in EMU_DCDCBoostOutputVoltageSet()
3671 BUS_RegMaskedWrite(&DCDC->EM01CTRL0, in EMU_EM01PeakCurrentSet()
Dem_i2c.c287 BUS_RegMaskedWrite(&i2c->CTRL, in I2C_BusFreqSet()
/hal_silabs-latest/simplicity_sdk/platform/service/clock_manager/src/
Dsl_clock_manager_init_hal_s2.c220 …BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_PRSSTATUSSEL0_MASK, (_HFXO_CTRL_PRSSTATUSSEL0_ENS << _… in init_hfxo()
236 BUS_RegMaskedWrite(&(PRS->ASYNC_CH[HFXO_CRYSTSAL_SHARING_PRS_CHANNEL].CTRL), mask, value); in init_hfxo()
261 BUS_RegMaskedWrite(&HFXO0->BUFOUTCTRL, in init_hfxo()
Dsl_clock_manager_hal_s2.c748 BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxo_ctrl_backup); in sli_clock_manager_hal_hfxo_calibrate_ctune()
/hal_silabs-latest/gecko/emlib/inc/
Dem_bus.h301 __STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, in BUS_RegMaskedWrite() function
Dem_gpio.h830 BUS_RegMaskedWrite(&(GPIO->INSENSE), mask, val); in GPIO_InputSenseSet()
/hal_silabs-latest/simplicity_sdk/platform/emlib/inc/
Dem_bus.h305 __STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, in BUS_RegMaskedWrite() function
Dem_gpio.h915 BUS_RegMaskedWrite(&(GPIO->INSENSE), mask, val); in GPIO_InputSenseSet()