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Searched refs:BUS_RegBitWrite (Results 1 – 25 of 62) sorted by relevance

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/hal_silabs-latest/gecko/emlib/src/
Dem_ebi.c92 BUS_RegBitWrite(&(EBI_GENERIC_ROUTE_REG), bit, val); in EBI_RouteBitWrite()
332 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable); in EBI_BankEnable()
335 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable); in EBI_BankEnable()
338 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable); in EBI_BankEnable()
341 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable); in EBI_BankEnable()
412 BUS_RegBitWrite(&(EBI->NANDCTRL), _EBI_NANDCTRL_BANKSEL_SHIFT, _EBI_NANDCTRL_BANKSEL_BANK0); in EBI_NANDFlashEnable()
415 BUS_RegBitWrite(&(EBI->NANDCTRL), _EBI_NANDCTRL_BANKSEL_SHIFT, _EBI_NANDCTRL_BANKSEL_BANK1); in EBI_NANDFlashEnable()
418 BUS_RegBitWrite(&(EBI->NANDCTRL), _EBI_NANDCTRL_BANKSEL_SHIFT, _EBI_NANDCTRL_BANKSEL_BANK2); in EBI_NANDFlashEnable()
421 BUS_RegBitWrite(&(EBI->NANDCTRL), _EBI_NANDCTRL_BANKSEL_SHIFT, _EBI_NANDCTRL_BANKSEL_BANK3); in EBI_NANDFlashEnable()
423 BUS_RegBitWrite(&(EBI->NANDCTRL), _EBI_NANDCTRL_EN_SHIFT, enable); in EBI_NANDFlashEnable()
[all …]
Dem_lcd.c435 BUS_RegBitWrite(&(LCD->SEGD0), bit, enable); in LCD_SegmentSet()
438 BUS_RegBitWrite(&(LCD->SEGD0H), bit, enable); in LCD_SegmentSet()
441 BUS_RegBitWrite(&(LCD->SEGD0), bit, enable); in LCD_SegmentSet()
448 BUS_RegBitWrite(&(LCD->SEGD1), bit, enable); in LCD_SegmentSet()
451 BUS_RegBitWrite(&(LCD->SEGD1H), bit, enable); in LCD_SegmentSet()
454 BUS_RegBitWrite(&(LCD->SEGD1), bit, enable); in LCD_SegmentSet()
461 BUS_RegBitWrite(&(LCD->SEGD2), bit, enable); in LCD_SegmentSet()
464 BUS_RegBitWrite(&(LCD->SEGD2H), bit, enable); in LCD_SegmentSet()
467 BUS_RegBitWrite(&(LCD->SEGD2), bit, enable); in LCD_SegmentSet()
474 BUS_RegBitWrite(&(LCD->SEGD3), bit, enable); in LCD_SegmentSet()
[all …]
Dem_gpio.c251 BUS_RegBitWrite(&(GPIO->EXTIRISE), intNo, risingEdge); in GPIO_ExtIntConfig()
254 BUS_RegBitWrite(&(GPIO->EXTIFALL), intNo, fallingEdge); in GPIO_ExtIntConfig()
260 BUS_RegBitWrite(&(GPIO->IEN), intNo, enable); in GPIO_ExtIntConfig()
321 BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WU_SHIFT, enable); in GPIO_EM4WUExtIntConfig()
323 BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN_SHIFT, enable); in GPIO_EM4WUExtIntConfig()
325 BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN0_SHIFT, enable); in GPIO_EM4WUExtIntConfig()
Dem_pcnt.c125 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); in PCNT_CounterReset()
128 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); in PCNT_CounterReset()
393 BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S0PRSEN_SHIFT, enable); in PCNT_PRSInputEnable()
395 BUS_RegBitWrite(&(pcnt->CFG), _PCNT_CFG_S0PRSEN_SHIFT, enable); in PCNT_PRSInputEnable()
402 BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S1PRSEN_SHIFT, enable); in PCNT_PRSInputEnable()
404 BUS_RegBitWrite(&(pcnt->CFG), _PCNT_CFG_S1PRSEN_SHIFT, enable); in PCNT_PRSInputEnable()
626 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); in PCNT_Init()
691 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); in PCNT_Init()
820 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); in PCNT_Reset()
832 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); in PCNT_Reset()
Dem_idac.c116 BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_EN_SHIFT, enable); in IDAC_Enable()
167 BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_MINOUTTRANS_SHIFT, enable); in IDAC_MinimalOutputTransitionMode()
337 BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_OUTEN_SHIFT, enable); in IDAC_OutEnable()
339 BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_APORTOUTEN_SHIFT, enable); in IDAC_OutEnable()
367 BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_MAINOUTEN_SHIFT, enable); in IDAC_OutpadEnable()
Dem_burtc.c268 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, (uint32_t) !enable); in BURTC_Enable()
328 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1U); in BURTC_CounterReset()
329 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0U); in BURTC_CounterReset()
352 BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1); in BURTC_Reset()
353 BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState); in BURTC_Reset()
Dem_rmu.c250 BUS_RegBitWrite(&EMU->RSTCTRL, (uint32_t)shift, mode ? 1 : 0); in RMU_ResetControl()
255 BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0); in RMU_ResetControl()
287 BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1); in RMU_ResetCauseClear()
288 BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0); in RMU_ResetCauseClear()
Dem_lesense.c772 BUS_RegBitWrite(&LESENSE->IEN, chIdx, confCh->enaInt); in LESENSE_ChannelConfig()
775 BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, chIdx, confCh->enaPin); in LESENSE_ChannelConfig()
778 BUS_RegBitWrite(&LESENSE->CHEN, chIdx, confCh->enaScanCh); in LESENSE_ChannelConfig()
814 BUS_RegBitWrite(&LESENSE->CTRL, in LESENSE_AltExConfig()
825 BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, in LESENSE_AltExConfig()
837 BUS_RegBitWrite(&LESENSE->ALTEXCONF, in LESENSE_AltExConfig()
853 BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, in LESENSE_AltExConfig()
869 BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, in LESENSE_AltExConfig()
908 BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, chIdx, enaPin); in LESENSE_ChannelEnable()
911 BUS_RegBitWrite(&LESENSE->CHEN, chIdx, enaScanCh); in LESENSE_ChannelEnable()
Dem_dac.c92 BUS_RegBitWrite(reg, _DAC_CH0CTRL_EN_SHIFT, enable); in DAC_Enable()
119 BUS_RegBitWrite(&(dac->CH0CTRL), _DAC_CH0CTRL_EN_SHIFT, 0); in DAC_Init()
120 BUS_RegBitWrite(&(dac->CH1CTRL), _DAC_CH0CTRL_EN_SHIFT, 0); in DAC_Init()
Dem_dma.c685 BUS_RegBitWrite(&(DMA->IEN), channel, 1); in DMA_CfgChannel()
687 BUS_RegBitWrite(&(DMA->IEN), channel, 0); in DMA_CfgChannel()
961 BUS_RegBitWrite(&DMA->CHREQMASKC, channel, 1); in DMA_ChannelRequestEnable()
963 BUS_RegBitWrite(&DMA->CHREQMASKS, channel, 1); in DMA_ChannelRequestEnable()
/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_lcd.c435 BUS_RegBitWrite(&(LCD->SEGD0), bit, enable); in LCD_SegmentSet()
438 BUS_RegBitWrite(&(LCD->SEGD0H), bit, enable); in LCD_SegmentSet()
441 BUS_RegBitWrite(&(LCD->SEGD0), bit, enable); in LCD_SegmentSet()
448 BUS_RegBitWrite(&(LCD->SEGD1), bit, enable); in LCD_SegmentSet()
451 BUS_RegBitWrite(&(LCD->SEGD1H), bit, enable); in LCD_SegmentSet()
454 BUS_RegBitWrite(&(LCD->SEGD1), bit, enable); in LCD_SegmentSet()
461 BUS_RegBitWrite(&(LCD->SEGD2), bit, enable); in LCD_SegmentSet()
464 BUS_RegBitWrite(&(LCD->SEGD2H), bit, enable); in LCD_SegmentSet()
467 BUS_RegBitWrite(&(LCD->SEGD2), bit, enable); in LCD_SegmentSet()
474 BUS_RegBitWrite(&(LCD->SEGD3), bit, enable); in LCD_SegmentSet()
[all …]
Dem_gpio.c251 BUS_RegBitWrite(&(GPIO->EXTIRISE), intNo, risingEdge); in GPIO_ExtIntConfig()
254 BUS_RegBitWrite(&(GPIO->EXTIFALL), intNo, fallingEdge); in GPIO_ExtIntConfig()
260 BUS_RegBitWrite(&(GPIO->IEN), intNo, enable); in GPIO_ExtIntConfig()
321 BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WU_SHIFT, enable); in GPIO_EM4WUExtIntConfig()
323 BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN_SHIFT, enable); in GPIO_EM4WUExtIntConfig()
325 BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN0_SHIFT, enable); in GPIO_EM4WUExtIntConfig()
Dem_pcnt.c125 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); in PCNT_CounterReset()
128 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); in PCNT_CounterReset()
393 BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S0PRSEN_SHIFT, enable); in PCNT_PRSInputEnable()
395 BUS_RegBitWrite(&(pcnt->CFG), _PCNT_CFG_S0PRSEN_SHIFT, enable); in PCNT_PRSInputEnable()
402 BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S1PRSEN_SHIFT, enable); in PCNT_PRSInputEnable()
404 BUS_RegBitWrite(&(pcnt->CFG), _PCNT_CFG_S1PRSEN_SHIFT, enable); in PCNT_PRSInputEnable()
626 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); in PCNT_Init()
691 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); in PCNT_Init()
820 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); in PCNT_Reset()
832 BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); in PCNT_Reset()
Dem_burtc.c270 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, (uint32_t) !enable); in BURTC_Enable()
330 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1U); in BURTC_CounterReset()
331 BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0U); in BURTC_CounterReset()
354 BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1); in BURTC_Reset()
355 BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState); in BURTC_Reset()
Dem_rmu.c256 BUS_RegBitWrite(&EMU->RSTCTRL, (uint32_t)shift, mode ? 1 : 0); in RMU_ResetControl()
262 BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0); in RMU_ResetControl()
297 BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1); in RMU_ResetCauseClear()
298 BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0); in RMU_ResetCauseClear()
Dem_lesense.c772 BUS_RegBitWrite(&LESENSE->IEN, chIdx, confCh->enaInt); in LESENSE_ChannelConfig()
775 BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, chIdx, confCh->enaPin); in LESENSE_ChannelConfig()
778 BUS_RegBitWrite(&LESENSE->CHEN, chIdx, confCh->enaScanCh); in LESENSE_ChannelConfig()
814 BUS_RegBitWrite(&LESENSE->CTRL, in LESENSE_AltExConfig()
825 BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, in LESENSE_AltExConfig()
837 BUS_RegBitWrite(&LESENSE->ALTEXCONF, in LESENSE_AltExConfig()
853 BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, in LESENSE_AltExConfig()
869 BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, in LESENSE_AltExConfig()
908 BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, chIdx, enaPin); in LESENSE_ChannelEnable()
911 BUS_RegBitWrite(&LESENSE->CHEN, chIdx, enaScanCh); in LESENSE_ChannelEnable()
/hal_silabs-latest/simplicity_sdk/platform/emlib/inc/
Dem_gpio.h717 BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, bit); in GPIO_DbgSWDClkEnable()
719 BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT, bit); in GPIO_DbgSWDClkEnable()
721 BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT, bit); in GPIO_DbgSWDClkEnable()
744 BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, bit); in GPIO_DbgSWDIOEnable()
746 BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT, bit); in GPIO_DbgSWDIOEnable()
748 BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT, bit); in GPIO_DbgSWDIOEnable()
778 BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, bit); in GPIO_DbgSWOEnable()
780 BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, bit); in GPIO_DbgSWOEnable()
782 BUS_RegBitWrite(&(GPIO->TRACEROUTEPEN), _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT, bit); in GPIO_DbgSWOEnable()
862 BUS_RegBitWrite(&GPIO->CTRL, _GPIO_CTRL_EM4RET_SHIFT, enable); in GPIO_EM4SetPinRetention()
[all …]
Dem_gpcrc.h185 BUS_RegBitWrite(&gpcrc->EN, _GPCRC_EN_EN_SHIFT, enable); in GPCRC_Enable()
187 BUS_RegBitWrite(&gpcrc->CTRL, _GPCRC_CTRL_EN_SHIFT, enable); in GPCRC_Enable()
Dem_chip.h253 BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); in CHIP_Init()
468 BUS_RegBitWrite((volatile uint32_t *)(0x400E3060UL), 28UL, 0); in CHIP_Reset()
469 BUS_RegBitWrite((volatile uint32_t *)(0x400E3074UL), 0, 0); in CHIP_Reset()
Dem_msc.h774 BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable); in MSC_EnableCache()
786 BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, !enable); in MSC_EnableCacheIRQs()
798 BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, !enable); in MSC_EnableAutoCacheFlush()
/hal_silabs-latest/gecko/emlib/inc/
Dem_gpio.h632 BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, bit); in GPIO_DbgSWDClkEnable()
634 BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT, bit); in GPIO_DbgSWDClkEnable()
636 BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT, bit); in GPIO_DbgSWDClkEnable()
659 BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, bit); in GPIO_DbgSWDIOEnable()
661 BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT, bit); in GPIO_DbgSWDIOEnable()
663 BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT, bit); in GPIO_DbgSWDIOEnable()
693 BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, bit); in GPIO_DbgSWOEnable()
695 BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, bit); in GPIO_DbgSWOEnable()
697 BUS_RegBitWrite(&(GPIO->TRACEROUTEPEN), _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT, bit); in GPIO_DbgSWOEnable()
777 BUS_RegBitWrite(&GPIO->CTRL, _GPIO_CTRL_EM4RET_SHIFT, enable); in GPIO_EM4SetPinRetention()
[all …]
Dem_gpcrc.h185 BUS_RegBitWrite(&gpcrc->EN, _GPCRC_EN_EN_SHIFT, enable); in GPCRC_Enable()
187 BUS_RegBitWrite(&gpcrc->CTRL, _GPCRC_CTRL_EN_SHIFT, enable); in GPCRC_Enable()
Dem_chip.h249 BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); in CHIP_Init()
447 BUS_RegBitWrite((volatile uint32_t *)(0x400E3060UL), 28UL, 0); in CHIP_Reset()
448 BUS_RegBitWrite((volatile uint32_t *)(0x400E3074UL), 0, 0); in CHIP_Reset()
Dem_cryotimer.h358 BUS_RegBitWrite((&CRYOTIMER->EM4WUEN), in CRYOTIMER_EM4WakeupEnable()
372 BUS_RegBitWrite((&CRYOTIMER->CTRL), in CRYOTIMER_Enable()
Dem_msc.h767 BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable); in MSC_EnableCache()
779 BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, !enable); in MSC_EnableCacheIRQs()
791 BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, !enable); in MSC_EnableAutoCacheFlush()

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