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Searched refs:BIT (Results 1 – 25 of 39) sorted by relevance

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/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/wireless/inc/
Dsl_wifi_device.h41 #ifndef BIT
42 #define BIT(a) ((uint32_t)1U << a) macro
75 #define SL_SI91X_FEAT_SECURITY_OPEN BIT(0)
85 #define SL_SI91X_FEAT_SECURITY_PSK BIT(1)
95 #define SL_SI91X_FEAT_AGGREGATION BIT(2)
105 #define SL_SI91X_FEAT_LP_GPIO_BASED_HANDSHAKE BIT(3)
115 #define SL_SI91X_FEAT_ULP_GPIO_BASED_HANDSHAKE BIT(4)
123 #define SL_SI91X_FEAT_DEV_TO_HOST_ULP_GPIO_1 BIT(5)
133 #define SL_SI91X_FEAT_RF_SUPPLY_VOL_3_3_VOLT BIT(6)
141 #define SL_SI91X_FEAT_WPS_DISABLE BIT(7)
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Dsl_si91x_constants.h50 #define SL_SI91X_ENABLE_TLS BIT(0)
53 #define SL_SI91X_TLS_V_1_0 BIT(2)
56 #define SL_SI91X_TLS_V_1_2 BIT(3)
59 #define SL_SI91X_TLS_V_1_1 BIT(4)
63 #define SL_SI91X_TLS_V_1_3 BIT(8)
74 #define SL_SI91X_ENABLE_NULL_DELIMETER BIT(1)
77 #define SL_SI91X_SUPPORT_HTTP_POST_DATA BIT(5)
80 #define SL_SI91X_HTTP_V_1_1 BIT(6)
83 #define SL_SI91X_HTTP_USER_DEFINED_CONTENT_TYPE BIT(7)
86 #define SL_SI91X_HTTPS_CERTIFICATE_INDEX_1 BIT(9)
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/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/
Drsi_power_save.h51 #define M4SS_PWRGATE_ULP_EXT_ROM BIT(22)
52 #define M4SS_PWRGATE_ULP_M4_CORE BIT(18)
53 #define M4SS_PWRGATE_ULP_IID BIT(14)
54 #define M4SS_PWRGATE_ULP_SDIO_SPI BIT(11)
55 #define M4SS_PWRGATE_ULP_RPDMA BIT(9)
57 #define M4SS_PWRGATE_ULP_EFUSE_PERI BIT(4)
58 #define M4SS_PWRGATE_ULP_QSPI_ICACHE BIT(13)
59 #define M4SS_PWRGATE_ULP_M4_DEBUG_FPU BIT(17)
61 #define M4SS_PWRGATE_ULP_EFUSE BIT(4)
62 #define M4SS_PWRGATE_ULP_QSPI BIT(13)
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Drsi_pll.h49 #define CCI_SYNC_MODE BIT(16) /* Enables CCI_SYNC_MODE */
53 #define USART1_PCLK_ENABLE BIT(0) /* Enables USART1_PCLK_ENABLE */
54 #define USART1_SCLK_ENABLE BIT(1) /* Enables USART1_SCLK_ENABLE */
55 #define USART2_PCLK_ENABLE BIT(2) /* Enables USART2_PCLK_ENABLE */
56 #define USART2_SCLK_ENABLE BIT(3) /* Enables USART2_SCLK_ENABLE */
58 #define QSPI_2_CLK_ENABLE BIT(4) /* Enables QSPI_CLK_ENABLE */
59 #define QSPI_2_HCLK_ENABLE BIT(5) /* Enables QSPI_HCLK_ENABLE */
60 #define QSPI_2_M4_SOC_SYNC BIT(6) /* Enables QSPI_M4_SOC_SYNC */
61 #define QSPI_2_CLK_ONEHOT_ENABLE BIT(7) /* Enables QSPI_CLK_ONEHOT_ENABLE */
63 #define CT_CLK_ENABLE BIT(9) /* Enables CT_CLK_ENABLE */
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Drsi_ipmu.h60 #define CMP_NPSS_PG_ENB BIT(16) /*Power gate enable for BOD CORE*/
61 #define ULP_ANG_CLKS_PG_ENB BIT(15) /*Power gate enable for CLKS CORE*/
62 #define ULP_ANG_PWRSUPPLY_PG_ENB BIT(14) /*Power gate enable for BG SPI*/
63 #define WURX_PG_ENB BIT(13) /*Power gate enable for WURX*/
64 #define WURX_CORR_PG_ENB BIT(12) /*Power gate enable for WURX CORRELATION BLOCK*/
65 #define AUXADC_PG_ENB BIT(11) /*Power gate enable for AUXADC*/
66 #define AUXADC_BYPASS_ISO_GEN BIT(10) /*power gate bypass for AUXADC*/
67 #define AUXADC_ISOLATION_ENABLE BIT(9) /*power gate isolation for AUXADC*/
68 #define AUXDAC_PG_ENB BIT(8) /*Power gate enable for AUXDAC*/
69 #define AUXDAC_BYPASS_ISO_GEN BIT(7) /*power gate bypass for AUXDAC*/
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Drsi_ulpss_clk.h54 #define TOUCH_SENSOR_PCLK_ENABLE BIT(31) /* Enables TOUCH_SENSOR_PCLK_ENABLE */
55 #define FIM_AHB_CLK_ENABLE BIT(30) /* Enables FIM_AHB_CLK_ENABLE */
56 #define ULPSS_TASS_QUASI_SYNC BIT(27) /* Enables ULPSS_TASS_QUASI_SYNC */
57 #define ULPSS_M4SS_SLV_SEL BIT(26) /* Enables ULPSS_M4SS_SLV_SEL */
58 #define AUX_SOC_EXT_TRIG_2_SEL BIT(25) /* Enables TOUCH_SENSOR_PCLK_ENABLE */
59 #define AUX_SOC_EXT_TRIG_1_SEL BIT(24) /* Enables AUX_SOC_EXT_TRIG_1_SEL */
60 #define AUX_ULP_EXT_TRIG_2_SEL BIT(23) /* Enables AUX_ULP_EXT_TRIG_2_SEL */
61 #define AUX_ULP_EXT_TRIG_1_SEL BIT(22) /* Enables AUX_ULP_EXT_TRIG_1_SEL */
62 #define TIMER_PCLK_EN BIT(21) /* Enables TIMER_PCLK_EN */
63 #define EGPIO_PCLK_EN BIT(20) /* Enables EGPIO_PCLK_EN */
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Drsi_reg_spi.h64 #define GSPI_RF_N_ULP BIT(12)
65 #define GSPI_ACTIVE BIT(8)
66 #define GSPI_TRIG BIT(7)
67 #define GSPI_READ BIT(6)
69 #define READ_INDICATION BIT(15)
Drsi_retention.h84 #define NPSS_GPIO_0_INTR BIT(0)
85 #define NPSS_GPIO_1_INTR BIT(1)
86 #define NPSS_GPIO_2_INTR BIT(2)
87 #define NPSS_GPIO_3_INTR BIT(3)
88 #define NPSS_GPIO_4_INTR BIT(4)
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/
Dsl_si91x_socket_constants.h35 #ifndef BIT
36 #define BIT(a) ((uint32_t)1U << a) macro
73 #define SI91X_SOCKET_FEAT_SSL BIT(0) // SAPI maps both SSL and synchronous to BIT(0)
74 #define SI91X_SOCKET_FEAT_SYNCHRONOUS BIT(0)
75 #define SI91X_SOCKET_FEAT_LTCP_ACCEPT BIT(1)
76 #define SI91X_WEBSOCKET_FEAT BIT(1)
77 #define SI91X_SOCKET_FEAT_TCP_ACK_INDICATION BIT(2)
78 #define SI91X_SOCKET_FEAT_TCP_RX_WINDOW BIT(4)
79 #define SI91X_SOCKET_FEAT_CERT_INDEX BIT(5)
80 #define SI91X_HIGH_PERFORMANCE_SOCKET BIT(7)
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/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/
Drsi_qspi.h280 #define RD_FIFO_EMPTY BIT(7)
282 #define Q_QSPI_BUSY BIT(0)
284 #define FULL_DUPLEX_EN BIT(22)
285 #define TAKE_LEN_FRM_REG BIT(21)
286 #define HW_CTRL_MODE BIT(25)
287 #define READ_TRIGGER BIT(2)
288 #define WRITE_TRIGGER BIT(1)
289 #define CSN_ACTIVE BIT(0)
292 #define QSPI_LOOP_BACK_MODE_EN BIT(14)
293 #define QSPI_MANUAL_DDR_PHASSE BIT(15)
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Drsi_efuse.h87 #define EFUSE_CLK_BIT BIT(5)
88 #define EFUSE_PCLK_BIT BIT(19)
92 #define SET_LOAD_ENABLE BIT(3)
93 #define SET_CHIP_ENABLE BIT(1)
94 #define SET_PROGRAM_ENABLE BIT(0)
96 #define READ_FSM_DONE BIT(15)
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/
Drsi_m4.h83 #define TA_wakeup_M4 BIT(2)
84 #define TA_is_active BIT(3)
85 #define M4_wakeup_TA BIT(0)
86 #define M4_is_active BIT(1)
92 #define TURN_ON_XTAL_REQUEST BIT(9)
93 #define TURN_OFF_XTAL_REQUEST BIT(10)
94 #define M4_IS_USING_XTAL_REQUEST BIT(11)
100 #ifndef BIT
101 #define BIT(x) (1 << (x)) macro
105 #define RX_BUFFER_VALID BIT(1)
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Drsi_wisemcu_hardware_setup.h47 #define M4SS_REF_CLK_MUX_CTRL BIT(24)
48 #define TASS_REF_CLK_MUX_CTRL BIT(25)
49 #define M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS BIT(2)
90 #define FRONT_END_SWITCH_SEL1 BIT(29)
91 #define FRONT_END_SWITCH_SEL2 BIT(30)
92 #define FRONT_END_SWITCH_SEL3 (BIT(29) | BIT(30))
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_ipmu.c550 ULP_SPI_MEM_MAP(0x141) &= ~BIT(20); in RSI_IPMU_PowerGateClr()
551 ULP_SPI_MEM_MAP(0x141) &= ~BIT(21); in RSI_IPMU_PowerGateClr()
578 ULP_SPI_MEM_MAP(SELECT_BG_CLK) &= ~(BIT(0) | BIT(1)); in RSI_IPMU_ClockMuxSel()
581 ULP_SPI_MEM_MAP(SELECT_BG_CLK) |= BIT(bg_pmu_clk); in RSI_IPMU_ClockMuxSel()
601 *(volatile uint32_t *)0x41300120 |= BIT(22); in RSI_IPMU_32MHzClkClib()
623 } while ((!(ULP_SPI_MEM_MAP(0x30C))) & BIT(20)); in RSI_IPMU_32MHzClkClib()
684 reg_read_data &= ~BIT(cnt); in RSI_IPMU_ProgramConfigData()
685 write_mask |= BIT(write_bit_pos); in RSI_IPMU_ProgramConfigData()
745 write_mask |= BIT(write_bit_pos); in RSI_APB_ProgramConfigData()
1376 ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) |= BIT(21); in RSI_IPMU_32KHzROClkClib()
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/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/
Dipmu_apis.c466 mask |= BIT(mask_bits); in program_ipmu_data()
493 PMU_DIRECT_ACCESS(0x125) |= (BIT(2)); //! Added by Nagaraj in shut_down_non_wireless_mode_pds()
494 PMU_DIRECT_ACCESS(0x127) &= ~((BIT(3)) | BIT(4)); //! Added by Nagaraj in shut_down_non_wireless_mode_pds()
618 PMU_DIRECT_ACCESS(0x129) |= (BIT(15) | BIT(16)); //! Added by Nagaraj in ipmu_init()
619 PMU_DIRECT_ACCESS(0x140) |= (BIT(15) | BIT(18) | BIT(19)); //! Added by Nagaraj in ipmu_init()
633 …PMU_DIRECT_ACCESS(SELECT_BG_CLK_OFFSET) |= BIT(1); //! BG-PMU Clock configured to MCU_FSM_SLEEP_CLK in ipmu_init()
670 PMU_DIRECT_ACCESS(BG_SLEEP_TIMER_REG_OFFSET) |= BIT(19); //bgs_active_timer_sel in ipmu_init()
687 ULP_DIRECT_ACCESS(NWPAON_POR_CTRL_BITS) |= (poc_cntrl_reg_0 | BIT(16)); in ipmu_init()
708 PMU_DIRECT_ACCESS(iPMU_SPARE_REG1_OFFSET) |= BIT(13); in configure_uulp_gpio_to_1p8v()
750 while ((*(volatile uint32_t *)(0x24043830)) & BIT(2)) in adc_read_data_func()
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/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/
Dsystem_si91x.h65 #define LF_32_KHZ_RC BIT(0)
66 #define LF_32_KHZ_XTAL BIT(1)
67 #define EXTERNAL_CAP_MODE BIT(2)
89 #define SELECT_RC_MHZ_CLOCK BIT(15)
90 #define SELECT_XTAL_MHZ_CLOCK ~(BIT(14) | BIT(15))
102 #define M4SS_REF_CLK_MUX_CTRL BIT(24)
103 #define TASS_REF_CLK_MUX_CTRL BIT(25)
105 #define MCU_TASS_REF_CLK_SEL_MUX_CTRL BIT(8)
107 #define M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS_BIT BIT(2)
108 #define M4_USING_FLASH BIT(3)
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Dbase_types.h68 #ifndef BIT
69 #define BIT(x) ((uint32_t)1U << (x)) macro
113 #define SET_BIT(n) BIT(n) //((uint32_t)1 << n)
114 #define CLR_BIT(n) ~BIT(n) //(~((uint32_t)1 << n))
/hal_silabs-latest/wiseconnect/components/protocol/wifi/inc/
Dsl_wifi_types.h47 #define MAC_INFO_ENABLE BIT(0)
48 #define BCAST_INDICATION BIT(1)
49 #define CONFIRM_REQUIRED_TO_HOST BIT(2)
50 #define QOS_ENABLE BIT(4)
60 #define FC_TYPE_DATA BIT(3)
61 #define FC_SUBTYPE_QOS_DATA BIT(7)
62 #define FC_TO_DS BIT(8)
63 #define FC_FROM_DS BIT(9)
64 #define TX_DATA_CTRL_FLAG_QOS_BIT BIT(1)
67 #define IS_4ADDR(ctrl_flags) (ctrl_flags & BIT(0))
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/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/
Drsi_bt_common_config.h105 #define RSI_SPP_PROFILE_BIT BIT(0) ///< bitmask to enable the SPP profile in Bluetooth Classic (BIT…
109 #define RSI_A2DP_PROFILE_BIT BIT(1) ///< bitmask to enable the A2DP profile in Bluetooth Classic (B…
113 #define RSI_AVRCP_PROFILE_BIT BIT(2) ///< bitmask to enable the AVRCP profile in Bluetooth Classic …
117 #define RSI_HFP_PROFILE_BIT BIT(3) ///< bitmask to enable the HFP profile in Bluetooth Classic (BIT…
122 …BIT(4) #define RSI_PBAP_PROFILE_BIT BIT(4) ///< bitmask to enable the PBAP profile in Bluetooth Cl…
Drsi_ble_common_config.h73 #define ATT_REC_MAINTAIN_IN_HOST BIT(0) ///< Att record maintained by the stack
74 #define SEC_MODE_1_LEVEL_1 BIT(1) ///< NO Auth & No Enc
75 #define SEC_MODE_1_LEVEL_2 BIT(2) ///< UnAUTH with Enc
76 #define SEC_MODE_1_LEVEL_3 BIT(3) ///< AUTH with Enc
77 #define SEC_MODE_1_LEVEL_4 BIT(4) ///< AUTH LE_SC Pairing with Enc
78 #define ON_BR_EDR_LINK_ONLY BIT(5) ///< BR/EDR link-only mode
79 #define ON_LE_LINK_ONLY BIT(6) ///< LE link-only mode
Drsi_bt_common.h53 #define BLE_PROTO_ENABLE BIT(2)
55 #define BT_CLASSIC_PROTO_ENABLE BIT(3)
57 #define PROP_PROTO_ENABLE (BIT(8))
61 #define RSI_BT_BLE_MODE_BITS (BIT(2) | BIT(3))
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/
Dsystem_si91x.c142 *(volatile uint32 *)(NPSS_GPIO_CTRL + (4 * OSC_UULP_GPIO)) = (BIT(3) | UULP_GPIO_OSC_MODE); in SystemCoreClockUpdate()
143 MCUAON_GEN_CTRLS_REG |= BIT(0); in SystemCoreClockUpdate()
166 ULP_SPI_MEM_MAP(BG_LDO_REG1) |= BIT(LDO_0P6_BYPASS_BIT); //bypassing the retention LDO in SystemCoreClockUpdate()
271 *(volatile uint32_t *)0x41300004 = BIT(24); in SystemInit()
274 *(volatile uint32_t *)0x24048140 = (BIT(19) | BIT(1) | BIT(0)); in SystemInit()
283 PMU_DIRECT_ACCESS(BG_SLEEP_TIMER_REG_OFFSET) |= BIT(19); //bgs_active_timer_sel in SystemInit()
Drsi_deepsleep_soc.c377 disable_pads_ctrl = (ULP_SPI_MEM_MAP(0x141) & BIT(11)); // ULP PADS PDO Status in RSI_PS_EnterDeepSleep()
378 ULP_SPI_MEM_MAP(0x141) &= ~(BIT(11)); // ULP PADS PDO OFF in RSI_PS_EnterDeepSleep()
409 && (lf_clk_mode & BIT(4)) in RSI_PS_EnterDeepSleep()
604 if (lf_clk_mode & BIT(4)) { in RSI_PS_EnterDeepSleep()
650 *(volatile uint32_t *)(0x24041400 + 0x3C) |= BIT(0); in RSI_PS_EnterDeepSleep()
662 ULP_SPI_MEM_MAP(0x141) |= (BIT(11)); // ULP PADS PDO ON in RSI_PS_EnterDeepSleep()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/wireless/src/
Dsl_rsi_utility.c1786 header_length += (packet[0] & BIT(7)) ? 2 : 0; /* 2 bytes QoS control */ in print_80211_packet()
1787 header_length += ((packet[1] & BIT(0)) && (packet[1] & BIT(1))) ? 6 : 0; /* 6 byte Addr4 */ in print_80211_packet()
1813 if ((packet[1] & BIT(0)) && (packet[1] & BIT(1))) { /* Addr4 */ in print_80211_packet()
1822 if (packet[0] & BIT(7)) { in print_80211_packet()
1862 din[0] = ((crc8_din & BIT(7)) >> 7); in sli_lmac_crc8_c()
1863 din[1] = ((crc8_din & BIT(6)) >> 6); in sli_lmac_crc8_c()
1864 din[2] = ((crc8_din & BIT(5)) >> 5); in sli_lmac_crc8_c()
1865 din[3] = ((crc8_din & BIT(4)) >> 4); in sli_lmac_crc8_c()
1866 din[4] = ((crc8_din & BIT(3)) >> 3); in sli_lmac_crc8_c()
1867 din[5] = ((crc8_din & BIT(2)) >> 2); in sli_lmac_crc8_c()
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/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/
Dsl_si91x_gpio.h237 UULP_GPIO_INTERRUPT_0_BIT = BIT(0), /// UULP GPIO 0 interrupt bit position
238 UULP_GPIO_INTERRUPT_1_BIT = BIT(1), /// UULP GPIO 1 interrupt bit position
239 UULP_GPIO_INTERRUPT_2_BIT = BIT(2), /// UULP GPIO 2 interrupt bit position
240 UULP_GPIO_INTERRUPT_3_BIT = BIT(3), /// UULP GPIO 3 interrupt bit position
241 UULP_GPIO_INTERRUPT_4_BIT = BIT(4), /// UULP GPIO 4 interrupt bit position

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