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Searched refs:_SMU_PPUPATD0_I2C1_DEFAULT (Results 1 – 25 of 73) sorted by relevance

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/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_smu.h197 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
198 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_smu.h197 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
198 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_smu.h197 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
198 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_smu.h197 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
198 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_smu.h197 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
198 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_smu.h218 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
219 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b390f1024gl112.h7663 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
7664 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b390f512gl112.h7663 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
7664 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b110f1024gq64.h8440 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8441 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b110f1024gm64.h8440 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8441 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b110f1024iq64.h8440 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8441 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b530f512iq64.h8471 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8472 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b530f512il112.h8471 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8472 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b530f512il120.h8471 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8472 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b530f512im64.h8471 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8472 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b110f1024im64.h8440 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8441 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b530f512iq100.h8471 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8472 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b530f512gq100.h8471 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8472 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b530f512gq64.h8471 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8472 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
Defm32gg12b310f1024gl112.h8469 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8470 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_smu.h228 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
229 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21_smu.h417 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< M… macro
418 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 24) /**< S…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22_smu.h417 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< M… macro
418 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 24) /**< S…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27_smu.h417 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< M… macro
418 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 24) /**< S…
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32MG24/Include/
Defr32mg24_smu.h407 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mo… macro
408 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 22) /**< Sh…

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