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Searched refs:RDMEM_SEQ_BANK1_SIZE (Results 1 – 25 of 69) sorted by relevance

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/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f768im32.h1157 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32mg21a020f1024im32.h1159 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32mg21a020f512im32.h1159 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32mg21a020f768im32.h1159 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32mg21b020f768im32.h1159 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ macro
Drm21z000f1024im32.h1155 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32mg21a010f1024im32.h1157 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32mg21a010f512im32.h1157 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32mg21b010f512im32.h1157 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32mg21b010f768im32.h1157 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32mg21b010f1024im32.h1157 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32mg21b020f1024im32.h1159 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32mg21b020f512im32.h1159 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ macro
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c222f352gm32.h1163 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32bg22c222f352gm40.h1177 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32bg22c224f512gm32.h1163 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32bg22c224f512gm40.h1177 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32bg22c224f512gn32.h1163 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32bg22c224f512im32.h1163 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32bg22c224f512im40.h1177 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32bg22c112f352gm32.h1161 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32bg22c112f352gm40.h1175 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32bg22c222f352gn32.h1163 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ macro
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27c230f768im32.h1229 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ macro
Defr32bg27c230f768im40.h1249 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ macro

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