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Searched refs:CLKEN0_CLR (Results 1 – 9 of 9) sorted by relevance

/hal_silabs-3.7.0/gecko/emlib/src/
Dem_se.c327 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_executeCommand()
397 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in rootIsOutputMailboxValid()
446 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_getVersion()
505 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_getConfigStatusBits()
544 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_getOTPVersion()
582 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_isCommandCompleted()
611 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_readExecutedCommand()
648 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_readCommandResponse()
696 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_ackCommand()
Dem_emu.c3353 CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; in EMU_EM01BoostPeakCurrentSet()
3591 CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; in EMU_EM01PeakCurrentSet()
3636 CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; in EMU_DCDCSetPFMXModePeakCurrent()
3675 CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; in EMU_DCDCSetPFMXTimeoutMaxCtrl()
Dem_msc.c2005 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in MSC_DmemPortMapSet()
Dem_cmu.c1494 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in sli_em_cmu_SYSTICEXTCLKENSet()
1518 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in sli_em_cmu_SYSTICEXTCLKENClear()
1742 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in CMU_ClockSelectSet()
1755 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in CMU_ClockSelectSet()
/hal_silabs-3.7.0/gecko/util/se_manager/src/
Dem_se.c312 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_executeCommand()
381 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in rootIsOutputMailboxValid()
430 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_getVersion()
489 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_getConfigStatusBits()
522 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_isCommandCompleted()
551 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_readExecutedCommand()
588 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_readCommandResponse()
636 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in SE_ackCommand()
/hal_silabs-3.7.0/gecko/emlib/inc/
Dem_chip.h354 CMU->CLKEN0_CLR = CMU_CLKEN0_HFRCO0; in CHIP_Init()
385 CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; in CHIP_Init()
389 CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; in CHIP_Init()
410 CMU->CLKEN0_CLR = CMU_CLKEN0_HFXO0; in CHIP_Init()
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27_cmu.h150 …__IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 … member
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22_cmu.h152 …__IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 … member
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32MG24/Include/
Defr32mg24_cmu.h164 …__IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 … member