1 /***************************************************************************//** 2 * @file 3 * @brief EFM32WG_ADC register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32WG_ADC 43 * @{ 44 * @brief EFM32WG_ADC Register Declaration 45 ******************************************************************************/ 46 typedef struct { 47 __IOM uint32_t CTRL; /**< Control Register */ 48 __IOM uint32_t CMD; /**< Command Register */ 49 __IM uint32_t STATUS; /**< Status Register */ 50 __IOM uint32_t SINGLECTRL; /**< Single Sample Control Register */ 51 __IOM uint32_t SCANCTRL; /**< Scan Control Register */ 52 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 53 __IM uint32_t IF; /**< Interrupt Flag Register */ 54 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 55 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 56 __IM uint32_t SINGLEDATA; /**< Single Conversion Result Data */ 57 __IM uint32_t SCANDATA; /**< Scan Conversion Result Data */ 58 __IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */ 59 __IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */ 60 __IOM uint32_t CAL; /**< Calibration Register */ 61 62 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 63 __IOM uint32_t BIASPROG; /**< Bias Programming Register */ 64 } ADC_TypeDef; /**< ADC Register Declaration *//** @} */ 65 66 /***************************************************************************//** 67 * @defgroup EFM32WG_ADC_BitFields 68 * @{ 69 ******************************************************************************/ 70 71 /* Bit fields for ADC CTRL */ 72 #define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */ 73 #define _ADC_CTRL_MASK 0x0F7F7F3BUL /**< Mask for ADC_CTRL */ 74 #define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */ 75 #define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */ 76 #define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ 77 #define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */ 78 #define _ADC_CTRL_WARMUPMODE_FASTBG 0x00000001UL /**< Mode FASTBG for ADC_CTRL */ 79 #define _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM 0x00000002UL /**< Mode KEEPSCANREFWARM for ADC_CTRL */ 80 #define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */ 81 #define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */ 82 #define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */ 83 #define ADC_CTRL_WARMUPMODE_FASTBG (_ADC_CTRL_WARMUPMODE_FASTBG << 0) /**< Shifted mode FASTBG for ADC_CTRL */ 84 #define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM (_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM << 0) /**< Shifted mode KEEPSCANREFWARM for ADC_CTRL */ 85 #define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */ 86 #define ADC_CTRL_TAILGATE (0x1UL << 3) /**< Conversion Tailgating */ 87 #define _ADC_CTRL_TAILGATE_SHIFT 3 /**< Shift value for ADC_TAILGATE */ 88 #define _ADC_CTRL_TAILGATE_MASK 0x8UL /**< Bit mask for ADC_TAILGATE */ 89 #define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ 90 #define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */ 91 #define _ADC_CTRL_LPFMODE_SHIFT 4 /**< Shift value for ADC_LPFMODE */ 92 #define _ADC_CTRL_LPFMODE_MASK 0x30UL /**< Bit mask for ADC_LPFMODE */ 93 #define _ADC_CTRL_LPFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ 94 #define _ADC_CTRL_LPFMODE_BYPASS 0x00000000UL /**< Mode BYPASS for ADC_CTRL */ 95 #define _ADC_CTRL_LPFMODE_DECAP 0x00000001UL /**< Mode DECAP for ADC_CTRL */ 96 #define _ADC_CTRL_LPFMODE_RCFILT 0x00000002UL /**< Mode RCFILT for ADC_CTRL */ 97 #define ADC_CTRL_LPFMODE_DEFAULT (_ADC_CTRL_LPFMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */ 98 #define ADC_CTRL_LPFMODE_BYPASS (_ADC_CTRL_LPFMODE_BYPASS << 4) /**< Shifted mode BYPASS for ADC_CTRL */ 99 #define ADC_CTRL_LPFMODE_DECAP (_ADC_CTRL_LPFMODE_DECAP << 4) /**< Shifted mode DECAP for ADC_CTRL */ 100 #define ADC_CTRL_LPFMODE_RCFILT (_ADC_CTRL_LPFMODE_RCFILT << 4) /**< Shifted mode RCFILT for ADC_CTRL */ 101 #define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */ 102 #define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */ 103 #define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ 104 #define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */ 105 #define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */ 106 #define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */ 107 #define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */ 108 #define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */ 109 #define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */ 110 #define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */ 111 #define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */ 112 #define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */ 113 #define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ 114 #define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */ 115 #define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */ 116 #define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */ 117 #define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */ 118 #define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */ 119 #define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */ 120 #define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */ 121 #define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */ 122 #define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */ 123 #define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */ 124 #define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */ 125 #define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */ 126 #define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */ 127 #define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */ 128 #define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */ 129 #define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */ 130 #define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */ 131 #define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */ 132 #define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */ 133 #define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */ 134 #define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */ 135 #define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */ 136 #define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */ 137 #define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */ 138 #define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */ 139 140 /* Bit fields for ADC CMD */ 141 #define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */ 142 #define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */ 143 #define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Conversion Start */ 144 #define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */ 145 #define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */ 146 #define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ 147 #define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */ 148 #define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Conversion Stop */ 149 #define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */ 150 #define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */ 151 #define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ 152 #define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */ 153 #define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */ 154 #define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */ 155 #define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */ 156 #define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ 157 #define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */ 158 #define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */ 159 #define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */ 160 #define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */ 161 #define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ 162 #define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */ 163 164 /* Bit fields for ADC STATUS */ 165 #define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */ 166 #define _ADC_STATUS_MASK 0x07031303UL /**< Mask for ADC_STATUS */ 167 #define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Conversion Active */ 168 #define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */ 169 #define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */ 170 #define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ 171 #define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */ 172 #define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */ 173 #define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */ 174 #define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */ 175 #define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ 176 #define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */ 177 #define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Reference Warmed Up */ 178 #define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */ 179 #define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */ 180 #define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ 181 #define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */ 182 #define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */ 183 #define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */ 184 #define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */ 185 #define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ 186 #define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */ 187 #define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */ 188 #define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */ 189 #define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */ 190 #define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ 191 #define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */ 192 #define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Sample Data Valid */ 193 #define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */ 194 #define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */ 195 #define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ 196 #define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */ 197 #define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */ 198 #define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */ 199 #define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */ 200 #define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ 201 #define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */ 202 #define _ADC_STATUS_SCANDATASRC_SHIFT 24 /**< Shift value for ADC_SCANDATASRC */ 203 #define _ADC_STATUS_SCANDATASRC_MASK 0x7000000UL /**< Bit mask for ADC_SCANDATASRC */ 204 #define _ADC_STATUS_SCANDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ 205 #define _ADC_STATUS_SCANDATASRC_CH0 0x00000000UL /**< Mode CH0 for ADC_STATUS */ 206 #define _ADC_STATUS_SCANDATASRC_CH1 0x00000001UL /**< Mode CH1 for ADC_STATUS */ 207 #define _ADC_STATUS_SCANDATASRC_CH2 0x00000002UL /**< Mode CH2 for ADC_STATUS */ 208 #define _ADC_STATUS_SCANDATASRC_CH3 0x00000003UL /**< Mode CH3 for ADC_STATUS */ 209 #define _ADC_STATUS_SCANDATASRC_CH4 0x00000004UL /**< Mode CH4 for ADC_STATUS */ 210 #define _ADC_STATUS_SCANDATASRC_CH5 0x00000005UL /**< Mode CH5 for ADC_STATUS */ 211 #define _ADC_STATUS_SCANDATASRC_CH6 0x00000006UL /**< Mode CH6 for ADC_STATUS */ 212 #define _ADC_STATUS_SCANDATASRC_CH7 0x00000007UL /**< Mode CH7 for ADC_STATUS */ 213 #define ADC_STATUS_SCANDATASRC_DEFAULT (_ADC_STATUS_SCANDATASRC_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_STATUS */ 214 #define ADC_STATUS_SCANDATASRC_CH0 (_ADC_STATUS_SCANDATASRC_CH0 << 24) /**< Shifted mode CH0 for ADC_STATUS */ 215 #define ADC_STATUS_SCANDATASRC_CH1 (_ADC_STATUS_SCANDATASRC_CH1 << 24) /**< Shifted mode CH1 for ADC_STATUS */ 216 #define ADC_STATUS_SCANDATASRC_CH2 (_ADC_STATUS_SCANDATASRC_CH2 << 24) /**< Shifted mode CH2 for ADC_STATUS */ 217 #define ADC_STATUS_SCANDATASRC_CH3 (_ADC_STATUS_SCANDATASRC_CH3 << 24) /**< Shifted mode CH3 for ADC_STATUS */ 218 #define ADC_STATUS_SCANDATASRC_CH4 (_ADC_STATUS_SCANDATASRC_CH4 << 24) /**< Shifted mode CH4 for ADC_STATUS */ 219 #define ADC_STATUS_SCANDATASRC_CH5 (_ADC_STATUS_SCANDATASRC_CH5 << 24) /**< Shifted mode CH5 for ADC_STATUS */ 220 #define ADC_STATUS_SCANDATASRC_CH6 (_ADC_STATUS_SCANDATASRC_CH6 << 24) /**< Shifted mode CH6 for ADC_STATUS */ 221 #define ADC_STATUS_SCANDATASRC_CH7 (_ADC_STATUS_SCANDATASRC_CH7 << 24) /**< Shifted mode CH7 for ADC_STATUS */ 222 223 /* Bit fields for ADC SINGLECTRL */ 224 #define _ADC_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRL */ 225 #define _ADC_SINGLECTRL_MASK 0xF1F70F37UL /**< Mask for ADC_SINGLECTRL */ 226 #define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Sample Repetitive Mode */ 227 #define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ 228 #define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ 229 #define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ 230 #define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ 231 #define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Sample Differential Mode */ 232 #define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ 233 #define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ 234 #define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ 235 #define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ 236 #define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Sample Result Adjustment */ 237 #define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ 238 #define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ 239 #define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ 240 #define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */ 241 #define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */ 242 #define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ 243 #define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */ 244 #define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */ 245 #define _ADC_SINGLECTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */ 246 #define _ADC_SINGLECTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */ 247 #define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ 248 #define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */ 249 #define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */ 250 #define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */ 251 #define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */ 252 #define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ 253 #define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SINGLECTRL */ 254 #define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SINGLECTRL */ 255 #define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SINGLECTRL */ 256 #define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SINGLECTRL */ 257 #define _ADC_SINGLECTRL_INPUTSEL_SHIFT 8 /**< Shift value for ADC_INPUTSEL */ 258 #define _ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL /**< Bit mask for ADC_INPUTSEL */ 259 #define _ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ 260 #define _ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL /**< Mode CH0CH1 for ADC_SINGLECTRL */ 261 #define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /**< Mode CH0 for ADC_SINGLECTRL */ 262 #define _ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL /**< Mode CH2CH3 for ADC_SINGLECTRL */ 263 #define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /**< Mode CH1 for ADC_SINGLECTRL */ 264 #define _ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL /**< Mode CH4CH5 for ADC_SINGLECTRL */ 265 #define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /**< Mode CH2 for ADC_SINGLECTRL */ 266 #define _ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL /**< Mode CH6CH7 for ADC_SINGLECTRL */ 267 #define _ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL /**< Mode CH3 for ADC_SINGLECTRL */ 268 #define _ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL /**< Mode DIFF0 for ADC_SINGLECTRL */ 269 #define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /**< Mode CH4 for ADC_SINGLECTRL */ 270 #define _ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL /**< Mode CH5 for ADC_SINGLECTRL */ 271 #define _ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL /**< Mode CH6 for ADC_SINGLECTRL */ 272 #define _ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL /**< Mode CH7 for ADC_SINGLECTRL */ 273 #define _ADC_SINGLECTRL_INPUTSEL_TEMP 0x00000008UL /**< Mode TEMP for ADC_SINGLECTRL */ 274 #define _ADC_SINGLECTRL_INPUTSEL_VDDDIV3 0x00000009UL /**< Mode VDDDIV3 for ADC_SINGLECTRL */ 275 #define _ADC_SINGLECTRL_INPUTSEL_VDD 0x0000000AUL /**< Mode VDD for ADC_SINGLECTRL */ 276 #define _ADC_SINGLECTRL_INPUTSEL_VSS 0x0000000BUL /**< Mode VSS for ADC_SINGLECTRL */ 277 #define _ADC_SINGLECTRL_INPUTSEL_VREFDIV2 0x0000000CUL /**< Mode VREFDIV2 for ADC_SINGLECTRL */ 278 #define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */ 279 #define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */ 280 #define ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ 281 #define ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SINGLECTRL */ 282 #define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /**< Shifted mode CH0 for ADC_SINGLECTRL */ 283 #define ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SINGLECTRL */ 284 #define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /**< Shifted mode CH1 for ADC_SINGLECTRL */ 285 #define ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SINGLECTRL */ 286 #define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /**< Shifted mode CH2 for ADC_SINGLECTRL */ 287 #define ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SINGLECTRL */ 288 #define ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8) /**< Shifted mode CH3 for ADC_SINGLECTRL */ 289 #define ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8) /**< Shifted mode DIFF0 for ADC_SINGLECTRL */ 290 #define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /**< Shifted mode CH4 for ADC_SINGLECTRL */ 291 #define ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8) /**< Shifted mode CH5 for ADC_SINGLECTRL */ 292 #define ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8) /**< Shifted mode CH6 for ADC_SINGLECTRL */ 293 #define ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8) /**< Shifted mode CH7 for ADC_SINGLECTRL */ 294 #define ADC_SINGLECTRL_INPUTSEL_TEMP (_ADC_SINGLECTRL_INPUTSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */ 295 #define ADC_SINGLECTRL_INPUTSEL_VDDDIV3 (_ADC_SINGLECTRL_INPUTSEL_VDDDIV3 << 8) /**< Shifted mode VDDDIV3 for ADC_SINGLECTRL */ 296 #define ADC_SINGLECTRL_INPUTSEL_VDD (_ADC_SINGLECTRL_INPUTSEL_VDD << 8) /**< Shifted mode VDD for ADC_SINGLECTRL */ 297 #define ADC_SINGLECTRL_INPUTSEL_VSS (_ADC_SINGLECTRL_INPUTSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */ 298 #define ADC_SINGLECTRL_INPUTSEL_VREFDIV2 (_ADC_SINGLECTRL_INPUTSEL_VREFDIV2 << 8) /**< Shifted mode VREFDIV2 for ADC_SINGLECTRL */ 299 #define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */ 300 #define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */ 301 #define _ADC_SINGLECTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */ 302 #define _ADC_SINGLECTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */ 303 #define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ 304 #define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */ 305 #define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */ 306 #define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */ 307 #define _ADC_SINGLECTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SINGLECTRL */ 308 #define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */ 309 #define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */ 310 #define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */ 311 #define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ 312 #define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SINGLECTRL */ 313 #define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SINGLECTRL */ 314 #define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SINGLECTRL */ 315 #define ADC_SINGLECTRL_REF_5VDIFF (_ADC_SINGLECTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SINGLECTRL */ 316 #define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */ 317 #define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */ 318 #define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */ 319 #define _ADC_SINGLECTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */ 320 #define _ADC_SINGLECTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */ 321 #define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ 322 #define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */ 323 #define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */ 324 #define _ADC_SINGLECTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SINGLECTRL */ 325 #define _ADC_SINGLECTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SINGLECTRL */ 326 #define _ADC_SINGLECTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SINGLECTRL */ 327 #define _ADC_SINGLECTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SINGLECTRL */ 328 #define _ADC_SINGLECTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SINGLECTRL */ 329 #define _ADC_SINGLECTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SINGLECTRL */ 330 #define _ADC_SINGLECTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SINGLECTRL */ 331 #define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ 332 #define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */ 333 #define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */ 334 #define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */ 335 #define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */ 336 #define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */ 337 #define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */ 338 #define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */ 339 #define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */ 340 #define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */ 341 #define ADC_SINGLECTRL_PRSEN (0x1UL << 24) /**< Single Sample PRS Trigger Enable */ 342 #define _ADC_SINGLECTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */ 343 #define _ADC_SINGLECTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */ 344 #define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ 345 #define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ 346 #define _ADC_SINGLECTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */ 347 #define _ADC_SINGLECTRL_PRSSEL_MASK 0xF0000000UL /**< Bit mask for ADC_PRSSEL */ 348 #define _ADC_SINGLECTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ 349 #define _ADC_SINGLECTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRL */ 350 #define _ADC_SINGLECTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRL */ 351 #define _ADC_SINGLECTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRL */ 352 #define _ADC_SINGLECTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRL */ 353 #define _ADC_SINGLECTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRL */ 354 #define _ADC_SINGLECTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRL */ 355 #define _ADC_SINGLECTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRL */ 356 #define _ADC_SINGLECTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRL */ 357 #define _ADC_SINGLECTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRL */ 358 #define _ADC_SINGLECTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRL */ 359 #define _ADC_SINGLECTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRL */ 360 #define _ADC_SINGLECTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRL */ 361 #define ADC_SINGLECTRL_PRSSEL_DEFAULT (_ADC_SINGLECTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ 362 #define ADC_SINGLECTRL_PRSSEL_PRSCH0 (_ADC_SINGLECTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SINGLECTRL */ 363 #define ADC_SINGLECTRL_PRSSEL_PRSCH1 (_ADC_SINGLECTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SINGLECTRL */ 364 #define ADC_SINGLECTRL_PRSSEL_PRSCH2 (_ADC_SINGLECTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SINGLECTRL */ 365 #define ADC_SINGLECTRL_PRSSEL_PRSCH3 (_ADC_SINGLECTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SINGLECTRL */ 366 #define ADC_SINGLECTRL_PRSSEL_PRSCH4 (_ADC_SINGLECTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SINGLECTRL */ 367 #define ADC_SINGLECTRL_PRSSEL_PRSCH5 (_ADC_SINGLECTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SINGLECTRL */ 368 #define ADC_SINGLECTRL_PRSSEL_PRSCH6 (_ADC_SINGLECTRL_PRSSEL_PRSCH6 << 28) /**< Shifted mode PRSCH6 for ADC_SINGLECTRL */ 369 #define ADC_SINGLECTRL_PRSSEL_PRSCH7 (_ADC_SINGLECTRL_PRSSEL_PRSCH7 << 28) /**< Shifted mode PRSCH7 for ADC_SINGLECTRL */ 370 #define ADC_SINGLECTRL_PRSSEL_PRSCH8 (_ADC_SINGLECTRL_PRSSEL_PRSCH8 << 28) /**< Shifted mode PRSCH8 for ADC_SINGLECTRL */ 371 #define ADC_SINGLECTRL_PRSSEL_PRSCH9 (_ADC_SINGLECTRL_PRSSEL_PRSCH9 << 28) /**< Shifted mode PRSCH9 for ADC_SINGLECTRL */ 372 #define ADC_SINGLECTRL_PRSSEL_PRSCH10 (_ADC_SINGLECTRL_PRSSEL_PRSCH10 << 28) /**< Shifted mode PRSCH10 for ADC_SINGLECTRL */ 373 #define ADC_SINGLECTRL_PRSSEL_PRSCH11 (_ADC_SINGLECTRL_PRSSEL_PRSCH11 << 28) /**< Shifted mode PRSCH11 for ADC_SINGLECTRL */ 374 375 /* Bit fields for ADC SCANCTRL */ 376 #define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */ 377 #define _ADC_SCANCTRL_MASK 0xF1F7FF37UL /**< Mask for ADC_SCANCTRL */ 378 #define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */ 379 #define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ 380 #define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ 381 #define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ 382 #define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ 383 #define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */ 384 #define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ 385 #define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ 386 #define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ 387 #define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ 388 #define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */ 389 #define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ 390 #define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ 391 #define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ 392 #define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */ 393 #define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */ 394 #define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ 395 #define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */ 396 #define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */ 397 #define _ADC_SCANCTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */ 398 #define _ADC_SCANCTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */ 399 #define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ 400 #define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */ 401 #define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */ 402 #define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */ 403 #define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */ 404 #define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ 405 #define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SCANCTRL */ 406 #define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SCANCTRL */ 407 #define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SCANCTRL */ 408 #define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SCANCTRL */ 409 #define _ADC_SCANCTRL_INPUTMASK_SHIFT 8 /**< Shift value for ADC_INPUTMASK */ 410 #define _ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL /**< Bit mask for ADC_INPUTMASK */ 411 #define _ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ 412 #define _ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL /**< Mode CH0CH1 for ADC_SCANCTRL */ 413 #define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /**< Mode CH0 for ADC_SCANCTRL */ 414 #define _ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL /**< Mode CH2CH3 for ADC_SCANCTRL */ 415 #define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /**< Mode CH1 for ADC_SCANCTRL */ 416 #define _ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL /**< Mode CH4CH5 for ADC_SCANCTRL */ 417 #define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /**< Mode CH2 for ADC_SCANCTRL */ 418 #define _ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL /**< Mode CH6CH7 for ADC_SCANCTRL */ 419 #define _ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL /**< Mode CH3 for ADC_SCANCTRL */ 420 #define _ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL /**< Mode CH4 for ADC_SCANCTRL */ 421 #define _ADC_SCANCTRL_INPUTMASK_CH5 0x00000020UL /**< Mode CH5 for ADC_SCANCTRL */ 422 #define _ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL /**< Mode CH6 for ADC_SCANCTRL */ 423 #define _ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL /**< Mode CH7 for ADC_SCANCTRL */ 424 #define ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ 425 #define ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SCANCTRL */ 426 #define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /**< Shifted mode CH0 for ADC_SCANCTRL */ 427 #define ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SCANCTRL */ 428 #define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /**< Shifted mode CH1 for ADC_SCANCTRL */ 429 #define ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SCANCTRL */ 430 #define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /**< Shifted mode CH2 for ADC_SCANCTRL */ 431 #define ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SCANCTRL */ 432 #define ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8) /**< Shifted mode CH3 for ADC_SCANCTRL */ 433 #define ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8) /**< Shifted mode CH4 for ADC_SCANCTRL */ 434 #define ADC_SCANCTRL_INPUTMASK_CH5 (_ADC_SCANCTRL_INPUTMASK_CH5 << 8) /**< Shifted mode CH5 for ADC_SCANCTRL */ 435 #define ADC_SCANCTRL_INPUTMASK_CH6 (_ADC_SCANCTRL_INPUTMASK_CH6 << 8) /**< Shifted mode CH6 for ADC_SCANCTRL */ 436 #define ADC_SCANCTRL_INPUTMASK_CH7 (_ADC_SCANCTRL_INPUTMASK_CH7 << 8) /**< Shifted mode CH7 for ADC_SCANCTRL */ 437 #define _ADC_SCANCTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */ 438 #define _ADC_SCANCTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */ 439 #define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ 440 #define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */ 441 #define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */ 442 #define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */ 443 #define _ADC_SCANCTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SCANCTRL */ 444 #define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */ 445 #define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */ 446 #define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */ 447 #define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ 448 #define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SCANCTRL */ 449 #define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SCANCTRL */ 450 #define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SCANCTRL */ 451 #define ADC_SCANCTRL_REF_5VDIFF (_ADC_SCANCTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SCANCTRL */ 452 #define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */ 453 #define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */ 454 #define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SCANCTRL */ 455 #define _ADC_SCANCTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */ 456 #define _ADC_SCANCTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */ 457 #define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ 458 #define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */ 459 #define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */ 460 #define _ADC_SCANCTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SCANCTRL */ 461 #define _ADC_SCANCTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SCANCTRL */ 462 #define _ADC_SCANCTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SCANCTRL */ 463 #define _ADC_SCANCTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SCANCTRL */ 464 #define _ADC_SCANCTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SCANCTRL */ 465 #define _ADC_SCANCTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SCANCTRL */ 466 #define _ADC_SCANCTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SCANCTRL */ 467 #define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ 468 #define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */ 469 #define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */ 470 #define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */ 471 #define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */ 472 #define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */ 473 #define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */ 474 #define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */ 475 #define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */ 476 #define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */ 477 #define ADC_SCANCTRL_PRSEN (0x1UL << 24) /**< Scan Sequence PRS Trigger Enable */ 478 #define _ADC_SCANCTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */ 479 #define _ADC_SCANCTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */ 480 #define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ 481 #define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ 482 #define _ADC_SCANCTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */ 483 #define _ADC_SCANCTRL_PRSSEL_MASK 0xF0000000UL /**< Bit mask for ADC_PRSSEL */ 484 #define _ADC_SCANCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ 485 #define _ADC_SCANCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRL */ 486 #define _ADC_SCANCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRL */ 487 #define _ADC_SCANCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRL */ 488 #define _ADC_SCANCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRL */ 489 #define _ADC_SCANCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRL */ 490 #define _ADC_SCANCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRL */ 491 #define _ADC_SCANCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRL */ 492 #define _ADC_SCANCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRL */ 493 #define _ADC_SCANCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRL */ 494 #define _ADC_SCANCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRL */ 495 #define _ADC_SCANCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRL */ 496 #define _ADC_SCANCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRL */ 497 #define ADC_SCANCTRL_PRSSEL_DEFAULT (_ADC_SCANCTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ 498 #define ADC_SCANCTRL_PRSSEL_PRSCH0 (_ADC_SCANCTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SCANCTRL */ 499 #define ADC_SCANCTRL_PRSSEL_PRSCH1 (_ADC_SCANCTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SCANCTRL */ 500 #define ADC_SCANCTRL_PRSSEL_PRSCH2 (_ADC_SCANCTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SCANCTRL */ 501 #define ADC_SCANCTRL_PRSSEL_PRSCH3 (_ADC_SCANCTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SCANCTRL */ 502 #define ADC_SCANCTRL_PRSSEL_PRSCH4 (_ADC_SCANCTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SCANCTRL */ 503 #define ADC_SCANCTRL_PRSSEL_PRSCH5 (_ADC_SCANCTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SCANCTRL */ 504 #define ADC_SCANCTRL_PRSSEL_PRSCH6 (_ADC_SCANCTRL_PRSSEL_PRSCH6 << 28) /**< Shifted mode PRSCH6 for ADC_SCANCTRL */ 505 #define ADC_SCANCTRL_PRSSEL_PRSCH7 (_ADC_SCANCTRL_PRSSEL_PRSCH7 << 28) /**< Shifted mode PRSCH7 for ADC_SCANCTRL */ 506 #define ADC_SCANCTRL_PRSSEL_PRSCH8 (_ADC_SCANCTRL_PRSSEL_PRSCH8 << 28) /**< Shifted mode PRSCH8 for ADC_SCANCTRL */ 507 #define ADC_SCANCTRL_PRSSEL_PRSCH9 (_ADC_SCANCTRL_PRSSEL_PRSCH9 << 28) /**< Shifted mode PRSCH9 for ADC_SCANCTRL */ 508 #define ADC_SCANCTRL_PRSSEL_PRSCH10 (_ADC_SCANCTRL_PRSSEL_PRSCH10 << 28) /**< Shifted mode PRSCH10 for ADC_SCANCTRL */ 509 #define ADC_SCANCTRL_PRSSEL_PRSCH11 (_ADC_SCANCTRL_PRSSEL_PRSCH11 << 28) /**< Shifted mode PRSCH11 for ADC_SCANCTRL */ 510 511 /* Bit fields for ADC IEN */ 512 #define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */ 513 #define _ADC_IEN_MASK 0x00000303UL /**< Mask for ADC_IEN */ 514 #define ADC_IEN_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Enable */ 515 #define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ 516 #define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ 517 #define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ 518 #define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */ 519 #define ADC_IEN_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Enable */ 520 #define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ 521 #define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ 522 #define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ 523 #define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */ 524 #define ADC_IEN_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Enable */ 525 #define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ 526 #define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ 527 #define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ 528 #define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */ 529 #define ADC_IEN_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Enable */ 530 #define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ 531 #define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ 532 #define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ 533 #define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */ 534 535 /* Bit fields for ADC IF */ 536 #define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */ 537 #define _ADC_IF_MASK 0x00000303UL /**< Mask for ADC_IF */ 538 #define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */ 539 #define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ 540 #define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ 541 #define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ 542 #define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */ 543 #define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */ 544 #define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ 545 #define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ 546 #define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ 547 #define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */ 548 #define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag */ 549 #define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ 550 #define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ 551 #define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ 552 #define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */ 553 #define ADC_IF_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag */ 554 #define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ 555 #define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ 556 #define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ 557 #define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */ 558 559 /* Bit fields for ADC IFS */ 560 #define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */ 561 #define _ADC_IFS_MASK 0x00000303UL /**< Mask for ADC_IFS */ 562 #define ADC_IFS_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Set */ 563 #define _ADC_IFS_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ 564 #define _ADC_IFS_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ 565 #define _ADC_IFS_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ 566 #define ADC_IFS_SINGLE_DEFAULT (_ADC_IFS_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFS */ 567 #define ADC_IFS_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Set */ 568 #define _ADC_IFS_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ 569 #define _ADC_IFS_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ 570 #define _ADC_IFS_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ 571 #define ADC_IFS_SCAN_DEFAULT (_ADC_IFS_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFS */ 572 #define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Set */ 573 #define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ 574 #define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ 575 #define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ 576 #define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */ 577 #define ADC_IFS_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Set */ 578 #define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ 579 #define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ 580 #define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ 581 #define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */ 582 583 /* Bit fields for ADC IFC */ 584 #define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */ 585 #define _ADC_IFC_MASK 0x00000303UL /**< Mask for ADC_IFC */ 586 #define ADC_IFC_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Clear */ 587 #define _ADC_IFC_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ 588 #define _ADC_IFC_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ 589 #define _ADC_IFC_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ 590 #define ADC_IFC_SINGLE_DEFAULT (_ADC_IFC_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFC */ 591 #define ADC_IFC_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Clear */ 592 #define _ADC_IFC_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ 593 #define _ADC_IFC_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ 594 #define _ADC_IFC_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ 595 #define ADC_IFC_SCAN_DEFAULT (_ADC_IFC_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFC */ 596 #define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Clear */ 597 #define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ 598 #define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ 599 #define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ 600 #define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */ 601 #define ADC_IFC_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Clear */ 602 #define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ 603 #define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ 604 #define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ 605 #define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */ 606 607 /* Bit fields for ADC SINGLEDATA */ 608 #define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */ 609 #define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */ 610 #define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ 611 #define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ 612 #define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */ 613 #define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */ 614 615 /* Bit fields for ADC SCANDATA */ 616 #define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */ 617 #define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */ 618 #define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ 619 #define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ 620 #define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */ 621 #define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */ 622 623 /* Bit fields for ADC SINGLEDATAP */ 624 #define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */ 625 #define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */ 626 #define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ 627 #define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ 628 #define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */ 629 #define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */ 630 631 /* Bit fields for ADC SCANDATAP */ 632 #define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */ 633 #define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */ 634 #define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ 635 #define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ 636 #define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */ 637 #define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */ 638 639 /* Bit fields for ADC CAL */ 640 #define _ADC_CAL_RESETVALUE 0x3F003F00UL /**< Default value for ADC_CAL */ 641 #define _ADC_CAL_MASK 0x7F7F7F7FUL /**< Mask for ADC_CAL */ 642 #define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */ 643 #define _ADC_CAL_SINGLEOFFSET_MASK 0x7FUL /**< Bit mask for ADC_SINGLEOFFSET */ 644 #define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ 645 #define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */ 646 #define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */ 647 #define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */ 648 #define _ADC_CAL_SINGLEGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */ 649 #define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */ 650 #define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */ 651 #define _ADC_CAL_SCANOFFSET_MASK 0x7F0000UL /**< Bit mask for ADC_SCANOFFSET */ 652 #define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ 653 #define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */ 654 #define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */ 655 #define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */ 656 #define _ADC_CAL_SCANGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */ 657 #define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */ 658 659 /* Bit fields for ADC BIASPROG */ 660 #define _ADC_BIASPROG_RESETVALUE 0x00000747UL /**< Default value for ADC_BIASPROG */ 661 #define _ADC_BIASPROG_MASK 0x00000F4FUL /**< Mask for ADC_BIASPROG */ 662 #define _ADC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for ADC_BIASPROG */ 663 #define _ADC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for ADC_BIASPROG */ 664 #define _ADC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */ 665 #define ADC_BIASPROG_BIASPROG_DEFAULT (_ADC_BIASPROG_BIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */ 666 #define ADC_BIASPROG_HALFBIAS (0x1UL << 6) /**< Half Bias Current */ 667 #define _ADC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for ADC_HALFBIAS */ 668 #define _ADC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for ADC_HALFBIAS */ 669 #define _ADC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_BIASPROG */ 670 #define ADC_BIASPROG_HALFBIAS_DEFAULT (_ADC_BIASPROG_HALFBIAS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_BIASPROG */ 671 #define _ADC_BIASPROG_COMPBIAS_SHIFT 8 /**< Shift value for ADC_COMPBIAS */ 672 #define _ADC_BIASPROG_COMPBIAS_MASK 0xF00UL /**< Bit mask for ADC_COMPBIAS */ 673 #define _ADC_BIASPROG_COMPBIAS_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */ 674 #define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */ 675 676 /** @} End of group EFM32WG_ADC */ 677 /** @} End of group Parts */ 678
