1 /***************************************************************************//**
2 * @file
3 * @brief Incremental Analog to Digital Converter (IADC) peripheral API
4 *******************************************************************************
5 * # License
6 * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
7 *******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 ******************************************************************************/
30
31 #ifndef EM_IADC_H
32 #define EM_IADC_H
33
34 #include "em_device.h"
35 #include "em_gpio.h"
36 #include "em_system.h"
37 #if defined(IADC_COUNT) && (IADC_COUNT > 0)
38
39 #include <stdbool.h>
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /***************************************************************************//**
46 * @addtogroup iadc
47 * @{
48 ******************************************************************************/
49
50 /*******************************************************************************
51 ******************************** ENUMS ************************************
52 ******************************************************************************/
53
54 /** Warm-up mode. */
55 typedef enum {
56 /** IADC shutdown after each conversion. */
57 iadcWarmupNormal = _IADC_CTRL_WARMUPMODE_NORMAL,
58
59 /** ADC is kept in standby mode between conversion. */
60 iadcWarmupKeepInStandby = _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY,
61
62 /** ADC and reference selected for scan mode kept warmup, allowing
63 continuous conversion. */
64 iadcWarmupKeepWarm = _IADC_CTRL_WARMUPMODE_KEEPWARM
65 } IADC_Warmup_t;
66
67 /** IADC result alignment. */
68 typedef enum {
69 /** IADC results 12-bit right aligned */
70 iadcAlignRight12 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12,
71
72 /** IADC results 12-bit left aligned */
73 iadcAlignLeft12 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12,
74
75 #if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16)
76 /** IADC results 16-bit right aligned */
77 iadcAlignRight16 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16,
78
79 /** IADC results 16-bit left aligned */
80 iadcAlignLeft16 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16,
81 #endif
82
83 #if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20)
84 /** IADC results 20-bit right aligned */
85 iadcAlignRight20 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20,
86
87 /** IADC results 20-bit left aligned */
88 iadcAlignLeft20 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20,
89 #endif
90 } IADC_Alignment_t;
91
92 /** IADC negative input selection. */
93 typedef enum {
94 /** Ground */
95 iadcNegInputGnd = (_IADC_SCAN_PORTNEG_GND << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT))
96 | 1,
97 /** Ground using even mux */
98 iadcNegInputGndaux = (_IADC_SCAN_PORTNEG_GND << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)),
99
100 #if defined(_IADC_SCAN_PORTNEG_DAC1)
101 /** Direct connection to DAC_1 input pin */
102 iadcNegInputDac1 = (_IADC_SCAN_PORTNEG_DAC1 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)),
103 #endif
104 #if defined(_IADC_SCAN_PORTNEG_PADANA1)
105 /** Direct connection to Pad_ana_1 input pin */
106 iadcNegInputPadAna1 = (_IADC_SCAN_PORTNEG_PADANA1 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)),
107 #endif
108 #if defined(_IADC_SCAN_PORTNEG_PADANA3)
109 /** Direct connection to Pad_ana_3 input pin */
110 iadcNegInputPadAna3 = (_IADC_SCAN_PORTNEG_PADANA3 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)),
111 #endif
112 #if defined(_IADC_SCAN_PORTNEG_PADREFNEG)
113 /** Negative reference pin 0 */
114 iadcNegInputNegRef = (_IADC_SCAN_PORTNEG_PADREFNEG << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)),
115 #endif
116 /** GPIO port A pin 0 */
117 iadcNegInputPortAPin0 = (_IADC_SCAN_PORTNEG_PORTA << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)),
118
119 /** GPIO port A pin 1 */
120 iadcNegInputPortAPin1,
121
122 /** GPIO port A pin 2 */
123 iadcNegInputPortAPin2,
124
125 /** GPIO port A pin 3 */
126 iadcNegInputPortAPin3,
127
128 /** GPIO port A pin 4 */
129 iadcNegInputPortAPin4,
130
131 /** GPIO port A pin 5 */
132 iadcNegInputPortAPin5,
133
134 /** GPIO port A pin 6 */
135 iadcNegInputPortAPin6,
136
137 /** GPIO port A pin 7 */
138 iadcNegInputPortAPin7,
139
140 /** GPIO port A pin 8 */
141 iadcNegInputPortAPin8,
142
143 /** GPIO port A pin 9 */
144 iadcNegInputPortAPin9,
145
146 /** GPIO port A pin 10 */
147 iadcNegInputPortAPin10,
148
149 /** GPIO port A pin 11 */
150 iadcNegInputPortAPin11,
151
152 /** GPIO port A pin 12 */
153 iadcNegInputPortAPin12,
154
155 /** GPIO port A pin 13 */
156 iadcNegInputPortAPin13,
157
158 /** GPIO port A pin 14 */
159 iadcNegInputPortAPin14,
160
161 /** GPIO port A pin 15 */
162 iadcNegInputPortAPin15,
163
164 /** GPIO port B pin 0 */
165 iadcNegInputPortBPin0,
166
167 /** GPIO port B pin 1 */
168 iadcNegInputPortBPin1,
169
170 /** GPIO port B pin 2 */
171 iadcNegInputPortBPin2,
172
173 /** GPIO port B pin 3 */
174 iadcNegInputPortBPin3,
175
176 /** GPIO port B pin 4 */
177 iadcNegInputPortBPin4,
178
179 /** GPIO port B pin 5 */
180 iadcNegInputPortBPin5,
181
182 /** GPIO port B pin 6 */
183 iadcNegInputPortBPin6,
184
185 /** GPIO port B pin 7 */
186 iadcNegInputPortBPin7,
187
188 /** GPIO port B pin 8 */
189 iadcNegInputPortBPin8,
190
191 /** GPIO port B pin 9 */
192 iadcNegInputPortBPin9,
193
194 /** GPIO port B pin 10 */
195 iadcNegInputPortBPin10,
196
197 /** GPIO port B pin 11 */
198 iadcNegInputPortBPin11,
199
200 /** GPIO port B pin 12 */
201 iadcNegInputPortBPin12,
202
203 /** GPIO port B pin 13 */
204 iadcNegInputPortBPin13,
205
206 /** GPIO port B pin 14 */
207 iadcNegInputPortBPin14,
208
209 /** GPIO port B pin 15 */
210 iadcNegInputPortBPin15,
211
212 /** GPIO port C pin 0 */
213 iadcNegInputPortCPin0,
214
215 /** GPIO port C pin 1 */
216 iadcNegInputPortCPin1,
217
218 /** GPIO port C pin 2 */
219 iadcNegInputPortCPin2,
220
221 /** GPIO port C pin 3 */
222 iadcNegInputPortCPin3,
223
224 /** GPIO port C pin 4 */
225 iadcNegInputPortCPin4,
226
227 /** GPIO port C pin 5 */
228 iadcNegInputPortCPin5,
229
230 /** GPIO port C pin 6 */
231 iadcNegInputPortCPin6,
232
233 /** GPIO port C pin 7 */
234 iadcNegInputPortCPin7,
235
236 /** GPIO port C pin 8 */
237 iadcNegInputPortCPin8,
238
239 /** GPIO port C pin 9 */
240 iadcNegInputPortCPin9,
241
242 /** GPIO port C pin 10 */
243 iadcNegInputPortCPin10,
244
245 /** GPIO port C pin 11 */
246 iadcNegInputPortCPin11,
247
248 /** GPIO port C pin 12 */
249 iadcNegInputPortCPin12,
250
251 /** GPIO port C pin 13 */
252 iadcNegInputPortCPin13,
253
254 /** GPIO port C pin 14 */
255 iadcNegInputPortCPin14,
256
257 /** GPIO port C pin 15 */
258 iadcNegInputPortCPin15,
259
260 /** GPIO port D pin 0 */
261 iadcNegInputPortDPin0,
262
263 /** GPIO port D pin 1 */
264 iadcNegInputPortDPin1,
265
266 /** GPIO port D pin 2 */
267 iadcNegInputPortDPin2,
268
269 /** GPIO port D pin 3 */
270 iadcNegInputPortDPin3,
271
272 /** GPIO port D pin 4 */
273 iadcNegInputPortDPin4,
274
275 /** GPIO port D pin 5 */
276 iadcNegInputPortDPin5,
277
278 /** GPIO port D pin 6 */
279 iadcNegInputPortDPin6,
280
281 /** GPIO port D pin 7 */
282 iadcNegInputPortDPin7,
283
284 /** GPIO port D pin 8 */
285 iadcNegInputPortDPin8,
286
287 /** GPIO port D pin 9 */
288 iadcNegInputPortDPin9,
289
290 /** GPIO port D pin 10 */
291 iadcNegInputPortDPin10,
292
293 /** GPIO port D pin 11 */
294 iadcNegInputPortDPin11,
295
296 /** GPIO port D pin 12 */
297 iadcNegInputPortDPin12,
298
299 /** GPIO port D pin 13 */
300 iadcNegInputPortDPin13,
301
302 /** GPIO port D pin 14 */
303 iadcNegInputPortDPin14,
304
305 /** GPIO port D pin 15 */
306 iadcNegInputPortDPin15
307 } IADC_NegInput_t;
308
309 /** IADC positive port selection. */
310 typedef enum {
311 /** Ground */
312 iadcPosInputGnd = (_IADC_SCAN_PORTPOS_GND << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)),
313
314 /** Avdd / 4 */
315 iadcPosInputAvdd = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT))
316 | 0,
317
318 /** Vddio / 4 */
319 iadcPosInputVddio = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT))
320 | 1,
321
322 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
323 /** Vddio1 / 4 */
324 iadcPosInputVddio1 = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT))
325 | 2,
326
327 /** Vddio2 / 4 */
328 iadcPosInputVddio2 = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT))
329 | 3,
330 #else
331 /** Vss */
332 iadcPosInputVss = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT))
333 | 2,
334
335 /** Vss */
336 iadcPosInputVssaux = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT))
337 | 3,
338 #endif
339
340 /** Dvdd / 4 */
341 iadcPosInputDvdd = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT))
342 | 4,
343
344 /** Decouple */
345 iadcPosInputDecouple = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT))
346 | 7,
347
348 #if defined(_IADC_SCAN_PORTPOS_DAC0)
349 /** Direct connection to DAC_0 input pin */
350 iadcPosInputDac0 = (_IADC_SCAN_PORTPOS_DAC0 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)),
351 #endif
352 #if defined(_IADC_SCAN_PORTPOS_PADANA0)
353 /** Direct connection to Pad_ana_0 input pin */
354 iadcPosInputPadAna0 = (_IADC_SCAN_PORTPOS_PADANA0 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)),
355 #endif
356 #if defined(_IADC_SCAN_PORTPOS_PADANA2)
357 /** Direct connection to Pad_ana_2 input pin */
358 iadcPosInputPadAna2 = (_IADC_SCAN_PORTPOS_PADANA2 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)),
359 #endif
360 #if defined(_IADC_SCAN_PORTPOS_PADREFPOS)
361 /** Positive reference pin 0 */
362 iadcPosInputPosRef = (_IADC_SCAN_PORTPOS_PADREFPOS << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)),
363 #endif
364
365 /** GPIO port A pin 0 */
366 iadcPosInputPortAPin0 = (_IADC_SCAN_PORTPOS_PORTA << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)),
367
368 /** GPIO port A pin 1 */
369 iadcPosInputPortAPin1,
370
371 /** GPIO port A pin 2 */
372 iadcPosInputPortAPin2,
373
374 /** GPIO port A pin 3 */
375 iadcPosInputPortAPin3,
376
377 /** GPIO port A pin 4 */
378 iadcPosInputPortAPin4,
379
380 /** GPIO port A pin 5 */
381 iadcPosInputPortAPin5,
382
383 /** GPIO port A pin 6 */
384 iadcPosInputPortAPin6,
385
386 /** GPIO port A pin 7 */
387 iadcPosInputPortAPin7,
388
389 /** GPIO port A pin 8 */
390 iadcPosInputPortAPin8,
391
392 /** GPIO port A pin 9 */
393 iadcPosInputPortAPin9,
394
395 /** GPIO port A pin 10 */
396 iadcPosInputPortAPin10,
397
398 /** GPIO port A pin 11 */
399 iadcPosInputPortAPin11,
400
401 /** GPIO port A pin 12 */
402 iadcPosInputPortAPin12,
403
404 /** GPIO port A pin 13 */
405 iadcPosInputPortAPin13,
406
407 /** GPIO port A pin 14 */
408 iadcPosInputPortAPin14,
409
410 /** GPIO port A pin 15 */
411 iadcPosInputPortAPin15,
412
413 /** GPIO port B pin 0 */
414 iadcPosInputPortBPin0,
415
416 /** GPIO port B pin 1 */
417 iadcPosInputPortBPin1,
418
419 /** GPIO port B pin 2 */
420 iadcPosInputPortBPin2,
421
422 /** GPIO port B pin 3 */
423 iadcPosInputPortBPin3,
424
425 /** GPIO port B pin 4 */
426 iadcPosInputPortBPin4,
427
428 /** GPIO port B pin 5 */
429 iadcPosInputPortBPin5,
430
431 /** GPIO port B pin 6 */
432 iadcPosInputPortBPin6,
433
434 /** GPIO port B pin 7 */
435 iadcPosInputPortBPin7,
436
437 /** GPIO port B pin 8 */
438 iadcPosInputPortBPin8,
439
440 /** GPIO port B pin 9 */
441 iadcPosInputPortBPin9,
442
443 /** GPIO port B pin 10 */
444 iadcPosInputPortBPin10,
445
446 /** GPIO port B pin 11 */
447 iadcPosInputPortBPin11,
448
449 /** GPIO port B pin 12 */
450 iadcPosInputPortBPin12,
451
452 /** GPIO port B pin 13 */
453 iadcPosInputPortBPin13,
454
455 /** GPIO port B pin 14 */
456 iadcPosInputPortBPin14,
457
458 /** GPIO port B pin 15 */
459 iadcPosInputPortBPin15,
460
461 /** GPIO port C pin 0 */
462 iadcPosInputPortCPin0,
463
464 /** GPIO port C pin 1 */
465 iadcPosInputPortCPin1,
466
467 /** GPIO port C pin 2 */
468 iadcPosInputPortCPin2,
469
470 /** GPIO port C pin 3 */
471 iadcPosInputPortCPin3,
472
473 /** GPIO port C pin 4 */
474 iadcPosInputPortCPin4,
475
476 /** GPIO port C pin 5 */
477 iadcPosInputPortCPin5,
478
479 /** GPIO port C pin 6 */
480 iadcPosInputPortCPin6,
481
482 /** GPIO port C pin 7 */
483 iadcPosInputPortCPin7,
484
485 /** GPIO port C pin 8 */
486 iadcPosInputPortCPin8,
487
488 /** GPIO port C pin 9 */
489 iadcPosInputPortCPin9,
490
491 /** GPIO port C pin 10 */
492 iadcPosInputPortCPin10,
493
494 /** GPIO port C pin 11 */
495 iadcPosInputPortCPin11,
496
497 /** GPIO port C pin 12 */
498 iadcPosInputPortCPin12,
499
500 /** GPIO port C pin 13 */
501 iadcPosInputPortCPin13,
502
503 /** GPIO port C pin 14 */
504 iadcPosInputPortCPin14,
505
506 /** GPIO port C pin 15 */
507 iadcPosInputPortCPin15,
508
509 /** GPIO port D pin 0 */
510 iadcPosInputPortDPin0,
511
512 /** GPIO port D pin 1 */
513 iadcPosInputPortDPin1,
514
515 /** GPIO port D pin 2 */
516 iadcPosInputPortDPin2,
517
518 /** GPIO port D pin 3 */
519 iadcPosInputPortDPin3,
520
521 /** GPIO port D pin 4 */
522 iadcPosInputPortDPin4,
523
524 /** GPIO port D pin 5 */
525 iadcPosInputPortDPin5,
526
527 /** GPIO port D pin 6 */
528 iadcPosInputPortDPin6,
529
530 /** GPIO port D pin 7 */
531 iadcPosInputPortDPin7,
532
533 /** GPIO port D pin 8 */
534 iadcPosInputPortDPin8,
535
536 /** GPIO port D pin 9 */
537 iadcPosInputPortDPin9,
538
539 /** GPIO port D pin 10 */
540 iadcPosInputPortDPin10,
541
542 /** GPIO port D pin 11 */
543 iadcPosInputPortDPin11,
544
545 /** GPIO port D pin 12 */
546 iadcPosInputPortDPin12,
547
548 /** GPIO port D pin 13 */
549 iadcPosInputPortDPin13,
550
551 /** GPIO port D pin 14 */
552 iadcPosInputPortDPin14,
553
554 /** GPIO port D pin 15 */
555 iadcPosInputPortDPin15
556 } IADC_PosInput_t;
557
558 /** IADC Commands. */
559 typedef enum {
560 /** Start single queue */
561 iadcCmdStartSingle = IADC_CMD_SINGLESTART,
562
563 /** Stop single queue */
564 iadcCmdStopSingle = IADC_CMD_SINGLESTOP,
565
566 /** Start scan queue */
567 iadcCmdStartScan = IADC_CMD_SCANSTART,
568
569 /** Stop scan queue */
570 iadcCmdStopScan = IADC_CMD_SCANSTOP,
571
572 /** Enable Timer */
573 iadcCmdEnableTimer = IADC_CMD_TIMEREN,
574
575 /** Disable Timer */
576 iadcCmdDisableTimer = IADC_CMD_TIMERDIS
577 } IADC_Cmd_t;
578
579 /** IADC Configuration. */
580 typedef enum {
581 /** Normal mode */
582 iadcCfgModeNormal = _IADC_CFG_ADCMODE_NORMAL,
583 #if defined(_IADC_CFG_ADCMODE_HIGHSPEED)
584 /** High Speed mode */
585 iadcCfgModeHighSpeed = _IADC_CFG_ADCMODE_HIGHSPEED,
586 #endif
587 #if defined(_IADC_CFG_ADCMODE_HIGHACCURACY)
588 /** High Accuracy mode */
589 iadcCfgModeHighAccuracy = _IADC_CFG_ADCMODE_HIGHACCURACY
590 #endif
591 } IADC_CfgAdcMode_t;
592
593 /** IADC Over sampling rate for high speed. */
594 typedef enum {
595 /** High speed oversampling of 2x */
596 iadcCfgOsrHighSpeed2x = _IADC_CFG_OSRHS_HISPD2,
597
598 /** High speed oversampling of 4x */
599 iadcCfgOsrHighSpeed4x = _IADC_CFG_OSRHS_HISPD4,
600
601 /** High speed oversampling of 8x */
602 iadcCfgOsrHighSpeed8x = _IADC_CFG_OSRHS_HISPD8,
603
604 /** High speed oversampling of 16x */
605 iadcCfgOsrHighSpeed16x = _IADC_CFG_OSRHS_HISPD16,
606
607 /** High speed oversampling of 32x */
608 iadcCfgOsrHighSpeed32x = _IADC_CFG_OSRHS_HISPD32,
609
610 /** High speed oversampling of 64x */
611 iadcCfgOsrHighSpeed64x = _IADC_CFG_OSRHS_HISPD64
612 } IADC_CfgOsrHighSpeed_t;
613
614 #if defined(_IADC_CFG_ADCMODE_HIGHACCURACY)
615 /** IADC Over sampling rate for high accuracy. */
616 typedef enum {
617 /** High accuracy oversampling of 16x */
618 iadcCfgOsrHighAccuracy16x = _IADC_CFG_OSRHA_HIACC16,
619
620 /** High accuracy oversampling of 32x */
621 iadcCfgOsrHighAccuracy32x = _IADC_CFG_OSRHA_HIACC32,
622
623 /** High accuracy oversampling of 64x */
624 iadcCfgOsrHighAccuracy64x = _IADC_CFG_OSRHA_HIACC64,
625
626 /** High accuracy oversampling of 92x */
627 iadcCfgOsrHighAccuracy92x = _IADC_CFG_OSRHA_HIACC92,
628
629 /** High accuracy oversampling of 128x */
630 iadcCfgOsrHighAccuracy128x = _IADC_CFG_OSRHA_HIACC128,
631
632 /** High accuracy oversampling of 256x */
633 iadcCfgOsrHighAccuracy256x = _IADC_CFG_OSRHA_HIACC256
634 } IADC_CfgOsrHighAccuracy_t;
635 #endif
636
637 /** IADC Analog Gain. */
638 typedef enum {
639 #if defined(_IADC_CFG_ANALOGGAIN_ANAGAIN0P25)
640 /** Analog gain of 0.25x */
641 iadcCfgAnalogGain0P25x = _IADC_CFG_ANALOGGAIN_ANAGAIN0P25,
642 #endif
643 /** Analog gain of 0.5x */
644 iadcCfgAnalogGain0P5x = _IADC_CFG_ANALOGGAIN_ANAGAIN0P5,
645
646 /** Analog gain of 1x */
647 iadcCfgAnalogGain1x = _IADC_CFG_ANALOGGAIN_ANAGAIN1,
648
649 /** Analog gain of 2x */
650 iadcCfgAnalogGain2x = _IADC_CFG_ANALOGGAIN_ANAGAIN2,
651
652 /** Analog gain of 3x */
653 iadcCfgAnalogGain3x = _IADC_CFG_ANALOGGAIN_ANAGAIN3,
654
655 /** Analog gain of 4x */
656 iadcCfgAnalogGain4x = _IADC_CFG_ANALOGGAIN_ANAGAIN4
657 } IADC_CfgAnalogGain_t;
658
659 /** IADC Reference */
660 typedef enum {
661 /** Internal 1.2V Band Gap Reference (buffered) to ground */
662 iadcCfgReferenceInt1V2 = _IADC_CFG_REFSEL_VBGR,
663
664 /** External reference (unbuffered) VREFP to VREFN.
665 * VEVREF up to AVDD. When inputs are routed to external GPIO pins,
666 * the maximum pin voltage is limited to the lower
667 * of the IOVDD and AVDD supplies.
668 * The internal calibration values correspond to a 1.25V reference,
669 * use of other voltages may require recalibration.
670 * See AN1189: Incremental Analog to Digital Converter (IADC) */
671 iadcCfgReferenceExt1V25 = _IADC_CFG_REFSEL_VREF,
672
673 #if defined(_IADC_CFG_REFSEL_VREF2P5)
674 /** External reference (unbuffered) VREFP to VREFN. Supports 2.5V in high accuracy mode. */
675 iadcCfgReferenceExt2V5 = _IADC_CFG_REFSEL_VREF2P5,
676 #endif
677
678 /** VDDX (unbuffered) to ground. */
679 iadcCfgReferenceVddx = _IADC_CFG_REFSEL_VDDX,
680
681 /** 0.8 * VDDX (buffered) to ground. */
682 iadcCfgReferenceVddX0P8Buf = _IADC_CFG_REFSEL_VDDX0P8BUF,
683
684 #if defined(_IADC_CFG_REFSEL_VREFBUF)
685 /** pad_vrefp (buffered) to pad_vrefn (pad_refp < vddx - 0.3) */
686 iadcCfgReferenceBuf = _IADC_CFG_REFSEL_VREFBUF,
687 #endif
688
689 #if defined(_IADC_CFG_REFSEL_VREF0P8BUF)
690 /** pad_vref (buffered) * 0.8 to pad_vrefn (LPF pad_refp noise) */
691 iadcCfgReference0P8Buf = _IADC_CFG_REFSEL_VREF0P8BUF,
692 #endif
693 } IADC_CfgReference_t;
694
695 /** IADC Two's complement results */
696 typedef enum {
697 /** Automatic. Single ended => Unipolar, Differential => Bipolar */
698 iadcCfgTwosCompAuto = _IADC_CFG_TWOSCOMPL_AUTO,
699
700 /** All results in unipolar format. Negative diff input gives 0 as result. */
701 iadcCfgTwosCompUnipolar = _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR,
702
703 /** All results in bipolar (2's complement) format. Half range for SE. */
704 iadcCfgTwosCompBipolar = _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR
705 } IADC_CfgTwosComp_t;
706
707 /** IADC trigger action */
708 typedef enum {
709 /** Start single/scan queue immediately */
710 iadcTriggerSelImmediate = _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE,
711
712 /** Timer starts single/scan queue */
713 iadcTriggerSelTimer = _IADC_TRIGGER_SCANTRIGSEL_TIMER,
714
715 /** PRS0 from timer in same clock group starts single/scan queue */
716 iadcTriggerSelPrs0SameClk = _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP,
717
718 /** PRS0 positive edge starts single/scan queue */
719 iadcTriggerSelPrs0PosEdge = _IADC_TRIGGER_SCANTRIGSEL_PRSPOS,
720
721 /** PRS0 negative edge starts single/scan queue */
722 iadcTriggerSelPrs0NegEdge = _IADC_TRIGGER_SCANTRIGSEL_PRSNEG,
723
724 #if defined(_IADC_TRIGGER_SCANTRIGSEL_LESENSE)
725 /** LESENSE starts scan queue */
726 iadcTriggerSelLesense = _IADC_TRIGGER_SCANTRIGSEL_LESENSE
727 #endif
728 } IADC_TriggerSel_t;
729
730 /** IADC trigger action */
731 typedef enum {
732 /** Convert single/scan queue once per trigger */
733 iadcTriggerActionOnce = _IADC_TRIGGER_SCANTRIGACTION_ONCE,
734
735 /** Convert single/scan queue continuously */
736 iadcTriggerActionContinuous = _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS,
737 } IADC_TriggerAction_t;
738
739 /** IADC data valid level before requesting DMA transfer */
740 typedef enum {
741 /** Data valid level is 1 before requesting DMA transfer */
742 iadcFifoCfgDvl1 = _IADC_SCANFIFOCFG_DVL_VALID1,
743
744 /** Data valid level is 2 before requesting DMA transfer */
745 iadcFifoCfgDvl2 = _IADC_SCANFIFOCFG_DVL_VALID2,
746
747 /** Data valid level is 3 before requesting DMA transfer */
748 iadcFifoCfgDvl3 = _IADC_SCANFIFOCFG_DVL_VALID3,
749
750 /** Data valid level is 4 before requesting DMA transfer */
751 iadcFifoCfgDvl4 = _IADC_SCANFIFOCFG_DVL_VALID4,
752
753 #if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)
754 #if _SILICON_LABS_32B_SERIES_2_CONFIG > 2
755 /** Data valid level is 5 before requesting DMA transfer */
756 iadcFifoCfgDvl5 = _IADC_SCANFIFOCFG_DVL_VALID5,
757
758 /** Data valid level is 6 before requesting DMA transfer */
759 iadcFifoCfgDvl6 = _IADC_SCANFIFOCFG_DVL_VALID6,
760
761 /** Data valid level is 7 before requesting DMA transfer */
762 iadcFifoCfgDvl7 = _IADC_SCANFIFOCFG_DVL_VALID7,
763 #endif
764
765 #if _SILICON_LABS_32B_SERIES_2_CONFIG > 3
766 /** Data valid level is 8 before requesting DMA transfer */
767 iadcFifoCfgDvl8 = _IADC_SCANFIFOCFG_DVL_VALID8
768 #endif
769 #endif
770 } IADC_FifoCfgDvl_t;
771
772 #if defined(_IADC_CFG_DIGAVG_MASK)
773 /** IADC digital averaging function. */
774 typedef enum {
775 /** Average over 1 sample (no averaging). */
776 iadcDigitalAverage1 = _IADC_CFG_DIGAVG_AVG1,
777
778 /** Average over 2 samples. */
779 iadcDigitalAverage2 = _IADC_CFG_DIGAVG_AVG2,
780
781 /** Average over 4 samples. */
782 iadcDigitalAverage4 = _IADC_CFG_DIGAVG_AVG4,
783
784 /** Average over 8 samples. */
785 iadcDigitalAverage8 = _IADC_CFG_DIGAVG_AVG8,
786
787 /** Average over 16 samples. */
788 iadcDigitalAverage16 = _IADC_CFG_DIGAVG_AVG16
789 } IADC_DigitalAveraging_t;
790 #endif
791
792 /*******************************************************************************
793 ******************************* STRUCTS ***********************************
794 ******************************************************************************/
795
796 /** IADC init structure, common for single conversion and scan sequence. */
797 typedef struct {
798 bool iadcClkSuspend0; /**< Suspend IADC_CLK when in scan mode until PRS trigger. */
799 bool iadcClkSuspend1; /**< Suspend IADC_CLK when in single mode until PRS trigger. */
800 bool debugHalt; /**< Halt IADC during debug mode. */
801 IADC_Warmup_t warmup; /**< IADC warmup mode. */
802 uint8_t timebase; /**< IADC clock cycles (timebase+1) corresponding to 1us.
803 Used as time reference for IADC delays, e.g. warmup.
804 If the user sets timebase to 0, then IADC_Init() will
805 calculate the timebase using the currently defined CMU
806 clock setting for the IADC. */
807 uint8_t srcClkPrescale; /**< User requested source clock divider (prescale+1) which
808 will be used if the calculated prescaler value is less. */
809 uint16_t timerCycles; /**< Number of ADC_CLK cycles per TIMER event. */
810 uint16_t greaterThanEqualThres; /**< Digital window comparator greater-than or equal threshold. */
811 uint16_t lessThanEqualThres; /**< Digital window comparator less-than or equal threshold. */
812 } IADC_Init_t;
813
814 /** Default config for IADC init structure. */
815 #define IADC_INIT_DEFAULT \
816 { \
817 false, /* IADC clock not disabled on PRS0*/ \
818 false, /* IADC clock not disabled on PRS1 */ \
819 false, /* Do not halt during debug */ \
820 iadcWarmupNormal, /* IADC shutdown after each conversion. */ \
821 0, /* Calculate timebase. */ \
822 0, /* Max IADC clock rate. */ \
823 _IADC_TIMER_TIMER_DEFAULT, /* Use HW default value. */ \
824 _IADC_CMPTHR_ADGT_DEFAULT, /* Use HW default value. */ \
825 _IADC_CMPTHR_ADLT_DEFAULT, /* Use HW default value. */ \
826 }
827
828 /** IADC config structure */
829 typedef struct {
830 IADC_CfgAdcMode_t adcMode; /**< IADC mode; Normal, High speed or High Accuracy. */
831 IADC_CfgOsrHighSpeed_t osrHighSpeed; /**< Over sampling ratio for High Speed and Normal modes. */
832 #if defined(_IADC_CFG_ADCMODE_HIGHACCURACY)
833 IADC_CfgOsrHighAccuracy_t osrHighAccuracy; /**< Over sampling ratio for High Accuracy mode. */
834 #endif
835 IADC_CfgAnalogGain_t analogGain; /**< Analog gain. */
836 IADC_CfgReference_t reference; /**< Reference selection. */
837 IADC_CfgTwosComp_t twosComplement; /**< Two's complement reporting. */
838 uint32_t adcClkPrescale; /**< ADC_CLK divider (prescale+1). */
839 uint32_t vRef; /**< Vref magnitude expressed in millivolts. */
840 #if defined(_IADC_CFG_DIGAVG_MASK)
841 IADC_DigitalAveraging_t digAvg; /**< Digital average mode. */
842 #endif
843 } IADC_Config_t;
844
845 #if defined(_IADC_CFG_DIGAVG_MASK)
846 #if defined(_IADC_CFG_ADCMODE_HIGHACCURACY)
847 /** Default IADC config structure. */
848 #define IADC_CONFIG_DEFAULT \
849 { \
850 iadcCfgModeNormal, /* Normal mode for IADC. */ \
851 iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \
852 iadcCfgOsrHighAccuracy92x, /* 92x high accuracy over sampling. */ \
853 iadcCfgAnalogGain1x, /* 1x analog gain. */ \
854 iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \
855 iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \
856 0, /* Max IADC analog clock rate. */ \
857 1210, /* Vref expressed in millivolts. */ \
858 iadcDigitalAverage1 /* No averaging. */ \
859 }
860 #else
861 /** Default IADC config structure. */
862 #define IADC_CONFIG_DEFAULT \
863 { \
864 iadcCfgModeNormal, /* Normal mode for IADC. */ \
865 iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \
866 iadcCfgAnalogGain1x, /* 1x analog gain. */ \
867 iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \
868 iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \
869 0, /* Max IADC analog clock rate. */ \
870 1210, /* Vref expressed in millivolts. */ \
871 iadcDigitalAverage1 /* No averaging. */ \
872 }
873 #endif
874 #else
875 #if defined(_IADC_CFG_ADCMODE_HIGHACCURACY)
876 /** Default IADC config structure. */
877 #define IADC_CONFIG_DEFAULT \
878 { \
879 iadcCfgModeNormal, /* Normal mode for IADC. */ \
880 iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \
881 iadcCfgOsrHighAccuracy92x, /* 92x high speed over sampling. */ \
882 iadcCfgAnalogGain1x, /* 1x analog gain. */ \
883 iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \
884 iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \
885 0, /* Max IADC analog clock rate. */ \
886 1210 /* Vref expressed in millivolts. */ \
887 }
888 #else
889 /** Default IADC config structure. */
890 #define IADC_CONFIG_DEFAULT \
891 { \
892 iadcCfgModeNormal, /* Normal mode for IADC. */ \
893 iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \
894 iadcCfgAnalogGain1x, /* 1x analog gain. */ \
895 iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \
896 iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \
897 0, /* Max IADC analog clock rate. */ \
898 1210 /* Vref expressed in millivolts. */ \
899 }
900 #endif
901 #endif
902
903 /** Structure for all IADC configs. */
904 typedef struct {
905 /** All IADC configs. */
906 IADC_Config_t configs[IADC0_CONFIGNUM];
907 } IADC_AllConfigs_t;
908
909 /** Default IADC sructure for all configs. */
910 #define IADC_ALLCONFIGS_DEFAULT \
911 { \
912 { \
913 IADC_CONFIG_DEFAULT, \
914 IADC_CONFIG_DEFAULT \
915 } \
916 }
917
918 /** IADC scan init structure */
919 typedef struct {
920 IADC_Alignment_t alignment; /**< Alignment of data in FIFO. */
921 bool showId; /**< Tag FIFO entry with scan table entry id. */
922 IADC_FifoCfgDvl_t dataValidLevel; /**< Data valid level before requesting DMA transfer. */
923 bool fifoDmaWakeup; /**< Wake-up DMA when FIFO reaches data valid level. */
924 IADC_TriggerSel_t triggerSelect; /**< Trigger selection. */
925 IADC_TriggerAction_t triggerAction; /**< Trigger action. */
926 bool start; /**< Start scan immediately. */
927 } IADC_InitScan_t;
928
929 /** Default config for IADC scan init structure. */
930 #define IADC_INITSCAN_DEFAULT \
931 { \
932 iadcAlignRight12, /* Results 12-bit right aligned */ \
933 false, /* Do not show ID in result */ \
934 iadcFifoCfgDvl4, /* Use HW default value. */ \
935 false, /* Do not wake up DMA on scan FIFO DVL */ \
936 iadcTriggerSelImmediate, /* Start scan immediately on trigger */ \
937 iadcTriggerActionOnce, /* Convert once on scan trigger */ \
938 false /* Do not start scan queue */ \
939 }
940
941 /** IADC single init structure */
942 typedef struct {
943 IADC_Alignment_t alignment; /**< Alignment of data in FIFO. */
944 bool showId; /**< Tag FIFO entry with single indicator (0x20). */
945 IADC_FifoCfgDvl_t dataValidLevel; /**< Data valid level before requesting DMA transfer. */
946 bool fifoDmaWakeup; /**< Wake-up DMA when FIFO reaches data valid level. */
947 IADC_TriggerSel_t triggerSelect; /**< Trigger selection. */
948 IADC_TriggerAction_t triggerAction; /**< Trigger action. */
949 bool singleTailgate; /**< If true, wait until end of SCAN queue
950 before single queue warmup and conversion. */
951 bool start; /**< Start scan immediately. */
952 } IADC_InitSingle_t;
953
954 /** Default config for IADC single init structure. */
955 #define IADC_INITSINGLE_DEFAULT \
956 { \
957 iadcAlignRight12, /* Results 12-bit right aligned */ \
958 false, /* Do not show ID in result */ \
959 iadcFifoCfgDvl4, /* Use HW default value. */ \
960 false, /* Do not wake up DMA on single FIFO DVL */ \
961 iadcTriggerSelImmediate, /* Start single immediately on trigger */ \
962 iadcTriggerActionOnce, /* Convert once on single trigger */ \
963 false, /* No tailgating */ \
964 false /* Do not start single queue */ \
965 }
966
967 /** IADC single input selection structure */
968 typedef struct {
969 IADC_NegInput_t negInput; /**< Port/pin input for the negative side of the ADC. */
970 IADC_PosInput_t posInput; /**< Port/pin input for the positive side of the ADC. */
971 uint8_t configId; /**< Configuration id. */
972 bool compare; /**< Perform digital window comparison on the result from this entry. */
973 } IADC_SingleInput_t;
974
975 /** Default config for IADC single input structure. */
976 #define IADC_SINGLEINPUT_DEFAULT \
977 { \
978 iadcNegInputGnd, /* Negative input GND */ \
979 iadcPosInputGnd, /* Positive input GND */ \
980 0, /* Config 0 */ \
981 false /* Do not compare results */ \
982 }
983
984 /** IADC scan table entry structure */
985 typedef struct {
986 IADC_NegInput_t negInput; /**< Port/pin input for the negative side of the ADC. */
987 IADC_PosInput_t posInput; /**< Port/pin input for the positive side of the ADC. */
988 uint8_t configId; /**< Configuration id. */
989 bool compare; /**< Perform digital window comparison on the result from this entry. */
990 bool includeInScan; /**< Include this scan table entry in scan operation. */
991 } IADC_ScanTableEntry_t;
992
993 /** Default config for IADC scan table entry structure. */
994 #define IADC_SCANTABLEENTRY_DEFAULT \
995 { \
996 iadcNegInputGnd,/* Negative input GND */ \
997 iadcPosInputGnd,/* Positive input GND */ \
998 0, /* Config 0 */ \
999 false, /* Do not compare results */ \
1000 false /* Do not include in scan */ \
1001 }
1002
1003 /** Structure for IADC scan table. */
1004 typedef struct {
1005 /** IADC scan table entries. */
1006 IADC_ScanTableEntry_t entries[IADC0_ENTRIES];
1007 } IADC_ScanTable_t;
1008
1009 /** Default IADC structure for scan table */
1010 #define IADC_SCANTABLE_DEFAULT \
1011 { \
1012 { \
1013 IADC_SCANTABLEENTRY_DEFAULT, \
1014 IADC_SCANTABLEENTRY_DEFAULT, \
1015 IADC_SCANTABLEENTRY_DEFAULT, \
1016 IADC_SCANTABLEENTRY_DEFAULT, \
1017 IADC_SCANTABLEENTRY_DEFAULT, \
1018 IADC_SCANTABLEENTRY_DEFAULT, \
1019 IADC_SCANTABLEENTRY_DEFAULT, \
1020 IADC_SCANTABLEENTRY_DEFAULT, \
1021 IADC_SCANTABLEENTRY_DEFAULT, \
1022 IADC_SCANTABLEENTRY_DEFAULT, \
1023 IADC_SCANTABLEENTRY_DEFAULT, \
1024 IADC_SCANTABLEENTRY_DEFAULT, \
1025 IADC_SCANTABLEENTRY_DEFAULT, \
1026 IADC_SCANTABLEENTRY_DEFAULT, \
1027 IADC_SCANTABLEENTRY_DEFAULT, \
1028 IADC_SCANTABLEENTRY_DEFAULT \
1029 } \
1030 }
1031
1032 /** Structure holding IADC result, including data and ID */
1033 typedef struct {
1034 uint32_t data; /**< ADC sample data. */
1035 uint8_t id; /**< ID of FIFO entry; Scan table entry id or single indicator (0x20). */
1036 } IADC_Result_t;
1037
1038 /*******************************************************************************
1039 ***************************** PROTOTYPES **********************************
1040 ******************************************************************************/
1041
1042 void IADC_init(IADC_TypeDef *iadc, const IADC_Init_t *init,
1043 const IADC_AllConfigs_t *allConfigs);
1044 void IADC_reset(IADC_TypeDef *iadc);
1045 void IADC_initScan(IADC_TypeDef *iadc,
1046 const IADC_InitScan_t *init,
1047 const IADC_ScanTable_t *scanTable);
1048 void IADC_updateScanEntry(IADC_TypeDef *iadc,
1049 uint8_t id,
1050 IADC_ScanTableEntry_t *entry);
1051 void IADC_setScanMask(IADC_TypeDef *iadc, uint32_t mask);
1052 void IADC_initSingle(IADC_TypeDef *iadc,
1053 const IADC_InitSingle_t *init,
1054 const IADC_SingleInput_t *input);
1055 void IADC_updateSingleInput(IADC_TypeDef *iadc,
1056 const IADC_SingleInput_t *input);
1057 uint8_t IADC_calcSrcClkPrescale(IADC_TypeDef *iadc,
1058 uint32_t srcClkFreq,
1059 uint32_t cmuClkFreq);
1060 uint32_t IADC_calcAdcClkPrescale(IADC_TypeDef *iadc,
1061 uint32_t adcClkFreq,
1062 uint32_t cmuClkFreq,
1063 IADC_CfgAdcMode_t adcMode,
1064 uint8_t srcClkPrescaler);
1065 uint8_t IADC_calcTimebase(IADC_TypeDef *iadc, uint32_t srcClkFreq);
1066 IADC_Result_t IADC_readSingleResult(IADC_TypeDef *iadc);
1067 IADC_Result_t IADC_pullSingleFifoResult(IADC_TypeDef *iadc);
1068 IADC_Result_t IADC_readScanResult(IADC_TypeDef *iadc);
1069 IADC_Result_t IADC_pullScanFifoResult(IADC_TypeDef *iadc);
1070 uint32_t IADC_getReferenceVoltage(IADC_CfgReference_t reference);
1071
1072 /***************************************************************************//**
1073 * @brief
1074 * Pull data from single data FIFO. If showId was set when initializing
1075 * single mode, the results will contain the ID (0x20).
1076 *
1077 * @note
1078 * Check data valid flag before calling this function.
1079 *
1080 * @param[in] iadc
1081 * Pointer to IADC peripheral register block.
1082 *
1083 * @return
1084 * Single conversion data.
1085 ******************************************************************************/
IADC_pullSingleFifoData(IADC_TypeDef * iadc)1086 __STATIC_INLINE uint32_t IADC_pullSingleFifoData(IADC_TypeDef *iadc)
1087 {
1088 return iadc->SINGLEFIFODATA;
1089 }
1090
1091 /***************************************************************************//**
1092 * @brief
1093 * Read most recent single conversion data. If showId was set when
1094 * initializing single mode, the data will contain the ID (0x20). Calling
1095 * this function will not affect the state of the single data FIFO.
1096 *
1097 * @note
1098 * Check data valid flag before calling this function.
1099 *
1100 * @param[in] iadc
1101 * Pointer to IADC peripheral register block.
1102 *
1103 * @return
1104 * Single conversion data.
1105 ******************************************************************************/
IADC_readSingleData(IADC_TypeDef * iadc)1106 __STATIC_INLINE uint32_t IADC_readSingleData(IADC_TypeDef *iadc)
1107 {
1108 return iadc->SINGLEDATA;
1109 }
1110
1111 /***************************************************************************//**
1112 * @brief
1113 * Pull data from scan data FIFO. If showId was set for the scan entry
1114 * initialization, the data will contain the ID of the scan entry.
1115 *
1116 * @note
1117 * Check data valid flag before calling this function.
1118 *
1119 * @param[in] iadc
1120 * Pointer to IADC peripheral register block.
1121 *
1122 * @return
1123 * Scan conversion data.
1124 ******************************************************************************/
IADC_pullScanFifoData(IADC_TypeDef * iadc)1125 __STATIC_INLINE uint32_t IADC_pullScanFifoData(IADC_TypeDef *iadc)
1126 {
1127 return iadc->SCANFIFODATA;
1128 }
1129
1130 /***************************************************************************//**
1131 * @brief
1132 * Read most recent scan conversion data. If showId was set for the scan
1133 * entry initialization, the data will contain the ID of the scan entry.
1134 * Calling this function will not affect the state of the scan data FIFO.
1135 *
1136 * @note
1137 * Check data valid flag before calling this function.
1138 *
1139 * @param[in] iadc
1140 * Pointer to IADC peripheral register block.
1141 *
1142 * @return
1143 * Scan conversion data.
1144 ******************************************************************************/
IADC_readScanData(IADC_TypeDef * iadc)1145 __STATIC_INLINE uint32_t IADC_readScanData(IADC_TypeDef *iadc)
1146 {
1147 return iadc->SCANDATA;
1148 }
1149
1150 /***************************************************************************//**
1151 * @brief
1152 * Clear one or more pending IADC interrupts.
1153 *
1154 * @param[in] iadc
1155 * Pointer to IADC peripheral register block.
1156 *
1157 * @param[in] flags
1158 * Pending IADC interrupt source to clear. Use a bitwise logic OR combination
1159 * of valid interrupt flags for the IADC module (IADC_IF_nnn).
1160 ******************************************************************************/
IADC_clearInt(IADC_TypeDef * iadc,uint32_t flags)1161 __STATIC_INLINE void IADC_clearInt(IADC_TypeDef *iadc, uint32_t flags)
1162 {
1163 iadc->IF_CLR = flags;
1164 }
1165
1166 /***************************************************************************//**
1167 * @brief
1168 * Disable one or more IADC interrupts.
1169 *
1170 * @param[in] iadc
1171 * Pointer to IADC peripheral register block.
1172 *
1173 * @param[in] flags
1174 * IADC interrupt sources to disable. Use a bitwise logic OR combination of
1175 * valid interrupt flags for the IADC module (IADC_IF_nnn).
1176 ******************************************************************************/
IADC_disableInt(IADC_TypeDef * iadc,uint32_t flags)1177 __STATIC_INLINE void IADC_disableInt(IADC_TypeDef *iadc, uint32_t flags)
1178 {
1179 #if defined (IADC_HAS_SET_CLEAR)
1180 iadc->IEN_CLR = flags;
1181 #else
1182 iadc->IEN &= ~flags;
1183 #endif
1184 }
1185
1186 /***************************************************************************//**
1187 * @brief
1188 * Enable one or more IADC interrupts.
1189 *
1190 * @note
1191 * Depending on the use, a pending interrupt may already be set prior to
1192 * enabling the interrupt. Consider using IADC_intClear() prior to enabling
1193 * if such a pending interrupt should be ignored.
1194 *
1195 * @param[in] iadc
1196 * Pointer to IADC peripheral register block.
1197 *
1198 * @param[in] flags
1199 * IADC interrupt sources to enable. Use a bitwise logic OR combination of
1200 * valid interrupt flags for the IADC module (IADC_IF_nnn).
1201 ******************************************************************************/
IADC_enableInt(IADC_TypeDef * iadc,uint32_t flags)1202 __STATIC_INLINE void IADC_enableInt(IADC_TypeDef *iadc, uint32_t flags)
1203 {
1204 iadc->IEN |= flags;
1205 }
1206
1207 /***************************************************************************//**
1208 * @brief
1209 * Get pending IADC interrupt flags.
1210 *
1211 * @note
1212 * The event bits are not cleared by the use of this function.
1213 *
1214 * @param[in] iadc
1215 * Pointer to IADC peripheral register block.
1216 *
1217 * @return
1218 * IADC interrupt sources pending. A bitwise logic OR combination of valid
1219 * interrupt flags for the IADC module (IADC_IF_nnn).
1220 ******************************************************************************/
IADC_getInt(IADC_TypeDef * iadc)1221 __STATIC_INLINE uint32_t IADC_getInt(IADC_TypeDef *iadc)
1222 {
1223 return iadc->IF;
1224 }
1225
1226 /***************************************************************************//**
1227 * @brief
1228 * Get enabled and pending IADC interrupt flags.
1229 * Useful for handling more interrupt sources in the same interrupt handler.
1230 *
1231 * @note
1232 * Interrupt flags are not cleared by the use of this function.
1233 *
1234 * @param[in] iadc
1235 * Pointer to IADC peripheral register block.
1236 *
1237 * @return
1238 * Pending and enabled IADC interrupt sources.
1239 * The return value is the bitwise AND combination of
1240 * - the OR combination of enabled interrupt sources in IADCx_IEN_nnn
1241 * register (IADCx_IEN_nnn) and
1242 * - the OR combination of valid interrupt flags of the IADC module
1243 * (IADCx_IF_nnn).
1244 ******************************************************************************/
IADC_getEnabledInt(IADC_TypeDef * iadc)1245 __STATIC_INLINE uint32_t IADC_getEnabledInt(IADC_TypeDef *iadc)
1246 {
1247 uint32_t ien;
1248
1249 /* Store IADCx->IEN in temporary variable in order to define explicit order
1250 * of volatile accesses. */
1251 ien = iadc->IEN;
1252
1253 /* Bitwise AND of pending and enabled interrupts */
1254 return iadc->IF & ien;
1255 }
1256
1257 /***************************************************************************//**
1258 * @brief
1259 * Set one or more pending IADC interrupts from SW.
1260 *
1261 * @param[in] iadc
1262 * Pointer to IADC peripheral register block.
1263 *
1264 * @param[in] flags
1265 * IADC interrupt sources to set to pending. Use a bitwise logic OR combination
1266 * of valid interrupt flags for the IADC module (IADC_IF_nnn).
1267 ******************************************************************************/
IADC_setInt(IADC_TypeDef * iadc,uint32_t flags)1268 __STATIC_INLINE void IADC_setInt(IADC_TypeDef *iadc, uint32_t flags)
1269 {
1270 iadc->IF_SET = flags;
1271 }
1272
1273 /***************************************************************************//**
1274 * @brief
1275 * Start/stop scan sequence, single conversion and/or timer.
1276 *
1277 * @param[in] iadc
1278 * Pointer to IADC peripheral register block.
1279 *
1280 * @param[in] cmd
1281 * Command to be performed.
1282 ******************************************************************************/
IADC_command(IADC_TypeDef * iadc,IADC_Cmd_t cmd)1283 __STATIC_INLINE void IADC_command(IADC_TypeDef *iadc, IADC_Cmd_t cmd)
1284 {
1285 iadc->CMD = (uint32_t)cmd;
1286 }
1287
1288 /***************************************************************************//**
1289 * @brief
1290 * Get the scan mask currently used in the IADC.
1291 *
1292 * @param[in] iadc
1293 * Pointer to IADC peripheral register block.
1294 *
1295 * @return
1296 * Mask of scan table entries currently included in scan.
1297 ******************************************************************************/
IADC_getScanMask(IADC_TypeDef * iadc)1298 __STATIC_INLINE uint32_t IADC_getScanMask(IADC_TypeDef *iadc)
1299 {
1300 return (iadc->STMASK) >> _IADC_STMASK_STMASK_SHIFT;
1301 }
1302
1303 /***************************************************************************//**
1304 * @brief
1305 * Get status bits of IADC.
1306 *
1307 * @param[in] iadc
1308 * Pointer to IADC peripheral register block.
1309 *
1310 * @return
1311 * IADC status bits
1312 ******************************************************************************/
IADC_getStatus(IADC_TypeDef * iadc)1313 __STATIC_INLINE uint32_t IADC_getStatus(IADC_TypeDef *iadc)
1314 {
1315 return iadc->STATUS;
1316 }
1317
1318 /***************************************************************************//**
1319 * @brief
1320 * Get the number of elements in the IADC single FIFO.
1321 *
1322 * @param[in] iadc
1323 * Pointer to IADC peripheral register block.
1324 *
1325 * @return
1326 * Number of elements in single FIFO
1327 ******************************************************************************/
IADC_getSingleFifoCnt(IADC_TypeDef * iadc)1328 __STATIC_INLINE uint8_t IADC_getSingleFifoCnt(IADC_TypeDef *iadc)
1329 {
1330 return (uint8_t) ((iadc->SINGLEFIFOSTAT & _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK)
1331 >> _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT);
1332 }
1333
1334 /***************************************************************************//**
1335 * @brief
1336 * Get the number of elements in the IADC scan FIFO.
1337 *
1338 * @param[in] iadc
1339 * Pointer to IADC peripheral register block.
1340 *
1341 * @return
1342 * Number of elements in scan FIFO
1343 ******************************************************************************/
IADC_getScanFifoCnt(IADC_TypeDef * iadc)1344 __STATIC_INLINE uint8_t IADC_getScanFifoCnt(IADC_TypeDef *iadc)
1345 {
1346 return (uint8_t) ((iadc->SCANFIFOSTAT & _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK)
1347 >> _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT);
1348 }
1349
1350 /***************************************************************************//**
1351 * @brief
1352 * Convert the GPIO port/pin to IADC negative input selection.
1353 *
1354 * @param[in] port
1355 * GPIO port
1356 *
1357 * @param[in] pin
1358 * GPIO in
1359 *
1360 * @return
1361 * IADC negative input selection
1362 ******************************************************************************/
IADC_portPinToNegInput(GPIO_Port_TypeDef port,uint8_t pin)1363 __STATIC_INLINE IADC_NegInput_t IADC_portPinToNegInput(GPIO_Port_TypeDef port,
1364 uint8_t pin)
1365 {
1366 uint32_t input = (((uint32_t) port + _IADC_SCAN_PORTNEG_PORTA) << 4) | pin;
1367
1368 return (IADC_NegInput_t) input;
1369 }
1370
1371 /***************************************************************************//**
1372 * @brief
1373 * Convert the GPIO port/pin to IADC positive input selection.
1374 *
1375 * @param[in] port
1376 * GPIO port
1377 *
1378 * @param[in] pin
1379 * GPIO in
1380 *
1381 * @return
1382 * IADC positive input selection
1383 ******************************************************************************/
IADC_portPinToPosInput(GPIO_Port_TypeDef port,uint8_t pin)1384 __STATIC_INLINE IADC_PosInput_t IADC_portPinToPosInput(GPIO_Port_TypeDef port,
1385 uint8_t pin)
1386 {
1387 uint32_t input = (((uint32_t) port + _IADC_SCAN_PORTPOS_PORTA) << 4) | pin;
1388
1389 return (IADC_PosInput_t) input;
1390 }
1391
1392 /** @} (end addtogroup iadc) */
1393
1394 #ifdef __cplusplus
1395 }
1396 #endif
1397
1398 #endif /* defined(IADC_COUNT) && (IADC_COUNT > 0) */
1399 #endif /* EM_IADC_H */
1400
