1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG22 SMU register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG22_SMU_H 31 #define EFR32BG22_SMU_H 32 #define SMU_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG22_SMU SMU 40 * @{ 41 * @brief EFR32BG22 SMU Register Declaration. 42 *****************************************************************************/ 43 44 /** SMU Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP Version */ 47 __IM uint32_t STATUS; /**< Status */ 48 __IOM uint32_t LOCK; /**< Lock */ 49 __IOM uint32_t IF; /**< Interrupt Flag */ 50 __IOM uint32_t IEN; /**< Interrupt Enable */ 51 uint32_t RESERVED0[3U]; /**< Reserved for future use */ 52 __IOM uint32_t M33CTRL; /**< M33 Control */ 53 uint32_t RESERVED1[7U]; /**< Reserved for future use */ 54 __IOM uint32_t PPUPATD0; /**< PPU PATD Register 0 */ 55 __IOM uint32_t PPUPATD1; /**< PPU PATD Register 1 */ 56 uint32_t RESERVED2[6U]; /**< Reserved for future use */ 57 __IOM uint32_t PPUSATD0; /**< PPU SATD Register 0 */ 58 __IOM uint32_t PPUSATD1; /**< PPU SATD Register 1 */ 59 uint32_t RESERVED3[54U]; /**< Reserved for future use */ 60 __IM uint32_t PPUFS; /**< PPU Fault Status */ 61 uint32_t RESERVED4[3U]; /**< Reserved for future use */ 62 __IOM uint32_t BMPUPATD0; /**< BMPU PATD Register 0 */ 63 uint32_t RESERVED5[7U]; /**< Reserved for future use */ 64 __IOM uint32_t BMPUSATD0; /**< BMPU SATD Register 0 */ 65 uint32_t RESERVED6[55U]; /**< Reserved for future use */ 66 __IM uint32_t BMPUFS; /**< BMPU Fault Status */ 67 __IM uint32_t BMPUFSADDR; /**< BMPU Fault Status Address */ 68 uint32_t RESERVED7[2U]; /**< Reserved for future use */ 69 __IOM uint32_t ESAURTYPES0; /**< ESAU Region Types Register 0 */ 70 __IOM uint32_t ESAURTYPES1; /**< ESAU Region Types Register 1 */ 71 uint32_t RESERVED8[2U]; /**< Reserved for future use */ 72 __IOM uint32_t ESAUMRB01; /**< ESAU Movable Region Boundary 0-1 */ 73 __IOM uint32_t ESAUMRB12; /**< ESAU Movable Region Boundary 1-2 */ 74 uint32_t RESERVED9[2U]; /**< Reserved for future use */ 75 __IOM uint32_t ESAUMRB45; /**< ESAU Movable Region Boundary 4-5 */ 76 __IOM uint32_t ESAUMRB56; /**< ESAU Movable Region Boundary 5-6 */ 77 uint32_t RESERVED10[862U]; /**< Reserved for future use */ 78 __IM uint32_t IPVERSION_SET; /**< IP Version */ 79 __IM uint32_t STATUS_SET; /**< Status */ 80 __IOM uint32_t LOCK_SET; /**< Lock */ 81 __IOM uint32_t IF_SET; /**< Interrupt Flag */ 82 __IOM uint32_t IEN_SET; /**< Interrupt Enable */ 83 uint32_t RESERVED11[3U]; /**< Reserved for future use */ 84 __IOM uint32_t M33CTRL_SET; /**< M33 Control */ 85 uint32_t RESERVED12[7U]; /**< Reserved for future use */ 86 __IOM uint32_t PPUPATD0_SET; /**< PPU PATD Register 0 */ 87 __IOM uint32_t PPUPATD1_SET; /**< PPU PATD Register 1 */ 88 uint32_t RESERVED13[6U]; /**< Reserved for future use */ 89 __IOM uint32_t PPUSATD0_SET; /**< PPU SATD Register 0 */ 90 __IOM uint32_t PPUSATD1_SET; /**< PPU SATD Register 1 */ 91 uint32_t RESERVED14[54U]; /**< Reserved for future use */ 92 __IM uint32_t PPUFS_SET; /**< PPU Fault Status */ 93 uint32_t RESERVED15[3U]; /**< Reserved for future use */ 94 __IOM uint32_t BMPUPATD0_SET; /**< BMPU PATD Register 0 */ 95 uint32_t RESERVED16[7U]; /**< Reserved for future use */ 96 __IOM uint32_t BMPUSATD0_SET; /**< BMPU SATD Register 0 */ 97 uint32_t RESERVED17[55U]; /**< Reserved for future use */ 98 __IM uint32_t BMPUFS_SET; /**< BMPU Fault Status */ 99 __IM uint32_t BMPUFSADDR_SET; /**< BMPU Fault Status Address */ 100 uint32_t RESERVED18[2U]; /**< Reserved for future use */ 101 __IOM uint32_t ESAURTYPES0_SET; /**< ESAU Region Types Register 0 */ 102 __IOM uint32_t ESAURTYPES1_SET; /**< ESAU Region Types Register 1 */ 103 uint32_t RESERVED19[2U]; /**< Reserved for future use */ 104 __IOM uint32_t ESAUMRB01_SET; /**< ESAU Movable Region Boundary 0-1 */ 105 __IOM uint32_t ESAUMRB12_SET; /**< ESAU Movable Region Boundary 1-2 */ 106 uint32_t RESERVED20[2U]; /**< Reserved for future use */ 107 __IOM uint32_t ESAUMRB45_SET; /**< ESAU Movable Region Boundary 4-5 */ 108 __IOM uint32_t ESAUMRB56_SET; /**< ESAU Movable Region Boundary 5-6 */ 109 uint32_t RESERVED21[862U]; /**< Reserved for future use */ 110 __IM uint32_t IPVERSION_CLR; /**< IP Version */ 111 __IM uint32_t STATUS_CLR; /**< Status */ 112 __IOM uint32_t LOCK_CLR; /**< Lock */ 113 __IOM uint32_t IF_CLR; /**< Interrupt Flag */ 114 __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ 115 uint32_t RESERVED22[3U]; /**< Reserved for future use */ 116 __IOM uint32_t M33CTRL_CLR; /**< M33 Control */ 117 uint32_t RESERVED23[7U]; /**< Reserved for future use */ 118 __IOM uint32_t PPUPATD0_CLR; /**< PPU PATD Register 0 */ 119 __IOM uint32_t PPUPATD1_CLR; /**< PPU PATD Register 1 */ 120 uint32_t RESERVED24[6U]; /**< Reserved for future use */ 121 __IOM uint32_t PPUSATD0_CLR; /**< PPU SATD Register 0 */ 122 __IOM uint32_t PPUSATD1_CLR; /**< PPU SATD Register 1 */ 123 uint32_t RESERVED25[54U]; /**< Reserved for future use */ 124 __IM uint32_t PPUFS_CLR; /**< PPU Fault Status */ 125 uint32_t RESERVED26[3U]; /**< Reserved for future use */ 126 __IOM uint32_t BMPUPATD0_CLR; /**< BMPU PATD Register 0 */ 127 uint32_t RESERVED27[7U]; /**< Reserved for future use */ 128 __IOM uint32_t BMPUSATD0_CLR; /**< BMPU SATD Register 0 */ 129 uint32_t RESERVED28[55U]; /**< Reserved for future use */ 130 __IM uint32_t BMPUFS_CLR; /**< BMPU Fault Status */ 131 __IM uint32_t BMPUFSADDR_CLR; /**< BMPU Fault Status Address */ 132 uint32_t RESERVED29[2U]; /**< Reserved for future use */ 133 __IOM uint32_t ESAURTYPES0_CLR; /**< ESAU Region Types Register 0 */ 134 __IOM uint32_t ESAURTYPES1_CLR; /**< ESAU Region Types Register 1 */ 135 uint32_t RESERVED30[2U]; /**< Reserved for future use */ 136 __IOM uint32_t ESAUMRB01_CLR; /**< ESAU Movable Region Boundary 0-1 */ 137 __IOM uint32_t ESAUMRB12_CLR; /**< ESAU Movable Region Boundary 1-2 */ 138 uint32_t RESERVED31[2U]; /**< Reserved for future use */ 139 __IOM uint32_t ESAUMRB45_CLR; /**< ESAU Movable Region Boundary 4-5 */ 140 __IOM uint32_t ESAUMRB56_CLR; /**< ESAU Movable Region Boundary 5-6 */ 141 uint32_t RESERVED32[862U]; /**< Reserved for future use */ 142 __IM uint32_t IPVERSION_TGL; /**< IP Version */ 143 __IM uint32_t STATUS_TGL; /**< Status */ 144 __IOM uint32_t LOCK_TGL; /**< Lock */ 145 __IOM uint32_t IF_TGL; /**< Interrupt Flag */ 146 __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ 147 uint32_t RESERVED33[3U]; /**< Reserved for future use */ 148 __IOM uint32_t M33CTRL_TGL; /**< M33 Control */ 149 uint32_t RESERVED34[7U]; /**< Reserved for future use */ 150 __IOM uint32_t PPUPATD0_TGL; /**< PPU PATD Register 0 */ 151 __IOM uint32_t PPUPATD1_TGL; /**< PPU PATD Register 1 */ 152 uint32_t RESERVED35[6U]; /**< Reserved for future use */ 153 __IOM uint32_t PPUSATD0_TGL; /**< PPU SATD Register 0 */ 154 __IOM uint32_t PPUSATD1_TGL; /**< PPU SATD Register 1 */ 155 uint32_t RESERVED36[54U]; /**< Reserved for future use */ 156 __IM uint32_t PPUFS_TGL; /**< PPU Fault Status */ 157 uint32_t RESERVED37[3U]; /**< Reserved for future use */ 158 __IOM uint32_t BMPUPATD0_TGL; /**< BMPU PATD Register 0 */ 159 uint32_t RESERVED38[7U]; /**< Reserved for future use */ 160 __IOM uint32_t BMPUSATD0_TGL; /**< BMPU SATD Register 0 */ 161 uint32_t RESERVED39[55U]; /**< Reserved for future use */ 162 __IM uint32_t BMPUFS_TGL; /**< BMPU Fault Status */ 163 __IM uint32_t BMPUFSADDR_TGL; /**< BMPU Fault Status Address */ 164 uint32_t RESERVED40[2U]; /**< Reserved for future use */ 165 __IOM uint32_t ESAURTYPES0_TGL; /**< ESAU Region Types Register 0 */ 166 __IOM uint32_t ESAURTYPES1_TGL; /**< ESAU Region Types Register 1 */ 167 uint32_t RESERVED41[2U]; /**< Reserved for future use */ 168 __IOM uint32_t ESAUMRB01_TGL; /**< ESAU Movable Region Boundary 0-1 */ 169 __IOM uint32_t ESAUMRB12_TGL; /**< ESAU Movable Region Boundary 1-2 */ 170 uint32_t RESERVED42[2U]; /**< Reserved for future use */ 171 __IOM uint32_t ESAUMRB45_TGL; /**< ESAU Movable Region Boundary 4-5 */ 172 __IOM uint32_t ESAUMRB56_TGL; /**< ESAU Movable Region Boundary 5-6 */ 173 } SMU_TypeDef; 174 /** @} End of group EFR32BG22_SMU */ 175 176 /**************************************************************************//** 177 * @addtogroup EFR32BG22_SMU 178 * @{ 179 * @defgroup EFR32BG22_SMU_BitFields SMU Bit Fields 180 * @{ 181 *****************************************************************************/ 182 183 /* Bit fields for SMU IPVERSION */ 184 #define _SMU_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SMU_IPVERSION */ 185 #define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ 186 #define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ 187 #define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ 188 #define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_IPVERSION */ 189 #define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ 190 191 /* Bit fields for SMU STATUS */ 192 #define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ 193 #define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ 194 #define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ 195 #define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ 196 #define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ 197 #define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ 198 #define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ 199 #define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ 200 #define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ 201 #define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ 202 #define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ 203 #define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ 204 #define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ 205 #define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ 206 #define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ 207 #define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ 208 209 /* Bit fields for SMU LOCK */ 210 #define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ 211 #define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ 212 #define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ 213 #define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ 214 #define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ 215 #define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ 216 #define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ 217 #define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ 218 219 /* Bit fields for SMU IF */ 220 #define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ 221 #define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ 222 #define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ 223 #define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ 224 #define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ 225 #define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ 226 #define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ 227 #define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ 228 #define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ 229 #define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ 230 #define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ 231 #define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ 232 #define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ 233 #define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ 234 #define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ 235 #define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ 236 #define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ 237 #define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ 238 #define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ 239 #define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ 240 #define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ 241 #define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ 242 243 /* Bit fields for SMU IEN */ 244 #define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ 245 #define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ 246 #define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ 247 #define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ 248 #define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ 249 #define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ 250 #define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ 251 #define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ 252 #define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ 253 #define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ 254 #define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ 255 #define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ 256 #define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ 257 #define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ 258 #define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ 259 #define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ 260 #define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ 261 #define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ 262 #define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ 263 #define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ 264 #define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ 265 #define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ 266 267 /* Bit fields for SMU M33CTRL */ 268 #define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ 269 #define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ 270 #define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< LOCKSVTAIRCR control of M33 CPU */ 271 #define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ 272 #define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ 273 #define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ 274 #define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ 275 #define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< LOCKNSVTOR control of M33 CPU */ 276 #define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ 277 #define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ 278 #define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ 279 #define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ 280 #define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< LOCKSMPU control of M33 CPU */ 281 #define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ 282 #define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ 283 #define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ 284 #define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ 285 #define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< LOCKNSMPU control of M33 CPU */ 286 #define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ 287 #define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ 288 #define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ 289 #define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ 290 #define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< LOCKSAU control of M33 CPU */ 291 #define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ 292 #define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ 293 #define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ 294 #define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ 295 296 /* Bit fields for SMU PPUPATD0 */ 297 #define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ 298 #define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ 299 #define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ 300 #define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ 301 #define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ 302 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 303 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 304 #define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ 305 #define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ 306 #define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ 307 #define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 308 #define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 309 #define SMU_PPUPATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Privileged Access */ 310 #define _SMU_PPUPATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ 311 #define _SMU_PPUPATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ 312 #define _SMU_PPUPATD0_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 313 #define SMU_PPUPATD0_HFXO0_DEFAULT (_SMU_PPUPATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 314 #define SMU_PPUPATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Privileged Access */ 315 #define _SMU_PPUPATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ 316 #define _SMU_PPUPATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ 317 #define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 318 #define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 319 #define SMU_PPUPATD0_FSRCO (0x1UL << 5) /**< FSRCO Privileged Access */ 320 #define _SMU_PPUPATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ 321 #define _SMU_PPUPATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ 322 #define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 323 #define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 324 #define SMU_PPUPATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Privileged Access */ 325 #define _SMU_PPUPATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ 326 #define _SMU_PPUPATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ 327 #define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 328 #define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 329 #define SMU_PPUPATD0_LFXO (0x1UL << 7) /**< LFXO Privileged Access */ 330 #define _SMU_PPUPATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ 331 #define _SMU_PPUPATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ 332 #define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 333 #define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 334 #define SMU_PPUPATD0_LFRCO (0x1UL << 8) /**< LFRCO Privileged Access */ 335 #define _SMU_PPUPATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ 336 #define _SMU_PPUPATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ 337 #define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 338 #define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 339 #define SMU_PPUPATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Privileged Access */ 340 #define _SMU_PPUPATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ 341 #define _SMU_PPUPATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ 342 #define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 343 #define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 344 #define SMU_PPUPATD0_MSC (0x1UL << 10) /**< MSC Privileged Access */ 345 #define _SMU_PPUPATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ 346 #define _SMU_PPUPATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ 347 #define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 348 #define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 349 #define SMU_PPUPATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Privileged Access */ 350 #define _SMU_PPUPATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ 351 #define _SMU_PPUPATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ 352 #define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 353 #define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 354 #define SMU_PPUPATD0_PRS (0x1UL << 12) /**< PRS Privileged Access */ 355 #define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ 356 #define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ 357 #define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 358 #define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 359 #define SMU_PPUPATD0_GPIO (0x1UL << 13) /**< GPIO Privileged Access */ 360 #define _SMU_PPUPATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ 361 #define _SMU_PPUPATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ 362 #define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 363 #define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 364 #define SMU_PPUPATD0_LDMA (0x1UL << 14) /**< LDMA Privileged Access */ 365 #define _SMU_PPUPATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ 366 #define _SMU_PPUPATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ 367 #define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 368 #define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 369 #define SMU_PPUPATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Privileged Access */ 370 #define _SMU_PPUPATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ 371 #define _SMU_PPUPATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ 372 #define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 373 #define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 374 #define SMU_PPUPATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Privileged Access */ 375 #define _SMU_PPUPATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ 376 #define _SMU_PPUPATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ 377 #define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 378 #define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 379 #define SMU_PPUPATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Privileged Access */ 380 #define _SMU_PPUPATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ 381 #define _SMU_PPUPATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ 382 #define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 383 #define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 384 #define SMU_PPUPATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Privileged Access */ 385 #define _SMU_PPUPATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ 386 #define _SMU_PPUPATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ 387 #define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 388 #define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 389 #define SMU_PPUPATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Privileged Access */ 390 #define _SMU_PPUPATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ 391 #define _SMU_PPUPATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ 392 #define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 393 #define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 394 #define SMU_PPUPATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Privileged Access */ 395 #define _SMU_PPUPATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ 396 #define _SMU_PPUPATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ 397 #define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 398 #define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 399 #define SMU_PPUPATD0_USART0 (0x1UL << 21) /**< USART0 Privileged Access */ 400 #define _SMU_PPUPATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ 401 #define _SMU_PPUPATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ 402 #define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 403 #define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 404 #define SMU_PPUPATD0_USART1 (0x1UL << 22) /**< USART1 Privileged Access */ 405 #define _SMU_PPUPATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ 406 #define _SMU_PPUPATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ 407 #define _SMU_PPUPATD0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 408 #define SMU_PPUPATD0_USART1_DEFAULT (_SMU_PPUPATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 409 #define SMU_PPUPATD0_BURTC (0x1UL << 23) /**< BURTC Privileged Access */ 410 #define _SMU_PPUPATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ 411 #define _SMU_PPUPATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ 412 #define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 413 #define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 414 #define SMU_PPUPATD0_I2C1 (0x1UL << 24) /**< I2C1 Privileged Access */ 415 #define _SMU_PPUPATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ 416 #define _SMU_PPUPATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ 417 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 418 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 419 #define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Privileged Access */ 420 #define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ 421 #define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ 422 #define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 423 #define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 424 #define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Privileged Access */ 425 #define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ 426 #define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ 427 #define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 428 #define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 429 #define SMU_PPUPATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Privileged Access */ 430 #define _SMU_PPUPATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ 431 #define _SMU_PPUPATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ 432 #define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 433 #define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 434 #define SMU_PPUPATD0_BURAM (0x1UL << 28) /**< BURAM Privileged Access */ 435 #define _SMU_PPUPATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ 436 #define _SMU_PPUPATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ 437 #define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 438 #define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 439 #define SMU_PPUPATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Privileged Access */ 440 #define _SMU_PPUPATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ 441 #define _SMU_PPUPATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ 442 #define _SMU_PPUPATD0_IFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 443 #define SMU_PPUPATD0_IFADCDEBUG_DEFAULT (_SMU_PPUPATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 444 #define SMU_PPUPATD0_GPCRC (0x1UL << 30) /**< GPCRC Privileged Access */ 445 #define _SMU_PPUPATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ 446 #define _SMU_PPUPATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ 447 #define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 448 #define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 449 #define SMU_PPUPATD0_DCI (0x1UL << 31) /**< DCI Privileged Access */ 450 #define _SMU_PPUPATD0_DCI_SHIFT 31 /**< Shift value for SMU_DCI */ 451 #define _SMU_PPUPATD0_DCI_MASK 0x80000000UL /**< Bit mask for SMU_DCI */ 452 #define _SMU_PPUPATD0_DCI_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 453 #define SMU_PPUPATD0_DCI_DEFAULT (_SMU_PPUPATD0_DCI_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 454 455 /* Bit fields for SMU PPUPATD1 */ 456 #define _SMU_PPUPATD1_RESETVALUE 0x0000FFFFUL /**< Default value for SMU_PPUPATD1 */ 457 #define _SMU_PPUPATD1_MASK 0x0000FFFFUL /**< Mask for SMU_PPUPATD1 */ 458 #define SMU_PPUPATD1_DCDC (0x1UL << 1) /**< DCDC Privileged Access */ 459 #define _SMU_PPUPATD1_DCDC_SHIFT 1 /**< Shift value for SMU_DCDC */ 460 #define _SMU_PPUPATD1_DCDC_MASK 0x2UL /**< Bit mask for SMU_DCDC */ 461 #define _SMU_PPUPATD1_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 462 #define SMU_PPUPATD1_DCDC_DEFAULT (_SMU_PPUPATD1_DCDC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 463 #define SMU_PPUPATD1_PDM (0x1UL << 2) /**< PDM Privileged Access */ 464 #define _SMU_PPUPATD1_PDM_SHIFT 2 /**< Shift value for SMU_PDM */ 465 #define _SMU_PPUPATD1_PDM_MASK 0x4UL /**< Bit mask for SMU_PDM */ 466 #define _SMU_PPUPATD1_PDM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 467 #define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 468 #define SMU_PPUPATD1_RFSENSE (0x1UL << 3) /**< RFSENSE Privileged Access */ 469 #define _SMU_PPUPATD1_RFSENSE_SHIFT 3 /**< Shift value for SMU_RFSENSE */ 470 #define _SMU_PPUPATD1_RFSENSE_MASK 0x8UL /**< Bit mask for SMU_RFSENSE */ 471 #define _SMU_PPUPATD1_RFSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 472 #define SMU_PPUPATD1_RFSENSE_DEFAULT (_SMU_PPUPATD1_RFSENSE_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 473 #define SMU_PPUPATD1_RADIOAES (0x1UL << 4) /**< RADIOAES Privileged Access */ 474 #define _SMU_PPUPATD1_RADIOAES_SHIFT 4 /**< Shift value for SMU_RADIOAES */ 475 #define _SMU_PPUPATD1_RADIOAES_MASK 0x10UL /**< Bit mask for SMU_RADIOAES */ 476 #define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 477 #define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 478 #define SMU_PPUPATD1_SMU (0x1UL << 5) /**< SMU Privileged Access */ 479 #define _SMU_PPUPATD1_SMU_SHIFT 5 /**< Shift value for SMU_SMU */ 480 #define _SMU_PPUPATD1_SMU_MASK 0x20UL /**< Bit mask for SMU_SMU */ 481 #define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 482 #define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 483 #define SMU_PPUPATD1_SMUCFGNS (0x1UL << 6) /**< SMUCFGNS Privileged Access */ 484 #define _SMU_PPUPATD1_SMUCFGNS_SHIFT 6 /**< Shift value for SMU_SMUCFGNS */ 485 #define _SMU_PPUPATD1_SMUCFGNS_MASK 0x40UL /**< Bit mask for SMU_SMUCFGNS */ 486 #define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 487 #define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 488 #define SMU_PPUPATD1_RTCC (0x1UL << 7) /**< RTCC Privileged Access */ 489 #define _SMU_PPUPATD1_RTCC_SHIFT 7 /**< Shift value for SMU_RTCC */ 490 #define _SMU_PPUPATD1_RTCC_MASK 0x80UL /**< Bit mask for SMU_RTCC */ 491 #define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 492 #define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 493 #define SMU_PPUPATD1_LETIMER0 (0x1UL << 8) /**< LETIMER0 Privileged Access */ 494 #define _SMU_PPUPATD1_LETIMER0_SHIFT 8 /**< Shift value for SMU_LETIMER0 */ 495 #define _SMU_PPUPATD1_LETIMER0_MASK 0x100UL /**< Bit mask for SMU_LETIMER0 */ 496 #define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 497 #define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 498 #define SMU_PPUPATD1_IADC0 (0x1UL << 9) /**< IADC0 Privileged Access */ 499 #define _SMU_PPUPATD1_IADC0_SHIFT 9 /**< Shift value for SMU_IADC0 */ 500 #define _SMU_PPUPATD1_IADC0_MASK 0x200UL /**< Bit mask for SMU_IADC0 */ 501 #define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 502 #define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 503 #define SMU_PPUPATD1_I2C0 (0x1UL << 10) /**< I2C0 Privileged Access */ 504 #define _SMU_PPUPATD1_I2C0_SHIFT 10 /**< Shift value for SMU_I2C0 */ 505 #define _SMU_PPUPATD1_I2C0_MASK 0x400UL /**< Bit mask for SMU_I2C0 */ 506 #define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 507 #define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 508 #define SMU_PPUPATD1_WDOG0 (0x1UL << 11) /**< WDOG0 Privileged Access */ 509 #define _SMU_PPUPATD1_WDOG0_SHIFT 11 /**< Shift value for SMU_WDOG0 */ 510 #define _SMU_PPUPATD1_WDOG0_MASK 0x800UL /**< Bit mask for SMU_WDOG0 */ 511 #define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 512 #define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 513 #define SMU_PPUPATD1_AMUXCP0 (0x1UL << 12) /**< AMUXCP0 Privileged Access */ 514 #define _SMU_PPUPATD1_AMUXCP0_SHIFT 12 /**< Shift value for SMU_AMUXCP0 */ 515 #define _SMU_PPUPATD1_AMUXCP0_MASK 0x1000UL /**< Bit mask for SMU_AMUXCP0 */ 516 #define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 517 #define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 518 #define SMU_PPUPATD1_EUART0 (0x1UL << 13) /**< EUART0 Privileged Access */ 519 #define _SMU_PPUPATD1_EUART0_SHIFT 13 /**< Shift value for SMU_EUART0 */ 520 #define _SMU_PPUPATD1_EUART0_MASK 0x2000UL /**< Bit mask for SMU_EUART0 */ 521 #define _SMU_PPUPATD1_EUART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 522 #define SMU_PPUPATD1_EUART0_DEFAULT (_SMU_PPUPATD1_EUART0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 523 #define SMU_PPUPATD1_CRYPTOACC (0x1UL << 14) /**< CRYPTOACC Privileged Access */ 524 #define _SMU_PPUPATD1_CRYPTOACC_SHIFT 14 /**< Shift value for SMU_CRYPTOACC */ 525 #define _SMU_PPUPATD1_CRYPTOACC_MASK 0x4000UL /**< Bit mask for SMU_CRYPTOACC */ 526 #define _SMU_PPUPATD1_CRYPTOACC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 527 #define SMU_PPUPATD1_CRYPTOACC_DEFAULT (_SMU_PPUPATD1_CRYPTOACC_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 528 #define SMU_PPUPATD1_AHBRADIO (0x1UL << 15) /**< AHBRADIO Privileged Access */ 529 #define _SMU_PPUPATD1_AHBRADIO_SHIFT 15 /**< Shift value for SMU_AHBRADIO */ 530 #define _SMU_PPUPATD1_AHBRADIO_MASK 0x8000UL /**< Bit mask for SMU_AHBRADIO */ 531 #define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 532 #define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 533 534 /* Bit fields for SMU PPUSATD0 */ 535 #define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ 536 #define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ 537 #define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ 538 #define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ 539 #define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ 540 #define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 541 #define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 542 #define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ 543 #define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ 544 #define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ 545 #define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 546 #define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 547 #define SMU_PPUSATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Secure Access */ 548 #define _SMU_PPUSATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ 549 #define _SMU_PPUSATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ 550 #define _SMU_PPUSATD0_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 551 #define SMU_PPUSATD0_HFXO0_DEFAULT (_SMU_PPUSATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 552 #define SMU_PPUSATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Secure Access */ 553 #define _SMU_PPUSATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ 554 #define _SMU_PPUSATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ 555 #define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 556 #define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 557 #define SMU_PPUSATD0_FSRCO (0x1UL << 5) /**< FSRCO Secure Access */ 558 #define _SMU_PPUSATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ 559 #define _SMU_PPUSATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ 560 #define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 561 #define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 562 #define SMU_PPUSATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Secure Access */ 563 #define _SMU_PPUSATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ 564 #define _SMU_PPUSATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ 565 #define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 566 #define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 567 #define SMU_PPUSATD0_LFXO (0x1UL << 7) /**< LFXO Secure Access */ 568 #define _SMU_PPUSATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ 569 #define _SMU_PPUSATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ 570 #define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 571 #define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 572 #define SMU_PPUSATD0_LFRCO (0x1UL << 8) /**< LFRCO Secure Access */ 573 #define _SMU_PPUSATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ 574 #define _SMU_PPUSATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ 575 #define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 576 #define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 577 #define SMU_PPUSATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Secure Access */ 578 #define _SMU_PPUSATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ 579 #define _SMU_PPUSATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ 580 #define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 581 #define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 582 #define SMU_PPUSATD0_MSC (0x1UL << 10) /**< MSC Secure Access */ 583 #define _SMU_PPUSATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ 584 #define _SMU_PPUSATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ 585 #define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 586 #define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 587 #define SMU_PPUSATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Secure Access */ 588 #define _SMU_PPUSATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ 589 #define _SMU_PPUSATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ 590 #define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 591 #define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 592 #define SMU_PPUSATD0_PRS (0x1UL << 12) /**< PRS Secure Access */ 593 #define _SMU_PPUSATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ 594 #define _SMU_PPUSATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ 595 #define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 596 #define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 597 #define SMU_PPUSATD0_GPIO (0x1UL << 13) /**< GPIO Secure Access */ 598 #define _SMU_PPUSATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ 599 #define _SMU_PPUSATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ 600 #define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 601 #define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 602 #define SMU_PPUSATD0_LDMA (0x1UL << 14) /**< LDMA Secure Access */ 603 #define _SMU_PPUSATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ 604 #define _SMU_PPUSATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ 605 #define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 606 #define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 607 #define SMU_PPUSATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Secure Access */ 608 #define _SMU_PPUSATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ 609 #define _SMU_PPUSATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ 610 #define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 611 #define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 612 #define SMU_PPUSATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Secure Access */ 613 #define _SMU_PPUSATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ 614 #define _SMU_PPUSATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ 615 #define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 616 #define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 617 #define SMU_PPUSATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Secure Access */ 618 #define _SMU_PPUSATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ 619 #define _SMU_PPUSATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ 620 #define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 621 #define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 622 #define SMU_PPUSATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Secure Access */ 623 #define _SMU_PPUSATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ 624 #define _SMU_PPUSATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ 625 #define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 626 #define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 627 #define SMU_PPUSATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Secure Access */ 628 #define _SMU_PPUSATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ 629 #define _SMU_PPUSATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ 630 #define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 631 #define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 632 #define SMU_PPUSATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Secure Access */ 633 #define _SMU_PPUSATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ 634 #define _SMU_PPUSATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ 635 #define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 636 #define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 637 #define SMU_PPUSATD0_USART0 (0x1UL << 21) /**< USART0 Secure Access */ 638 #define _SMU_PPUSATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ 639 #define _SMU_PPUSATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ 640 #define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 641 #define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 642 #define SMU_PPUSATD0_USART1 (0x1UL << 22) /**< USART1 Secure Access */ 643 #define _SMU_PPUSATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ 644 #define _SMU_PPUSATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ 645 #define _SMU_PPUSATD0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 646 #define SMU_PPUSATD0_USART1_DEFAULT (_SMU_PPUSATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 647 #define SMU_PPUSATD0_BURTC (0x1UL << 23) /**< BURTC Secure Access */ 648 #define _SMU_PPUSATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ 649 #define _SMU_PPUSATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ 650 #define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 651 #define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 652 #define SMU_PPUSATD0_I2C1 (0x1UL << 24) /**< I2C1 Secure Access */ 653 #define _SMU_PPUSATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ 654 #define _SMU_PPUSATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ 655 #define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 656 #define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 657 #define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Secure Access */ 658 #define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ 659 #define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ 660 #define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 661 #define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 662 #define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Secure Access */ 663 #define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ 664 #define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ 665 #define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 666 #define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 667 #define SMU_PPUSATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Secure Access */ 668 #define _SMU_PPUSATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ 669 #define _SMU_PPUSATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ 670 #define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 671 #define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 672 #define SMU_PPUSATD0_BURAM (0x1UL << 28) /**< BURAM Secure Access */ 673 #define _SMU_PPUSATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ 674 #define _SMU_PPUSATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ 675 #define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 676 #define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 677 #define SMU_PPUSATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Secure Access */ 678 #define _SMU_PPUSATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ 679 #define _SMU_PPUSATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ 680 #define _SMU_PPUSATD0_IFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 681 #define SMU_PPUSATD0_IFADCDEBUG_DEFAULT (_SMU_PPUSATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 682 #define SMU_PPUSATD0_GPCRC (0x1UL << 30) /**< GPCRC Secure Access */ 683 #define _SMU_PPUSATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ 684 #define _SMU_PPUSATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ 685 #define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 686 #define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 687 #define SMU_PPUSATD0_DCI (0x1UL << 31) /**< DCI Secure Access */ 688 #define _SMU_PPUSATD0_DCI_SHIFT 31 /**< Shift value for SMU_DCI */ 689 #define _SMU_PPUSATD0_DCI_MASK 0x80000000UL /**< Bit mask for SMU_DCI */ 690 #define _SMU_PPUSATD0_DCI_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ 691 #define SMU_PPUSATD0_DCI_DEFAULT (_SMU_PPUSATD0_DCI_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ 692 693 /* Bit fields for SMU PPUSATD1 */ 694 #define _SMU_PPUSATD1_RESETVALUE 0x0000FFFFUL /**< Default value for SMU_PPUSATD1 */ 695 #define _SMU_PPUSATD1_MASK 0x0000FFFFUL /**< Mask for SMU_PPUSATD1 */ 696 #define SMU_PPUSATD1_DCDC (0x1UL << 1) /**< DCDC Secure Access */ 697 #define _SMU_PPUSATD1_DCDC_SHIFT 1 /**< Shift value for SMU_DCDC */ 698 #define _SMU_PPUSATD1_DCDC_MASK 0x2UL /**< Bit mask for SMU_DCDC */ 699 #define _SMU_PPUSATD1_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 700 #define SMU_PPUSATD1_DCDC_DEFAULT (_SMU_PPUSATD1_DCDC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 701 #define SMU_PPUSATD1_PDM (0x1UL << 2) /**< PDM Secure Access */ 702 #define _SMU_PPUSATD1_PDM_SHIFT 2 /**< Shift value for SMU_PDM */ 703 #define _SMU_PPUSATD1_PDM_MASK 0x4UL /**< Bit mask for SMU_PDM */ 704 #define _SMU_PPUSATD1_PDM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 705 #define SMU_PPUSATD1_PDM_DEFAULT (_SMU_PPUSATD1_PDM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 706 #define SMU_PPUSATD1_RFSENSE (0x1UL << 3) /**< RFSENSE Secure Access */ 707 #define _SMU_PPUSATD1_RFSENSE_SHIFT 3 /**< Shift value for SMU_RFSENSE */ 708 #define _SMU_PPUSATD1_RFSENSE_MASK 0x8UL /**< Bit mask for SMU_RFSENSE */ 709 #define _SMU_PPUSATD1_RFSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 710 #define SMU_PPUSATD1_RFSENSE_DEFAULT (_SMU_PPUSATD1_RFSENSE_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 711 #define SMU_PPUSATD1_RADIOAES (0x1UL << 4) /**< RADIOAES Secure Access */ 712 #define _SMU_PPUSATD1_RADIOAES_SHIFT 4 /**< Shift value for SMU_RADIOAES */ 713 #define _SMU_PPUSATD1_RADIOAES_MASK 0x10UL /**< Bit mask for SMU_RADIOAES */ 714 #define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 715 #define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 716 #define SMU_PPUSATD1_SMU (0x1UL << 5) /**< SMU Secure Access */ 717 #define _SMU_PPUSATD1_SMU_SHIFT 5 /**< Shift value for SMU_SMU */ 718 #define _SMU_PPUSATD1_SMU_MASK 0x20UL /**< Bit mask for SMU_SMU */ 719 #define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 720 #define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 721 #define SMU_PPUSATD1_SMUCFGNS (0x1UL << 6) /**< SMUCFGNS Secure Access */ 722 #define _SMU_PPUSATD1_SMUCFGNS_SHIFT 6 /**< Shift value for SMU_SMUCFGNS */ 723 #define _SMU_PPUSATD1_SMUCFGNS_MASK 0x40UL /**< Bit mask for SMU_SMUCFGNS */ 724 #define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 725 #define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 726 #define SMU_PPUSATD1_RTCC (0x1UL << 7) /**< RTCC Secure Access */ 727 #define _SMU_PPUSATD1_RTCC_SHIFT 7 /**< Shift value for SMU_RTCC */ 728 #define _SMU_PPUSATD1_RTCC_MASK 0x80UL /**< Bit mask for SMU_RTCC */ 729 #define _SMU_PPUSATD1_RTCC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 730 #define SMU_PPUSATD1_RTCC_DEFAULT (_SMU_PPUSATD1_RTCC_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 731 #define SMU_PPUSATD1_LETIMER0 (0x1UL << 8) /**< LETIMER0 Secure Access */ 732 #define _SMU_PPUSATD1_LETIMER0_SHIFT 8 /**< Shift value for SMU_LETIMER0 */ 733 #define _SMU_PPUSATD1_LETIMER0_MASK 0x100UL /**< Bit mask for SMU_LETIMER0 */ 734 #define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 735 #define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 736 #define SMU_PPUSATD1_IADC0 (0x1UL << 9) /**< IADC0 Secure Access */ 737 #define _SMU_PPUSATD1_IADC0_SHIFT 9 /**< Shift value for SMU_IADC0 */ 738 #define _SMU_PPUSATD1_IADC0_MASK 0x200UL /**< Bit mask for SMU_IADC0 */ 739 #define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 740 #define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 741 #define SMU_PPUSATD1_I2C0 (0x1UL << 10) /**< I2C0 Secure Access */ 742 #define _SMU_PPUSATD1_I2C0_SHIFT 10 /**< Shift value for SMU_I2C0 */ 743 #define _SMU_PPUSATD1_I2C0_MASK 0x400UL /**< Bit mask for SMU_I2C0 */ 744 #define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 745 #define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 746 #define SMU_PPUSATD1_WDOG0 (0x1UL << 11) /**< WDOG0 Secure Access */ 747 #define _SMU_PPUSATD1_WDOG0_SHIFT 11 /**< Shift value for SMU_WDOG0 */ 748 #define _SMU_PPUSATD1_WDOG0_MASK 0x800UL /**< Bit mask for SMU_WDOG0 */ 749 #define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 750 #define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 751 #define SMU_PPUSATD1_AMUXCP0 (0x1UL << 12) /**< AMUXCP0 Secure Access */ 752 #define _SMU_PPUSATD1_AMUXCP0_SHIFT 12 /**< Shift value for SMU_AMUXCP0 */ 753 #define _SMU_PPUSATD1_AMUXCP0_MASK 0x1000UL /**< Bit mask for SMU_AMUXCP0 */ 754 #define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 755 #define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 756 #define SMU_PPUSATD1_EUART0 (0x1UL << 13) /**< EUART0 Secure Access */ 757 #define _SMU_PPUSATD1_EUART0_SHIFT 13 /**< Shift value for SMU_EUART0 */ 758 #define _SMU_PPUSATD1_EUART0_MASK 0x2000UL /**< Bit mask for SMU_EUART0 */ 759 #define _SMU_PPUSATD1_EUART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 760 #define SMU_PPUSATD1_EUART0_DEFAULT (_SMU_PPUSATD1_EUART0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 761 #define SMU_PPUSATD1_CRYPTOACC (0x1UL << 14) /**< CRYPTOACC Secure Access */ 762 #define _SMU_PPUSATD1_CRYPTOACC_SHIFT 14 /**< Shift value for SMU_CRYPTOACC */ 763 #define _SMU_PPUSATD1_CRYPTOACC_MASK 0x4000UL /**< Bit mask for SMU_CRYPTOACC */ 764 #define _SMU_PPUSATD1_CRYPTOACC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 765 #define SMU_PPUSATD1_CRYPTOACC_DEFAULT (_SMU_PPUSATD1_CRYPTOACC_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 766 #define SMU_PPUSATD1_AHBRADIO (0x1UL << 15) /**< AHBRADIO Secure Access */ 767 #define _SMU_PPUSATD1_AHBRADIO_SHIFT 15 /**< Shift value for SMU_AHBRADIO */ 768 #define _SMU_PPUSATD1_AHBRADIO_MASK 0x8000UL /**< Bit mask for SMU_AHBRADIO */ 769 #define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ 770 #define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ 771 772 /* Bit fields for SMU PPUFS */ 773 #define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ 774 #define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ 775 #define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ 776 #define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ 777 #define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ 778 #define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ 779 780 /* Bit fields for SMU BMPUPATD0 */ 781 #define _SMU_BMPUPATD0_RESETVALUE 0x0000001FUL /**< Default value for SMU_BMPUPATD0 */ 782 #define _SMU_BMPUPATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUPATD0 */ 783 #define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ 784 #define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ 785 #define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ 786 #define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ 787 #define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ 788 #define SMU_BMPUPATD0_CRYPTOACC (0x1UL << 1) /**< CRYPTOACC DMA privileged mode */ 789 #define _SMU_BMPUPATD0_CRYPTOACC_SHIFT 1 /**< Shift value for SMU_CRYPTOACC */ 790 #define _SMU_BMPUPATD0_CRYPTOACC_MASK 0x2UL /**< Bit mask for SMU_CRYPTOACC */ 791 #define _SMU_BMPUPATD0_CRYPTOACC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ 792 #define SMU_BMPUPATD0_CRYPTOACC_DEFAULT (_SMU_BMPUPATD0_CRYPTOACC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ 793 #define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 2) /**< RADIO subsystem manager privileged mode */ 794 #define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 2 /**< Shift value for SMU_RADIOSUBSYSTEM */ 795 #define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x4UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ 796 #define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ 797 #define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ 798 #define SMU_BMPUPATD0_RADIOIFADCDEBUG (0x1UL << 3) /**< RADIO IFADC debug privileged mode */ 799 #define _SMU_BMPUPATD0_RADIOIFADCDEBUG_SHIFT 3 /**< Shift value for SMU_RADIOIFADCDEBUG */ 800 #define _SMU_BMPUPATD0_RADIOIFADCDEBUG_MASK 0x8UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ 801 #define _SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ 802 #define SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ 803 #define SMU_BMPUPATD0_LDMA (0x1UL << 4) /**< MCU LDMA privileged mode */ 804 #define _SMU_BMPUPATD0_LDMA_SHIFT 4 /**< Shift value for SMU_LDMA */ 805 #define _SMU_BMPUPATD0_LDMA_MASK 0x10UL /**< Bit mask for SMU_LDMA */ 806 #define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ 807 #define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ 808 809 /* Bit fields for SMU BMPUSATD0 */ 810 #define _SMU_BMPUSATD0_RESETVALUE 0x0000001FUL /**< Default value for SMU_BMPUSATD0 */ 811 #define _SMU_BMPUSATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUSATD0 */ 812 #define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES DMA secure mode */ 813 #define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ 814 #define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ 815 #define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ 816 #define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ 817 #define SMU_BMPUSATD0_CRYPTOACC (0x1UL << 1) /**< CRYPTOACC DMA secure mode */ 818 #define _SMU_BMPUSATD0_CRYPTOACC_SHIFT 1 /**< Shift value for SMU_CRYPTOACC */ 819 #define _SMU_BMPUSATD0_CRYPTOACC_MASK 0x2UL /**< Bit mask for SMU_CRYPTOACC */ 820 #define _SMU_BMPUSATD0_CRYPTOACC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ 821 #define SMU_BMPUSATD0_CRYPTOACC_DEFAULT (_SMU_BMPUSATD0_CRYPTOACC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ 822 #define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 2) /**< RADIO subsystem manager secure mode */ 823 #define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 2 /**< Shift value for SMU_RADIOSUBSYSTEM */ 824 #define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x4UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ 825 #define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ 826 #define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ 827 #define SMU_BMPUSATD0_RADIOIFADCDEBUG (0x1UL << 3) /**< RADIO IFADC debug secure mode */ 828 #define _SMU_BMPUSATD0_RADIOIFADCDEBUG_SHIFT 3 /**< Shift value for SMU_RADIOIFADCDEBUG */ 829 #define _SMU_BMPUSATD0_RADIOIFADCDEBUG_MASK 0x8UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ 830 #define _SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ 831 #define SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ 832 #define SMU_BMPUSATD0_LDMA (0x1UL << 4) /**< MCU LDMA secure mode */ 833 #define _SMU_BMPUSATD0_LDMA_SHIFT 4 /**< Shift value for SMU_LDMA */ 834 #define _SMU_BMPUSATD0_LDMA_MASK 0x10UL /**< Bit mask for SMU_LDMA */ 835 #define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ 836 #define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ 837 838 /* Bit fields for SMU BMPUFS */ 839 #define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ 840 #define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ 841 #define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ 842 #define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ 843 #define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ 844 #define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ 845 846 /* Bit fields for SMU BMPUFSADDR */ 847 #define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ 848 #define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ 849 #define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ 850 #define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ 851 #define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ 852 #define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ 853 854 /* Bit fields for SMU ESAURTYPES0 */ 855 #define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ 856 #define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ 857 #define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure Type */ 858 #define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ 859 #define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ 860 #define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ 861 #define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ 862 863 /* Bit fields for SMU ESAURTYPES1 */ 864 #define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ 865 #define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ 866 #define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure Type */ 867 #define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ 868 #define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ 869 #define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ 870 #define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ 871 872 /* Bit fields for SMU ESAUMRB01 */ 873 #define _SMU_ESAUMRB01_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB01 */ 874 #define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ 875 #define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ 876 #define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ 877 #define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ 878 #define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ 879 880 /* Bit fields for SMU ESAUMRB12 */ 881 #define _SMU_ESAUMRB12_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB12 */ 882 #define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ 883 #define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ 884 #define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ 885 #define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ 886 #define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ 887 888 /* Bit fields for SMU ESAUMRB45 */ 889 #define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ 890 #define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ 891 #define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ 892 #define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ 893 #define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ 894 #define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ 895 896 /* Bit fields for SMU ESAUMRB56 */ 897 #define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ 898 #define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ 899 #define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ 900 #define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ 901 #define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ 902 #define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ 903 904 /** @} End of group EFR32BG22_SMU_BitFields */ 905 /** @} End of group EFR32BG22_SMU */ 906 /**************************************************************************//** 907 * @defgroup EFR32BG22_SMU_CFGNS SMU_CFGNS 908 * @{ 909 * @brief EFR32BG22 SMU_CFGNS Register Declaration. 910 *****************************************************************************/ 911 912 /** SMU_CFGNS Register Declaration. */ 913 typedef struct { 914 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 915 __IM uint32_t NSSTATUS; /**< Non-Secure Status */ 916 __IOM uint32_t NSLOCK; /**< Non-Secure Lock */ 917 __IOM uint32_t NSIF; /**< Non-Secure Interrupt Flag */ 918 __IOM uint32_t NSIEN; /**< Non-Secure Interrupt Enable */ 919 uint32_t RESERVED1[3U]; /**< Reserved for future use */ 920 uint32_t RESERVED2[8U]; /**< Reserved for future use */ 921 __IOM uint32_t PPUNSPATD0; /**< PPU Non-secure PATD Register 0 */ 922 __IOM uint32_t PPUNSPATD1; /**< PPU Non-secure PATD Register 1 */ 923 uint32_t RESERVED3[62U]; /**< Reserved for future use */ 924 __IM uint32_t PPUNSFS; /**< PPU Non-secure Fault Status */ 925 uint32_t RESERVED4[3U]; /**< Reserved for future use */ 926 __IOM uint32_t BMPUNSPATD0; /**< BMPU Non-Secure PATD Register 0 */ 927 uint32_t RESERVED5[63U]; /**< Reserved for future use */ 928 uint32_t RESERVED6[876U]; /**< Reserved for future use */ 929 uint32_t RESERVED7[1U]; /**< Reserved for future use */ 930 __IM uint32_t NSSTATUS_SET; /**< Non-Secure Status */ 931 __IOM uint32_t NSLOCK_SET; /**< Non-Secure Lock */ 932 __IOM uint32_t NSIF_SET; /**< Non-Secure Interrupt Flag */ 933 __IOM uint32_t NSIEN_SET; /**< Non-Secure Interrupt Enable */ 934 uint32_t RESERVED8[3U]; /**< Reserved for future use */ 935 uint32_t RESERVED9[8U]; /**< Reserved for future use */ 936 __IOM uint32_t PPUNSPATD0_SET; /**< PPU Non-secure PATD Register 0 */ 937 __IOM uint32_t PPUNSPATD1_SET; /**< PPU Non-secure PATD Register 1 */ 938 uint32_t RESERVED10[62U]; /**< Reserved for future use */ 939 __IM uint32_t PPUNSFS_SET; /**< PPU Non-secure Fault Status */ 940 uint32_t RESERVED11[3U]; /**< Reserved for future use */ 941 __IOM uint32_t BMPUNSPATD0_SET; /**< BMPU Non-Secure PATD Register 0 */ 942 uint32_t RESERVED12[63U]; /**< Reserved for future use */ 943 uint32_t RESERVED13[876U]; /**< Reserved for future use */ 944 uint32_t RESERVED14[1U]; /**< Reserved for future use */ 945 __IM uint32_t NSSTATUS_CLR; /**< Non-Secure Status */ 946 __IOM uint32_t NSLOCK_CLR; /**< Non-Secure Lock */ 947 __IOM uint32_t NSIF_CLR; /**< Non-Secure Interrupt Flag */ 948 __IOM uint32_t NSIEN_CLR; /**< Non-Secure Interrupt Enable */ 949 uint32_t RESERVED15[3U]; /**< Reserved for future use */ 950 uint32_t RESERVED16[8U]; /**< Reserved for future use */ 951 __IOM uint32_t PPUNSPATD0_CLR; /**< PPU Non-secure PATD Register 0 */ 952 __IOM uint32_t PPUNSPATD1_CLR; /**< PPU Non-secure PATD Register 1 */ 953 uint32_t RESERVED17[62U]; /**< Reserved for future use */ 954 __IM uint32_t PPUNSFS_CLR; /**< PPU Non-secure Fault Status */ 955 uint32_t RESERVED18[3U]; /**< Reserved for future use */ 956 __IOM uint32_t BMPUNSPATD0_CLR; /**< BMPU Non-Secure PATD Register 0 */ 957 uint32_t RESERVED19[63U]; /**< Reserved for future use */ 958 uint32_t RESERVED20[876U]; /**< Reserved for future use */ 959 uint32_t RESERVED21[1U]; /**< Reserved for future use */ 960 __IM uint32_t NSSTATUS_TGL; /**< Non-Secure Status */ 961 __IOM uint32_t NSLOCK_TGL; /**< Non-Secure Lock */ 962 __IOM uint32_t NSIF_TGL; /**< Non-Secure Interrupt Flag */ 963 __IOM uint32_t NSIEN_TGL; /**< Non-Secure Interrupt Enable */ 964 uint32_t RESERVED22[3U]; /**< Reserved for future use */ 965 uint32_t RESERVED23[8U]; /**< Reserved for future use */ 966 __IOM uint32_t PPUNSPATD0_TGL; /**< PPU Non-secure PATD Register 0 */ 967 __IOM uint32_t PPUNSPATD1_TGL; /**< PPU Non-secure PATD Register 1 */ 968 uint32_t RESERVED24[62U]; /**< Reserved for future use */ 969 __IM uint32_t PPUNSFS_TGL; /**< PPU Non-secure Fault Status */ 970 uint32_t RESERVED25[3U]; /**< Reserved for future use */ 971 __IOM uint32_t BMPUNSPATD0_TGL; /**< BMPU Non-Secure PATD Register 0 */ 972 uint32_t RESERVED26[63U]; /**< Reserved for future use */ 973 } SMU_CFGNS_TypeDef; 974 /** @} End of group EFR32BG22_SMU_CFGNS */ 975 976 /**************************************************************************//** 977 * @addtogroup EFR32BG22_SMU_CFGNS 978 * @{ 979 * @defgroup EFR32BG22_SMU_CFGNS_BitFields SMU_CFGNS Bit Fields 980 * @{ 981 *****************************************************************************/ 982 983 /* Bit fields for SMU NSSTATUS */ 984 #define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ 985 #define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ 986 #define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock Status */ 987 #define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ 988 #define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ 989 #define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ 990 #define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ 991 #define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ 992 #define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ 993 #define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ 994 #define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ 995 996 /* Bit fields for SMU NSLOCK */ 997 #define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ 998 #define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ 999 #define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ 1000 #define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ 1001 #define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ 1002 #define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ 1003 #define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ 1004 #define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ 1005 1006 /* Bit fields for SMU NSIF */ 1007 #define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ 1008 #define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ 1009 #define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ 1010 #define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ 1011 #define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ 1012 #define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ 1013 #define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ 1014 #define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ 1015 #define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ 1016 #define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ 1017 #define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ 1018 #define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ 1019 1020 /* Bit fields for SMU NSIEN */ 1021 #define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ 1022 #define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ 1023 #define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ 1024 #define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ 1025 #define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ 1026 #define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ 1027 #define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ 1028 #define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ 1029 #define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ 1030 #define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ 1031 #define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ 1032 #define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ 1033 1034 /* Bit fields for SMU PPUNSPATD0 */ 1035 #define _SMU_PPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD0 */ 1036 #define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ 1037 #define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ 1038 #define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ 1039 #define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ 1040 #define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1041 #define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1042 #define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ 1043 #define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ 1044 #define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ 1045 #define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1046 #define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1047 #define SMU_PPUNSPATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Privileged Access */ 1048 #define _SMU_PPUNSPATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ 1049 #define _SMU_PPUNSPATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ 1050 #define _SMU_PPUNSPATD0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1051 #define SMU_PPUNSPATD0_HFXO0_DEFAULT (_SMU_PPUNSPATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1052 #define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Privileged Access */ 1053 #define _SMU_PPUNSPATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ 1054 #define _SMU_PPUNSPATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ 1055 #define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1056 #define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1057 #define SMU_PPUNSPATD0_FSRCO (0x1UL << 5) /**< FSRCO Privileged Access */ 1058 #define _SMU_PPUNSPATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ 1059 #define _SMU_PPUNSPATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ 1060 #define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1061 #define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1062 #define SMU_PPUNSPATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Privileged Access */ 1063 #define _SMU_PPUNSPATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ 1064 #define _SMU_PPUNSPATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ 1065 #define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1066 #define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1067 #define SMU_PPUNSPATD0_LFXO (0x1UL << 7) /**< LFXO Privileged Access */ 1068 #define _SMU_PPUNSPATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ 1069 #define _SMU_PPUNSPATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ 1070 #define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1071 #define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1072 #define SMU_PPUNSPATD0_LFRCO (0x1UL << 8) /**< LFRCO Privileged Access */ 1073 #define _SMU_PPUNSPATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ 1074 #define _SMU_PPUNSPATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ 1075 #define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1076 #define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1077 #define SMU_PPUNSPATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Privileged Access */ 1078 #define _SMU_PPUNSPATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ 1079 #define _SMU_PPUNSPATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ 1080 #define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1081 #define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1082 #define SMU_PPUNSPATD0_MSC (0x1UL << 10) /**< MSC Privileged Access */ 1083 #define _SMU_PPUNSPATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ 1084 #define _SMU_PPUNSPATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ 1085 #define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1086 #define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1087 #define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Privileged Access */ 1088 #define _SMU_PPUNSPATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ 1089 #define _SMU_PPUNSPATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ 1090 #define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1091 #define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1092 #define SMU_PPUNSPATD0_PRS (0x1UL << 12) /**< PRS Privileged Access */ 1093 #define _SMU_PPUNSPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ 1094 #define _SMU_PPUNSPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ 1095 #define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1096 #define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1097 #define SMU_PPUNSPATD0_GPIO (0x1UL << 13) /**< GPIO Privileged Access */ 1098 #define _SMU_PPUNSPATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ 1099 #define _SMU_PPUNSPATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ 1100 #define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1101 #define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1102 #define SMU_PPUNSPATD0_LDMA (0x1UL << 14) /**< LDMA Privileged Access */ 1103 #define _SMU_PPUNSPATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ 1104 #define _SMU_PPUNSPATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ 1105 #define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1106 #define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1107 #define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Privileged Access */ 1108 #define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ 1109 #define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ 1110 #define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1111 #define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1112 #define SMU_PPUNSPATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Privileged Access */ 1113 #define _SMU_PPUNSPATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ 1114 #define _SMU_PPUNSPATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ 1115 #define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1116 #define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1117 #define SMU_PPUNSPATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Privileged Access */ 1118 #define _SMU_PPUNSPATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ 1119 #define _SMU_PPUNSPATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ 1120 #define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1121 #define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1122 #define SMU_PPUNSPATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Privileged Access */ 1123 #define _SMU_PPUNSPATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ 1124 #define _SMU_PPUNSPATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ 1125 #define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1126 #define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1127 #define SMU_PPUNSPATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Privileged Access */ 1128 #define _SMU_PPUNSPATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ 1129 #define _SMU_PPUNSPATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ 1130 #define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1131 #define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1132 #define SMU_PPUNSPATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Privileged Access */ 1133 #define _SMU_PPUNSPATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ 1134 #define _SMU_PPUNSPATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ 1135 #define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1136 #define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1137 #define SMU_PPUNSPATD0_USART0 (0x1UL << 21) /**< USART0 Privileged Access */ 1138 #define _SMU_PPUNSPATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ 1139 #define _SMU_PPUNSPATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ 1140 #define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1141 #define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1142 #define SMU_PPUNSPATD0_USART1 (0x1UL << 22) /**< USART1 Privileged Access */ 1143 #define _SMU_PPUNSPATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ 1144 #define _SMU_PPUNSPATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ 1145 #define _SMU_PPUNSPATD0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1146 #define SMU_PPUNSPATD0_USART1_DEFAULT (_SMU_PPUNSPATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1147 #define SMU_PPUNSPATD0_BURTC (0x1UL << 23) /**< BURTC Privileged Access */ 1148 #define _SMU_PPUNSPATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ 1149 #define _SMU_PPUNSPATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ 1150 #define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1151 #define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1152 #define SMU_PPUNSPATD0_I2C1 (0x1UL << 24) /**< I2C1 Privileged Access */ 1153 #define _SMU_PPUNSPATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ 1154 #define _SMU_PPUNSPATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ 1155 #define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1156 #define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1157 #define SMU_PPUNSPATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Privileged Access */ 1158 #define _SMU_PPUNSPATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ 1159 #define _SMU_PPUNSPATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ 1160 #define _SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1161 #define SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1162 #define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Privileged Access */ 1163 #define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ 1164 #define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ 1165 #define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1166 #define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1167 #define SMU_PPUNSPATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Privileged Access */ 1168 #define _SMU_PPUNSPATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ 1169 #define _SMU_PPUNSPATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ 1170 #define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1171 #define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1172 #define SMU_PPUNSPATD0_BURAM (0x1UL << 28) /**< BURAM Privileged Access */ 1173 #define _SMU_PPUNSPATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ 1174 #define _SMU_PPUNSPATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ 1175 #define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1176 #define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1177 #define SMU_PPUNSPATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Privileged Access */ 1178 #define _SMU_PPUNSPATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ 1179 #define _SMU_PPUNSPATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ 1180 #define _SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1181 #define SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT (_SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1182 #define SMU_PPUNSPATD0_GPCRC (0x1UL << 30) /**< GPCRC Privileged Access */ 1183 #define _SMU_PPUNSPATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ 1184 #define _SMU_PPUNSPATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ 1185 #define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1186 #define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1187 #define SMU_PPUNSPATD0_DCI (0x1UL << 31) /**< DCI Privileged Access */ 1188 #define _SMU_PPUNSPATD0_DCI_SHIFT 31 /**< Shift value for SMU_DCI */ 1189 #define _SMU_PPUNSPATD0_DCI_MASK 0x80000000UL /**< Bit mask for SMU_DCI */ 1190 #define _SMU_PPUNSPATD0_DCI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ 1191 #define SMU_PPUNSPATD0_DCI_DEFAULT (_SMU_PPUNSPATD0_DCI_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ 1192 1193 /* Bit fields for SMU PPUNSPATD1 */ 1194 #define _SMU_PPUNSPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD1 */ 1195 #define _SMU_PPUNSPATD1_MASK 0x0000FFFFUL /**< Mask for SMU_PPUNSPATD1 */ 1196 #define SMU_PPUNSPATD1_DCDC (0x1UL << 1) /**< DCDC Privileged Access */ 1197 #define _SMU_PPUNSPATD1_DCDC_SHIFT 1 /**< Shift value for SMU_DCDC */ 1198 #define _SMU_PPUNSPATD1_DCDC_MASK 0x2UL /**< Bit mask for SMU_DCDC */ 1199 #define _SMU_PPUNSPATD1_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1200 #define SMU_PPUNSPATD1_DCDC_DEFAULT (_SMU_PPUNSPATD1_DCDC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1201 #define SMU_PPUNSPATD1_PDM (0x1UL << 2) /**< PDM Privileged Access */ 1202 #define _SMU_PPUNSPATD1_PDM_SHIFT 2 /**< Shift value for SMU_PDM */ 1203 #define _SMU_PPUNSPATD1_PDM_MASK 0x4UL /**< Bit mask for SMU_PDM */ 1204 #define _SMU_PPUNSPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1205 #define SMU_PPUNSPATD1_PDM_DEFAULT (_SMU_PPUNSPATD1_PDM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1206 #define SMU_PPUNSPATD1_RFSENSE (0x1UL << 3) /**< RFSENSE Privileged Access */ 1207 #define _SMU_PPUNSPATD1_RFSENSE_SHIFT 3 /**< Shift value for SMU_RFSENSE */ 1208 #define _SMU_PPUNSPATD1_RFSENSE_MASK 0x8UL /**< Bit mask for SMU_RFSENSE */ 1209 #define _SMU_PPUNSPATD1_RFSENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1210 #define SMU_PPUNSPATD1_RFSENSE_DEFAULT (_SMU_PPUNSPATD1_RFSENSE_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1211 #define SMU_PPUNSPATD1_RADIOAES (0x1UL << 4) /**< RADIOAES Privileged Access */ 1212 #define _SMU_PPUNSPATD1_RADIOAES_SHIFT 4 /**< Shift value for SMU_RADIOAES */ 1213 #define _SMU_PPUNSPATD1_RADIOAES_MASK 0x10UL /**< Bit mask for SMU_RADIOAES */ 1214 #define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1215 #define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1216 #define SMU_PPUNSPATD1_SMU (0x1UL << 5) /**< SMU Privileged Access */ 1217 #define _SMU_PPUNSPATD1_SMU_SHIFT 5 /**< Shift value for SMU_SMU */ 1218 #define _SMU_PPUNSPATD1_SMU_MASK 0x20UL /**< Bit mask for SMU_SMU */ 1219 #define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1220 #define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1221 #define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 6) /**< SMUCFGNS Privileged Access */ 1222 #define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 6 /**< Shift value for SMU_SMUCFGNS */ 1223 #define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x40UL /**< Bit mask for SMU_SMUCFGNS */ 1224 #define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1225 #define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1226 #define SMU_PPUNSPATD1_RTCC (0x1UL << 7) /**< RTCC Privileged Access */ 1227 #define _SMU_PPUNSPATD1_RTCC_SHIFT 7 /**< Shift value for SMU_RTCC */ 1228 #define _SMU_PPUNSPATD1_RTCC_MASK 0x80UL /**< Bit mask for SMU_RTCC */ 1229 #define _SMU_PPUNSPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1230 #define SMU_PPUNSPATD1_RTCC_DEFAULT (_SMU_PPUNSPATD1_RTCC_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1231 #define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 8) /**< LETIMER0 Privileged Access */ 1232 #define _SMU_PPUNSPATD1_LETIMER0_SHIFT 8 /**< Shift value for SMU_LETIMER0 */ 1233 #define _SMU_PPUNSPATD1_LETIMER0_MASK 0x100UL /**< Bit mask for SMU_LETIMER0 */ 1234 #define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1235 #define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1236 #define SMU_PPUNSPATD1_IADC0 (0x1UL << 9) /**< IADC0 Privileged Access */ 1237 #define _SMU_PPUNSPATD1_IADC0_SHIFT 9 /**< Shift value for SMU_IADC0 */ 1238 #define _SMU_PPUNSPATD1_IADC0_MASK 0x200UL /**< Bit mask for SMU_IADC0 */ 1239 #define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1240 #define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1241 #define SMU_PPUNSPATD1_I2C0 (0x1UL << 10) /**< I2C0 Privileged Access */ 1242 #define _SMU_PPUNSPATD1_I2C0_SHIFT 10 /**< Shift value for SMU_I2C0 */ 1243 #define _SMU_PPUNSPATD1_I2C0_MASK 0x400UL /**< Bit mask for SMU_I2C0 */ 1244 #define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1245 #define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1246 #define SMU_PPUNSPATD1_WDOG0 (0x1UL << 11) /**< WDOG0 Privileged Access */ 1247 #define _SMU_PPUNSPATD1_WDOG0_SHIFT 11 /**< Shift value for SMU_WDOG0 */ 1248 #define _SMU_PPUNSPATD1_WDOG0_MASK 0x800UL /**< Bit mask for SMU_WDOG0 */ 1249 #define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1250 #define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1251 #define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 12) /**< AMUXCP0 Privileged Access */ 1252 #define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 12 /**< Shift value for SMU_AMUXCP0 */ 1253 #define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x1000UL /**< Bit mask for SMU_AMUXCP0 */ 1254 #define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1255 #define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1256 #define SMU_PPUNSPATD1_EUART0 (0x1UL << 13) /**< EUART0 Privileged Access */ 1257 #define _SMU_PPUNSPATD1_EUART0_SHIFT 13 /**< Shift value for SMU_EUART0 */ 1258 #define _SMU_PPUNSPATD1_EUART0_MASK 0x2000UL /**< Bit mask for SMU_EUART0 */ 1259 #define _SMU_PPUNSPATD1_EUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1260 #define SMU_PPUNSPATD1_EUART0_DEFAULT (_SMU_PPUNSPATD1_EUART0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1261 #define SMU_PPUNSPATD1_CRYPTOACC (0x1UL << 14) /**< CRYPTOACC Privileged Access */ 1262 #define _SMU_PPUNSPATD1_CRYPTOACC_SHIFT 14 /**< Shift value for SMU_CRYPTOACC */ 1263 #define _SMU_PPUNSPATD1_CRYPTOACC_MASK 0x4000UL /**< Bit mask for SMU_CRYPTOACC */ 1264 #define _SMU_PPUNSPATD1_CRYPTOACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1265 #define SMU_PPUNSPATD1_CRYPTOACC_DEFAULT (_SMU_PPUNSPATD1_CRYPTOACC_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1266 #define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 15) /**< AHBRADIO Privileged Access */ 1267 #define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 15 /**< Shift value for SMU_AHBRADIO */ 1268 #define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x8000UL /**< Bit mask for SMU_AHBRADIO */ 1269 #define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ 1270 #define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ 1271 1272 /* Bit fields for SMU PPUNSFS */ 1273 #define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ 1274 #define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ 1275 #define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ 1276 #define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ 1277 #define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ 1278 #define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ 1279 1280 /* Bit fields for SMU BMPUNSPATD0 */ 1281 #define _SMU_BMPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUNSPATD0 */ 1282 #define _SMU_BMPUNSPATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUNSPATD0 */ 1283 #define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ 1284 #define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ 1285 #define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ 1286 #define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ 1287 #define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ 1288 #define SMU_BMPUNSPATD0_CRYPTOACC (0x1UL << 1) /**< CRYPTOACC DMA privileged mode */ 1289 #define _SMU_BMPUNSPATD0_CRYPTOACC_SHIFT 1 /**< Shift value for SMU_CRYPTOACC */ 1290 #define _SMU_BMPUNSPATD0_CRYPTOACC_MASK 0x2UL /**< Bit mask for SMU_CRYPTOACC */ 1291 #define _SMU_BMPUNSPATD0_CRYPTOACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ 1292 #define SMU_BMPUNSPATD0_CRYPTOACC_DEFAULT (_SMU_BMPUNSPATD0_CRYPTOACC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ 1293 #define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 2) /**< RADIO subsystem manager privileged mode */ 1294 #define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 2 /**< Shift value for SMU_RADIOSUBSYSTEM */ 1295 #define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x4UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ 1296 #define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ 1297 #define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ 1298 #define SMU_BMPUNSPATD0_RADIOIFADCDEBUG (0x1UL << 3) /**< RADIO IFADC debug privileged mode */ 1299 #define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_SHIFT 3 /**< Shift value for SMU_RADIOIFADCDEBUG */ 1300 #define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_MASK 0x8UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ 1301 #define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ 1302 #define SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ 1303 #define SMU_BMPUNSPATD0_LDMA (0x1UL << 4) /**< MCU LDMA privileged mode */ 1304 #define _SMU_BMPUNSPATD0_LDMA_SHIFT 4 /**< Shift value for SMU_LDMA */ 1305 #define _SMU_BMPUNSPATD0_LDMA_MASK 0x10UL /**< Bit mask for SMU_LDMA */ 1306 #define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ 1307 #define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ 1308 1309 /** @} End of group EFR32BG22_SMU_CFGNS_BitFields */ 1310 /** @} End of group EFR32BG22_SMU_CFGNS */ 1311 /** @} End of group Parts */ 1312 1313 #endif /* EFR32BG22_SMU_H */ 1314
