1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG24 HFRCO register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG24_HFRCO_H 31 #define EFR32MG24_HFRCO_H 32 #define HFRCO_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG24_HFRCO HFRCO 40 * @{ 41 * @brief EFR32MG24 HFRCO Register Declaration. 42 *****************************************************************************/ 43 44 /** HFRCO Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP Version ID */ 47 __IOM uint32_t CTRL; /**< Ctrl Register */ 48 __IOM uint32_t CAL; /**< Calibration Register */ 49 __IM uint32_t STATUS; /**< Status Register */ 50 __IOM uint32_t IF; /**< Interrupt Flag Register */ 51 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 52 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 53 __IOM uint32_t LOCK; /**< Lock Register */ 54 uint32_t RESERVED1[1016U]; /**< Reserved for future use */ 55 __IM uint32_t IPVERSION_SET; /**< IP Version ID */ 56 __IOM uint32_t CTRL_SET; /**< Ctrl Register */ 57 __IOM uint32_t CAL_SET; /**< Calibration Register */ 58 __IM uint32_t STATUS_SET; /**< Status Register */ 59 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 60 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 61 uint32_t RESERVED2[1U]; /**< Reserved for future use */ 62 __IOM uint32_t LOCK_SET; /**< Lock Register */ 63 uint32_t RESERVED3[1016U]; /**< Reserved for future use */ 64 __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ 65 __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ 66 __IOM uint32_t CAL_CLR; /**< Calibration Register */ 67 __IM uint32_t STATUS_CLR; /**< Status Register */ 68 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 69 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 70 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 71 __IOM uint32_t LOCK_CLR; /**< Lock Register */ 72 uint32_t RESERVED5[1016U]; /**< Reserved for future use */ 73 __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ 74 __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ 75 __IOM uint32_t CAL_TGL; /**< Calibration Register */ 76 __IM uint32_t STATUS_TGL; /**< Status Register */ 77 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 78 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 79 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 80 __IOM uint32_t LOCK_TGL; /**< Lock Register */ 81 } HFRCO_TypeDef; 82 /** @} End of group EFR32MG24_HFRCO */ 83 84 /**************************************************************************//** 85 * @addtogroup EFR32MG24_HFRCO 86 * @{ 87 * @defgroup EFR32MG24_HFRCO_BitFields HFRCO Bit Fields 88 * @{ 89 *****************************************************************************/ 90 91 /* Bit fields for HFRCO IPVERSION */ 92 #define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */ 93 #define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ 94 #define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ 95 #define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ 96 #define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */ 97 #define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ 98 99 /* Bit fields for HFRCO CTRL */ 100 #define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ 101 #define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */ 102 #define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ 103 #define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ 104 #define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ 105 #define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ 106 #define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ 107 #define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ 108 #define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ 109 #define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ 110 #define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ 111 #define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ 112 #define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */ 113 #define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */ 114 #define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */ 115 #define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ 116 #define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */ 117 118 /* Bit fields for HFRCO CAL */ 119 #define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ 120 #define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ 121 #define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ 122 #define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ 123 #define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ 124 #define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ 125 #define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ 126 #define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ 127 #define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ 128 #define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ 129 #define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ 130 #define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ 131 #define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ 132 #define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ 133 #define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ 134 #define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ 135 #define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ 136 #define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ 137 #define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ 138 #define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ 139 #define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ 140 #define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ 141 #define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ 142 #define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ 143 #define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ 144 #define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ 145 #define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ 146 #define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ 147 #define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ 148 #define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ 149 #define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ 150 #define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ 151 #define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ 152 #define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ 153 #define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ 154 #define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ 155 #define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ 156 #define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ 157 #define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ 158 #define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ 159 #define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ 160 161 /* Bit fields for HFRCO STATUS */ 162 #define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ 163 #define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ 164 #define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ 165 #define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ 166 #define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ 167 #define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ 168 #define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ 169 #define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ 170 #define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ 171 #define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ 172 #define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ 173 #define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ 174 #define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ 175 #define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ 176 #define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ 177 #define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ 178 #define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ 179 #define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ 180 #define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ 181 #define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ 182 #define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ 183 #define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ 184 #define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ 185 #define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ 186 #define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ 187 #define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ 188 #define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ 189 #define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ 190 #define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ 191 #define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ 192 #define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ 193 194 /* Bit fields for HFRCO IF */ 195 #define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ 196 #define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ 197 #define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ 198 #define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ 199 #define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ 200 #define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ 201 #define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ 202 203 /* Bit fields for HFRCO IEN */ 204 #define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ 205 #define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ 206 #define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ 207 #define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ 208 #define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ 209 #define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ 210 #define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ 211 212 /* Bit fields for HFRCO LOCK */ 213 #define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ 214 #define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ 215 #define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ 216 #define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ 217 #define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ 218 #define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ 219 #define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ 220 #define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ 221 222 /** @} End of group EFR32MG24_HFRCO_BitFields */ 223 /** @} End of group EFR32MG24_HFRCO */ 224 /** @} End of group Parts */ 225 226 #endif /* EFR32MG24_HFRCO_H */ 227
