Home
last modified time | relevance | path

Searched refs:_EMU_IFS_VMONALTAVDDRISE_DEFAULT (Results 1 – 25 of 71) sorted by relevance

123

/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p_emu.h388 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
389 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) …
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b_emu.h388 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
389 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) …
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_emu.h462 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
463 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_emu.h457 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
458 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_emu.h457 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
458 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_emu.h462 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
463 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_emu.h462 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
463 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_emu.h510 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
511 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b390f1024gl112.h2586 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
2587 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b390f512gl112.h2586 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
2587 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512il120.h3425 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3426 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512im64.h3425 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3426 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512iq100.h3425 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3426 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512iq64.h3425 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3426 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512gm64.h3425 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3426 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512gq100.h3425 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3426 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512gq64.h3425 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3426 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512il112.h3425 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3426 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b110f1024gm64.h3417 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3418 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b510f1024gl112.h3425 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3426 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b510f1024gl120.h3425 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3426 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b510f1024gm64.h3425 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3426 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b510f1024gq100.h3425 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3426 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b510f1024gq64.h3425 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3426 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_emu.h518 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
519 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3…

123