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/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b100f128gm32.h421 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
422 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32pg1b100f128im32.h421 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
422 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32pg1b100f256gm32.h421 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
422 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32pg1b100f256im32.h421 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
422 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32pg1b200f128gm32.h423 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
424 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32pg1b200f128gm48.h423 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
424 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32pg1b200f128im32.h423 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
424 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32pg1b200f256gm32.h423 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
424 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32pg1b200f256gm48.h423 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
424 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32pg1b200f256im32.h423 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
424 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32pg1b200f256im48.h423 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
424 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFM32HG/Include/
Defm32hg322f64.h396 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
397 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32hg350f32.h396 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
397 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32hg350f64.h396 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
397 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32hg309f32.h396 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
397 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32hg309f64.h396 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
397 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32hg310f32.h396 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
397 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32hg310f64.h396 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
397 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defm32hg322f32.h396 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
397 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p132f64gm32.h437 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
438 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defr32fg1p132f64gm48.h437 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
438 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defr32fg1p133f128gm48.h437 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
438 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defr32fg1p133f256gm32.h437 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
438 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defr32fg1p133f256gm48.h437 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
438 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
Defr32fg1p133f64gm48.h437 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
438 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));

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