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Searched refs:STATUS (Results 1 – 25 of 497) sorted by relevance

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/hal_silabs-3.6.0/gecko/emlib/src/
Dem_vdac.c66 while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { in VDAC_DisableModule()
72 while (vdac->STATUS & (VDAC_STATUS_CH0ENS)) { in VDAC_DisableModule()
76 while (vdac->STATUS & (VDAC_STATUS_CH1ENS)) { in VDAC_DisableModule()
80 while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { in VDAC_DisableModule()
85 …while (vdac->STATUS & (VDAC_STATUS_SYNCBUSY | VDAC_STATUS_CH0FIFOFLBUSY | VDAC_STATUS_CH1FIFOFLBUS… in VDAC_DisableModule()
120 while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { in VDAC_Enable()
127 while ((vdac->STATUS & VDAC_STATUS_CH0ENS) == 0) { in VDAC_Enable()
131 while (vdac->STATUS & VDAC_STATUS_CH0ENS) { in VDAC_Enable()
134 while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { in VDAC_Enable()
137 while (vdac->STATUS & VDAC_STATUS_CH0FIFOFLBUSY) { in VDAC_Enable()
[all …]
Dem_msc.c242 #define MSC_IS_LOCKED() ((MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != 0U)
344 uint32_t status = MSC->STATUS; in mscStatusWait()
412 if (MSC->STATUS & MSC_STATUS_INVADDR) { in writeBurst()
747 if (MSC->STATUS & MSC_STATUS_INVADDR) { in MSC_WriteWordDma()
799 EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); in MSC_Init()
800 EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); in MSC_Init()
946 while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { in MSC_LoadVerifyAddress()
959 if (MSC->STATUS & MSC_STATUS_INVADDR) { in MSC_LoadVerifyAddress()
1001 while ((!(MSC->STATUS & MSC_STATUS_WDATAREADY)) && (timeOut != 0)) { in MSC_LoadWriteData()
1018 while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { in MSC_LoadWriteData()
[all …]
Dem_aes.c208 while (AES->STATUS & AES_STATUS_RUNNING) in AES_CBC128()
243 while (AES->STATUS & AES_STATUS_RUNNING) in AES_CBC128()
334 while (AES->STATUS & AES_STATUS_RUNNING) in AES_CBC256()
361 while (AES->STATUS & AES_STATUS_RUNNING) in AES_CBC256()
492 while (AES->STATUS & AES_STATUS_RUNNING) in AES_CFB128()
571 while (AES->STATUS & AES_STATUS_RUNNING) in AES_CFB256()
689 while (AES->STATUS & AES_STATUS_RUNNING) in AES_CTR128()
761 while (AES->STATUS & AES_STATUS_RUNNING) in AES_CTR256()
823 while (AES->STATUS & AES_STATUS_RUNNING) in AES_DecryptKey128()
864 while (AES->STATUS & AES_STATUS_RUNNING) in AES_DecryptKey256()
[all …]
Dem_leuart.c527 while (!(leuart->STATUS & LEUART_STATUS_RXDATAV)) { in LEUART_Rx()
552 while (!(leuart->STATUS & LEUART_STATUS_RXDATAV)) { in LEUART_RxExt()
584 while (!(leuart->STATUS & LEUART_STATUS_TXBL)) { in LEUART_Tx()
615 while (!(leuart->STATUS & LEUART_STATUS_TXBL)) { in LEUART_TxExt()
644 bool txEnabled = (leuart->STATUS & _LEUART_STATUS_TXENS_MASK) != 0U; in LEUART_TxDmaInEM2Enable()
647 while ((leuart->STATUS & LEUART_STATUS_TXIDLE) == 0U) { in LEUART_TxDmaInEM2Enable()
692 bool rxEnabled = (leuart->STATUS & _LEUART_STATUS_RXENS_MASK) != 0U; in LEUART_RxDmaInEM2Enable()
Dem_eusart.c385 while ((eusart->STATUS & (_EUSART_STATUS_TXENS_MASK | _EUSART_STATUS_RXENS_MASK)) != tmp) { in EUSART_Enable()
407 while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { in EUSART_Rx()
417 while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { in EUSART_Rx()
431 while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { in EUSART_RxExt()
443 while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { in EUSART_Tx()
455 while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { in EUSART_TxExt()
468 while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { in EUSART_Spi_TxRx()
473 while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { in EUSART_Spi_TxRx()
490 while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { in EUSART_Dali_Tx()
516 while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { in EUSART_Dali_Rx()
[all …]
Dem_cmu.c478 while ((CMU->STATUS & CMU_STATUS_CALRDY) == 0UL) { in CMU_CalibrateCountGet()
1627 while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { in CMU_ClockSelectSet()
2514 while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { in CMU_HFRCODPLLBandSet()
2556 while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { in CMU_HFRCODPLLBandSet()
2653 while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { in CMU_DPLLLock()
2721 while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { in CMU_DPLLLock()
2834 while (USBPLL0->STATUS & USBPLL_STATUS_PLLLOCK) ; in CMU_USBPLLInit()
2843 while (USBPLL0->STATUS & USBPLL_STATUS_SYNCBUSY) ; in CMU_USBPLLInit()
2856 while (USBPLL0->STATUS & USBPLL_STATUS_SYNCBUSY) ; in CMU_USBPLLInit()
2975 while ((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0U) { in CMU_HFXOInit()
[all …]
Dem_usart.c1184 while (!(usart->STATUS & USART_STATUS_RXDATAV)) { in USART_Rx()
1216 while (!(usart->STATUS & USART_STATUS_RXFULL)) { in USART_RxDouble()
1248 while (!(usart->STATUS & USART_STATUS_RXFULL)) { in USART_RxDoubleExt()
1280 while (!(usart->STATUS & USART_STATUS_RXDATAV)) { in USART_RxExt()
1307 while (!(usart->STATUS & USART_STATUS_TXBL)) { in USART_SpiTransfer()
1310 while (!(usart->STATUS & USART_STATUS_TXC)) { in USART_SpiTransfer()
1341 while (!(usart->STATUS & USART_STATUS_TXBL)) { in USART_Tx()
1376 while (!(usart->STATUS & USART_STATUS_TXBL)) { in USART_TxDouble()
1411 while (!(usart->STATUS & USART_STATUS_TXBL)) { in USART_TxDoubleExt()
1438 while (!(usart->STATUS & USART_STATUS_TXBL)) { in USART_TxExt()
Dem_opamp.c281 while (dac->STATUS & VDAC_STATUS_OPA0ENS) { in OPAMP_Disable()
287 while (dac->STATUS & VDAC_STATUS_OPA1ENS) { in OPAMP_Disable()
293 while (dac->STATUS & VDAC_STATUS_OPA2ENS) { in OPAMP_Disable()
299 while (dac->STATUS & VDAC_STATUS_OPA3ENS) { in OPAMP_Disable()
Dem_iadc.c134 while ((iadc->STATUS & IADC_STATUS_SYNCBUSY) != 0U) { in IADC_disable()
808 while ((iadc->STATUS & (IADC_STATUS_CONVERTING in IADC_reset()
820 while ((iadc->STATUS & (IADC_STATUS_MASKREQWRITEPENDING in IADC_reset()
829 while (((iadc->STATUS & IADC_STATUS_SINGLEFIFODV) != 0UL) || (iadc->SINGLEFIFOSTAT > 0)) { in IADC_reset()
835 while (((iadc->STATUS & IADC_STATUS_SCANFIFODV) != 0UL) || (iadc->SCANFIFOSTAT > 0)) { in IADC_reset()
Dem_letimer.c365 if (!(init->enable) && (letimer->STATUS & LETIMER_STATUS_RUNNING)) { in LETIMER_Init()
427 if (init->enable && !(letimer->STATUS & LETIMER_STATUS_RUNNING)) { in LETIMER_Init()
Dem_emu.c413 cmuStatus = CMU->STATUS; in emState()
418 vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) in emState()
663 uint32_t em01vs = (EMU->STATUS & _EMU_STATUS_VSCALE_MASK) >> _EMU_STATUS_VSCALE_SHIFT; in vScaleDownEM23Setup()
1512 while ((CMU->STATUS & CMU_STATUS_HFRCORDY) == 0U) { in EMU_EnterEM4()
1934 && ((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U)) { in EMU_VScaleEM01()
1935 EFM_ASSERT((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U); in EMU_VScaleEM01()
3432 while (((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { in EMU_DCDCModeSet()
3444 while (((DCDC->STATUS & DCDC_STATUS_VREGIN) != 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { in EMU_DCDCModeSet()
4036 return BUS_RegBitRead(&EMU->STATUS, bit) != 0U; in EMU_VmonChannelStatusGet()
/hal_silabs-3.6.0/gecko/service/power_manager/src/
Dsl_power_manager_hal_s2.c195 is_dpll_used = ((DPLL0->STATUS & _DPLL_STATUS_ENS_MASK) != 0); in sli_power_manager_init_hardware()
369 if (((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0 in EMU_EM23PostsleepHook()
371 || (HFXO0->STATUS & _HFXO_STATUS_RDY_MASK) != 0) { in EMU_EM23PostsleepHook()
426 if (((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0 in sli_power_manager_restore_high_freq_accuracy_clk()
428 || (HFXO0->STATUS & _HFXO_STATUS_RDY_MASK) != 0) { in sli_power_manager_restore_high_freq_accuracy_clk()
507 while ((DPLL0->STATUS & _DPLL_STATUS_RDY_MASK) == 0U) { in sli_power_manager_restore_states()
535 while (!(DPLL0->STATUS && _DPLL_STATUS_RDY_MASK)) { in sli_power_manager_restore_states()
/hal_silabs-3.6.0/gecko/service/hfxo_manager/src/
Dsl_hfxo_manager_hal_s2.c196 …ready = (((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_PRSRDY)) != 0) && !error_flag) ? true : … in sli_hfxo_manager_is_hfxo_ready()
198 ready = (((HFXO0->STATUS & HFXO_STATUS_RDY) != 0) && !error_flag) ? true : false; in sli_hfxo_manager_is_hfxo_ready()
266 while ((HFXO0->STATUS & HFXO_STATUS_ENS) != 0) { in sl_hfxo_manager_irq_handler()
339 while ((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0U) { in sl_hfxo_manager_irq_handler()
386 while ((HFXO0->STATUS & HFXO_STATUS_ENS) != 0) { in sl_hfxo_manager_irq_handler()
/hal_silabs-3.6.0/gecko/emlib/inc/
Dem_vcmp.h181 if (VCMP->STATUS & VCMP_STATUS_VCMPOUT) { in VCMP_VDDLower()
198 if (VCMP->STATUS & VCMP_STATUS_VCMPOUT) { in VCMP_VDDHigher()
214 if (VCMP->STATUS & VCMP_STATUS_VCMPACT) { in VCMP_Ready()
Dem_can.h317 (can->STATUS & _CAN_STATUS_LEC_MASK); in CAN_GetLastErrorCode()
318 can->STATUS |= ~_CAN_STATUS_LEC_MASK; in CAN_GetLastErrorCode()
449 return can->STATUS & ~_CAN_STATUS_LEC_MASK; in CAN_StatusGet()
464 can->STATUS &= ~flags; in CAN_StatusClear()
Dem_vdac.h543 while (0UL != (vdac->STATUS & VDAC_STATUS_SYNCBUSY)) { in VDAC_SineModeStart()
548 while (0UL == (vdac->STATUS & VDAC_STATUS_SINEACTIVE)) { in VDAC_SineModeStart()
552 while (0UL != (vdac->STATUS & VDAC_STATUS_SINEACTIVE)) { in VDAC_SineModeStart()
754 return vdac->STATUS; in VDAC_GetStatus()
Dem_lcd.h494 while (LCD->STATUS & _LCD_STATUS_LOADBUSY_MASK) ; in LCD_LoadBusyWait()
507 || (LCD->STATUS & _LCD_STATUS_LOADBUSY_MASK)) { in LCD_ReadyWait()
700 return (int)(LCD->STATUS & _LCD_STATUS_ASTATE_MASK) >> _LCD_STATUS_ASTATE_SHIFT; in LCD_AnimState()
712 return (int)(LCD->STATUS & _LCD_STATUS_BLINK_MASK) >> _LCD_STATUS_BLINK_SHIFT; in LCD_BlinkState()
Dem_emu.h1332 while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT) != 0U) { in EMU_VScaleWait()
1349 ((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) in EMU_VScaleGet()
1365 return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT) != 0U; in EMU_VmonStatusGet()
1593 while (!(EMU->STATUS & EMU_STATUS_BURDY)) in EMU_BUReady()
1707 return (0UL != (EMU->STATUS & EMU_STATUS_FIRSTTEMPDONE)); in EMU_TemperatureReady()
Dem_pdm.h423 while ((pdm->STATUS & PDM_STATUS_EMPTY) == PDM_STATUS_EMPTY) { in PDM_Rx()
456 return pdm->STATUS; in PDM_StatusGet()
Dem_chip.h313 if (chipRev.major == 0x01 && (HFXO0->STATUS & HFXO_STATUS_ENS) == 0U) { in CHIP_Init()
376 while ((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) { in CHIP_Init()
Dsli_em_cmu.h1680 while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) {} \
1687 while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) {} \
1694 while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) {} \
1703 while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) {} \
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFM32HG/Source/
Dsystem_efm32hg.c165 switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL in SystemHFClockGet()
276 if ((CMU->STATUS & CMU_STATUS_HFXOSEL) != 0U) { in SystemHFXOClockSet()
380 if ((CMU->STATUS & CMU_STATUS_LFXOSEL) != 0U) { in SystemLFXOClockSet()
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFM32WG/Source/
Dsystem_efm32wg.c172 switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL in SystemHFClockGet()
285 if ((CMU->STATUS & CMU_STATUS_HFXOSEL) != 0U) { in SystemHFXOClockSet()
399 if ((CMU->STATUS & CMU_STATUS_LFXOSEL) != 0U) { in SystemLFXOClockSet()
/hal_silabs-3.6.0/gecko/util/third_party/crypto/sl_component/sl_protocol_crypto/src/
Dsli_radioaes_management.c93 …while (RADIOAES->STATUS & (AES_STATUS_FETCHERBSY | AES_STATUS_PUSHERBSY | AES_STATUS_SOFTRSTBSY)) { in sli_radioaes_acquire()
154 …while (RADIOAES->STATUS & (AES_STATUS_FETCHERBSY | AES_STATUS_PUSHERBSY | AES_STATUS_SOFTRSTBSY)) { in sli_radioaes_acquire()
Dsli_protocol_crypto_radioaes.c215 while (RADIOAES->STATUS & (AES_STATUS_FETCHERBSY | AES_STATUS_PUSHERBSY)) { in sli_radioaes_run_operation()
802 while (RADIOAES->STATUS & AES_STATUS_FETCHERBSY) { in sli_process_ble_rpa()
811 while (RADIOAES->STATUS & AES_STATUS_PUSHERBSY) { in sli_process_ble_rpa()
833 while (RADIOAES->STATUS & AES_STATUS_PUSHERBSY) { in sli_process_ble_rpa()

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