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Searched refs:PER_REG_BLOCK_CLR_OFFSET (Results 1 – 25 of 70) sorted by relevance

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/hal_silabs-3.6.0/gecko/emlib/inc/
Dem_bus.h146 #if defined(PER_REG_BLOCK_SET_OFFSET) && defined(PER_REG_BLOCK_CLR_OFFSET) in BUS_RegBitWrite()
151 aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; in BUS_RegBitWrite()
262 #if defined(PER_REG_BLOCK_CLR_OFFSET) in BUS_RegMaskedClear()
263 uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; in BUS_RegMaskedClear()
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c222f352gm40.h950 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32bg22c222f352gn32.h936 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32bg22c224f512gm32.h936 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32bg22c224f512gm40.h950 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32bg22c224f512gn32.h936 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32bg22c224f512im32.h936 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32bg22c224f512im40.h950 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32bg22c112f352gm32.h934 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32bg22c112f352gm40.h948 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32bg22c222f352gm32.h936 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h919 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32mg21a010f512im32.h919 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32mg21a010f768im32.h919 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32mg21a020f1024im32.h921 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32mg21a020f512im32.h921 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32mg21a020f768im32.h921 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32mg21b010f1024im32.h919 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32mg21b010f512im32.h919 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32mg21b010f768im32.h919 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32mg21b020f1024im32.h921 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32mg21b020f512im32.h921 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Defr32mg21b020f768im32.h921 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
Drm21z000f1024im32.h917 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27c140f768im32.h1002 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ macro

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