1 /***************************************************************************//** 2 * @file 3 * @brief Operational Amplifier (OPAMP) peripheral API 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #ifndef EM_OPAMP_H 32 #define EM_OPAMP_H 33 34 #include "em_device.h" 35 #if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ 36 || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include <stdint.h> 43 #include <stdbool.h> 44 45 #if defined(_SILICON_LABS_32B_SERIES_0) 46 #include "em_dac.h" 47 #elif defined (_SILICON_LABS_32B_SERIES_1) 48 #include "em_vdac.h" 49 #endif 50 51 /***************************************************************************//** 52 * @addtogroup opamp 53 * @{ 54 ******************************************************************************/ 55 56 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ 57 58 /** Validation of DAC OPA number for assert statements. */ 59 #if defined(_SILICON_LABS_32B_SERIES_0) 60 #define DAC_OPA_VALID(opa) ((opa) <= OPA2) 61 #elif defined(_SILICON_LABS_32B_SERIES_1) 62 #if defined(VDAC_STATUS_OPA3ENS) 63 #define VDAC_OPA_VALID(opa) ((opa) <= OPA3) 64 #elif defined(VDAC_STATUS_OPA2ENS) 65 #define VDAC_OPA_VALID(opa) ((opa) <= OPA2) 66 #elif defined(VDAC_STATUS_OPA1ENS) 67 #define VDAC_OPA_VALID(opa) ((opa) <= OPA1) 68 #else 69 #define VDAC_OPA_VALID(opa) ((opa) = OPA0) 70 #endif 71 #endif 72 73 /** @endcond */ 74 75 /******************************************************************************* 76 ******************************** ENUMS ************************************ 77 ******************************************************************************/ 78 79 /** OPAMP selector values. */ 80 typedef enum { 81 #if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA0ENS) 82 OPA0 = 0, /**< Select OPA0. */ 83 #endif 84 #if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA1ENS) 85 OPA1 = 1, /**< Select OPA1. */ 86 #endif 87 #if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA2ENS) 88 OPA2 = 2, /**< Select OPA2. */ 89 #endif 90 #if defined(VDAC_STATUS_OPA3ENS) 91 OPA3 = 3, /**< Select OPA3. */ 92 #endif 93 } OPAMP_TypeDef; 94 95 /** OPAMP negative terminal input selection values. */ 96 typedef enum { 97 #if defined(_SILICON_LABS_32B_SERIES_0) 98 opaNegSelDisable = DAC_OPA0MUX_NEGSEL_DISABLE, /**< Input disabled. */ 99 opaNegSelUnityGain = DAC_OPA0MUX_NEGSEL_UG, /**< Unity gain feedback path. */ 100 opaNegSelResTap = DAC_OPA0MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ 101 opaNegSelNegPad = DAC_OPA0MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ 102 #elif defined(_SILICON_LABS_32B_SERIES_1) 103 opaNegSelAPORT1YCH1 = VDAC_OPA_MUX_NEGSEL_APORT1YCH1, /**< APORT1YCH1 */ 104 opaNegSelAPORT1YCH3 = VDAC_OPA_MUX_NEGSEL_APORT1YCH3, /**< APORT1YCH3 */ 105 opaNegSelAPORT1YCH5 = VDAC_OPA_MUX_NEGSEL_APORT1YCH5, /**< APORT1YCH5 */ 106 opaNegSelAPORT1YCH7 = VDAC_OPA_MUX_NEGSEL_APORT1YCH7, /**< APORT1YCH7 */ 107 opaNegSelAPORT1YCH9 = VDAC_OPA_MUX_NEGSEL_APORT1YCH9, /**< APORT1YCH9 */ 108 opaNegSelAPORT1YCH11 = VDAC_OPA_MUX_NEGSEL_APORT1YCH11, /**< APORT1YCH11 */ 109 opaNegSelAPORT1YCH13 = VDAC_OPA_MUX_NEGSEL_APORT1YCH13, /**< APORT1YCH13 */ 110 opaNegSelAPORT1YCH15 = VDAC_OPA_MUX_NEGSEL_APORT1YCH15, /**< APORT1YCH15 */ 111 opaNegSelAPORT1YCH17 = VDAC_OPA_MUX_NEGSEL_APORT1YCH17, /**< APORT1YCH17 */ 112 opaNegSelAPORT1YCH19 = VDAC_OPA_MUX_NEGSEL_APORT1YCH19, /**< APORT1YCH19 */ 113 opaNegSelAPORT1YCH21 = VDAC_OPA_MUX_NEGSEL_APORT1YCH21, /**< APORT1YCH21 */ 114 opaNegSelAPORT1YCH23 = VDAC_OPA_MUX_NEGSEL_APORT1YCH23, /**< APORT1YCH23 */ 115 opaNegSelAPORT1YCH25 = VDAC_OPA_MUX_NEGSEL_APORT1YCH25, /**< APORT1YCH25 */ 116 opaNegSelAPORT1YCH27 = VDAC_OPA_MUX_NEGSEL_APORT1YCH27, /**< APORT1YCH27 */ 117 opaNegSelAPORT1YCH29 = VDAC_OPA_MUX_NEGSEL_APORT1YCH29, /**< APORT1YCH29 */ 118 opaNegSelAPORT1YCH31 = VDAC_OPA_MUX_NEGSEL_APORT1YCH31, /**< APORT1YCH31 */ 119 opaNegSelAPORT2YCH0 = VDAC_OPA_MUX_NEGSEL_APORT2YCH0, /**< APORT2YCH0 */ 120 opaNegSelAPORT2YCH2 = VDAC_OPA_MUX_NEGSEL_APORT2YCH2, /**< APORT2YCH2 */ 121 opaNegSelAPORT2YCH4 = VDAC_OPA_MUX_NEGSEL_APORT2YCH4, /**< APORT2YCH4 */ 122 opaNegSelAPORT2YCH6 = VDAC_OPA_MUX_NEGSEL_APORT2YCH6, /**< APORT2YCH6 */ 123 opaNegSelAPORT2YCH8 = VDAC_OPA_MUX_NEGSEL_APORT2YCH8, /**< APORT2YCH8 */ 124 opaNegSelAPORT2YCH10 = VDAC_OPA_MUX_NEGSEL_APORT2YCH10, /**< APORT2YCH10 */ 125 opaNegSelAPORT2YCH12 = VDAC_OPA_MUX_NEGSEL_APORT2YCH12, /**< APORT2YCH12 */ 126 opaNegSelAPORT2YCH14 = VDAC_OPA_MUX_NEGSEL_APORT2YCH14, /**< APORT2YCH14 */ 127 opaNegSelAPORT2YCH16 = VDAC_OPA_MUX_NEGSEL_APORT2YCH16, /**< APORT2YCH16 */ 128 opaNegSelAPORT2YCH18 = VDAC_OPA_MUX_NEGSEL_APORT2YCH18, /**< APORT2YCH18 */ 129 opaNegSelAPORT2YCH20 = VDAC_OPA_MUX_NEGSEL_APORT2YCH20, /**< APORT2YCH20 */ 130 opaNegSelAPORT2YCH22 = VDAC_OPA_MUX_NEGSEL_APORT2YCH22, /**< APORT2YCH22 */ 131 opaNegSelAPORT2YCH24 = VDAC_OPA_MUX_NEGSEL_APORT2YCH24, /**< APORT2YCH24 */ 132 opaNegSelAPORT2YCH26 = VDAC_OPA_MUX_NEGSEL_APORT2YCH26, /**< APORT2YCH26 */ 133 opaNegSelAPORT2YCH28 = VDAC_OPA_MUX_NEGSEL_APORT2YCH28, /**< APORT2YCH28 */ 134 opaNegSelAPORT2YCH30 = VDAC_OPA_MUX_NEGSEL_APORT2YCH30, /**< APORT2YCH30 */ 135 opaNegSelAPORT3YCH1 = VDAC_OPA_MUX_NEGSEL_APORT3YCH1, /**< APORT3YCH1 */ 136 opaNegSelAPORT3YCH3 = VDAC_OPA_MUX_NEGSEL_APORT3YCH3, /**< APORT3YCH3 */ 137 opaNegSelAPORT3YCH5 = VDAC_OPA_MUX_NEGSEL_APORT3YCH5, /**< APORT3YCH5 */ 138 opaNegSelAPORT3YCH7 = VDAC_OPA_MUX_NEGSEL_APORT3YCH7, /**< APORT3YCH7 */ 139 opaNegSelAPORT3YCH9 = VDAC_OPA_MUX_NEGSEL_APORT3YCH9, /**< APORT3YCH9 */ 140 opaNegSelAPORT3YCH11 = VDAC_OPA_MUX_NEGSEL_APORT3YCH11, /**< APORT3YCH11 */ 141 opaNegSelAPORT3YCH13 = VDAC_OPA_MUX_NEGSEL_APORT3YCH13, /**< APORT3YCH13 */ 142 opaNegSelAPORT3YCH15 = VDAC_OPA_MUX_NEGSEL_APORT3YCH15, /**< APORT3YCH15 */ 143 opaNegSelAPORT3YCH17 = VDAC_OPA_MUX_NEGSEL_APORT3YCH17, /**< APORT3YCH17 */ 144 opaNegSelAPORT3YCH19 = VDAC_OPA_MUX_NEGSEL_APORT3YCH19, /**< APORT3YCH19 */ 145 opaNegSelAPORT3YCH21 = VDAC_OPA_MUX_NEGSEL_APORT3YCH21, /**< APORT3YCH21 */ 146 opaNegSelAPORT3YCH23 = VDAC_OPA_MUX_NEGSEL_APORT3YCH23, /**< APORT3YCH23 */ 147 opaNegSelAPORT3YCH25 = VDAC_OPA_MUX_NEGSEL_APORT3YCH25, /**< APORT3YCH25 */ 148 opaNegSelAPORT3YCH27 = VDAC_OPA_MUX_NEGSEL_APORT3YCH27, /**< APORT3YCH27 */ 149 opaNegSelAPORT3YCH29 = VDAC_OPA_MUX_NEGSEL_APORT3YCH29, /**< APORT3YCH29 */ 150 opaNegSelAPORT3YCH31 = VDAC_OPA_MUX_NEGSEL_APORT3YCH31, /**< APORT3YCH31 */ 151 opaNegSelAPORT4YCH0 = VDAC_OPA_MUX_NEGSEL_APORT4YCH0, /**< APORT4YCH0 */ 152 opaNegSelAPORT4YCH2 = VDAC_OPA_MUX_NEGSEL_APORT4YCH2, /**< APORT4YCH2 */ 153 opaNegSelAPORT4YCH4 = VDAC_OPA_MUX_NEGSEL_APORT4YCH4, /**< APORT4YCH4 */ 154 opaNegSelAPORT4YCH6 = VDAC_OPA_MUX_NEGSEL_APORT4YCH6, /**< APORT4YCH6 */ 155 opaNegSelAPORT4YCH8 = VDAC_OPA_MUX_NEGSEL_APORT4YCH8, /**< APORT4YCH8 */ 156 opaNegSelAPORT4YCH10 = VDAC_OPA_MUX_NEGSEL_APORT4YCH10, /**< APORT4YCH10 */ 157 opaNegSelAPORT4YCH12 = VDAC_OPA_MUX_NEGSEL_APORT4YCH12, /**< APORT4YCH12 */ 158 opaNegSelAPORT4YCH14 = VDAC_OPA_MUX_NEGSEL_APORT4YCH14, /**< APORT4YCH14 */ 159 opaNegSelAPORT4YCH16 = VDAC_OPA_MUX_NEGSEL_APORT4YCH16, /**< APORT4YCH16 */ 160 opaNegSelAPORT4YCH18 = VDAC_OPA_MUX_NEGSEL_APORT4YCH18, /**< APORT4YCH18 */ 161 opaNegSelAPORT4YCH20 = VDAC_OPA_MUX_NEGSEL_APORT4YCH20, /**< APORT4YCH20 */ 162 opaNegSelAPORT4YCH22 = VDAC_OPA_MUX_NEGSEL_APORT4YCH22, /**< APORT4YCH22 */ 163 opaNegSelAPORT4YCH24 = VDAC_OPA_MUX_NEGSEL_APORT4YCH24, /**< APORT4YCH24 */ 164 opaNegSelAPORT4YCH26 = VDAC_OPA_MUX_NEGSEL_APORT4YCH26, /**< APORT4YCH26 */ 165 opaNegSelAPORT4YCH28 = VDAC_OPA_MUX_NEGSEL_APORT4YCH28, /**< APORT4YCH28 */ 166 opaNegSelAPORT4YCH30 = VDAC_OPA_MUX_NEGSEL_APORT4YCH30, /**< APORT4YCH30 */ 167 opaNegSelDisable = VDAC_OPA_MUX_NEGSEL_DISABLE, /**< Input disabled. */ 168 opaNegSelUnityGain = VDAC_OPA_MUX_NEGSEL_UG, /**< Unity gain feedback path. */ 169 opaNegSelResTap = VDAC_OPA_MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ 170 opaNegSelNegPad = VDAC_OPA_MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ 171 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ 172 } OPAMP_NegSel_TypeDef; 173 174 /** OPAMP positive terminal input selection values. */ 175 typedef enum { 176 #if defined(_SILICON_LABS_32B_SERIES_0) 177 opaPosSelDisable = DAC_OPA0MUX_POSSEL_DISABLE, /**< Input disabled. */ 178 opaPosSelDac = DAC_OPA0MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ 179 opaPosSelPosPad = DAC_OPA0MUX_POSSEL_POSPAD, /**< Positive pad as input. */ 180 opaPosSelOpaIn = DAC_OPA0MUX_POSSEL_OPA0INP, /**< Input from OPAx. */ 181 opaPosSelResTapOpa0 = DAC_OPA0MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap from OPA0. */ 182 #elif defined(_SILICON_LABS_32B_SERIES_1) 183 opaPosSelAPORT1XCH0 = VDAC_OPA_MUX_POSSEL_APORT1XCH0, /**< APORT1XCH0 */ 184 opaPosSelAPORT1XCH2 = VDAC_OPA_MUX_POSSEL_APORT1XCH2, /**< APORT1XCH2 */ 185 opaPosSelAPORT1XCH4 = VDAC_OPA_MUX_POSSEL_APORT1XCH4, /**< APORT1XCH4 */ 186 opaPosSelAPORT1XCH6 = VDAC_OPA_MUX_POSSEL_APORT1XCH6, /**< APORT1XCH6 */ 187 opaPosSelAPORT1XCH8 = VDAC_OPA_MUX_POSSEL_APORT1XCH8, /**< APORT1XCH8 */ 188 opaPosSelAPORT1XCH10 = VDAC_OPA_MUX_POSSEL_APORT1XCH10, /**< APORT1XCH10 */ 189 opaPosSelAPORT1XCH12 = VDAC_OPA_MUX_POSSEL_APORT1XCH12, /**< APORT1XCH12 */ 190 opaPosSelAPORT1XCH14 = VDAC_OPA_MUX_POSSEL_APORT1XCH14, /**< APORT1XCH14 */ 191 opaPosSelAPORT1XCH16 = VDAC_OPA_MUX_POSSEL_APORT1XCH16, /**< APORT1XCH16 */ 192 opaPosSelAPORT1XCH18 = VDAC_OPA_MUX_POSSEL_APORT1XCH18, /**< APORT1XCH18 */ 193 opaPosSelAPORT1XCH20 = VDAC_OPA_MUX_POSSEL_APORT1XCH20, /**< APORT1XCH20 */ 194 opaPosSelAPORT1XCH22 = VDAC_OPA_MUX_POSSEL_APORT1XCH22, /**< APORT1XCH22 */ 195 opaPosSelAPORT1XCH24 = VDAC_OPA_MUX_POSSEL_APORT1XCH24, /**< APORT1XCH24 */ 196 opaPosSelAPORT1XCH26 = VDAC_OPA_MUX_POSSEL_APORT1XCH26, /**< APORT1XCH26 */ 197 opaPosSelAPORT1XCH28 = VDAC_OPA_MUX_POSSEL_APORT1XCH28, /**< APORT1XCH28 */ 198 opaPosSelAPORT1XCH30 = VDAC_OPA_MUX_POSSEL_APORT1XCH30, /**< APORT1XCH30 */ 199 opaPosSelAPORT2XCH1 = VDAC_OPA_MUX_POSSEL_APORT2XCH1, /**< APORT2XCH1 */ 200 opaPosSelAPORT2XCH3 = VDAC_OPA_MUX_POSSEL_APORT2XCH3, /**< APORT2XCH3 */ 201 opaPosSelAPORT2XCH5 = VDAC_OPA_MUX_POSSEL_APORT2XCH5, /**< APORT2XCH5 */ 202 opaPosSelAPORT2XCH7 = VDAC_OPA_MUX_POSSEL_APORT2XCH7, /**< APORT2XCH7 */ 203 opaPosSelAPORT2XCH9 = VDAC_OPA_MUX_POSSEL_APORT2XCH9, /**< APORT2XCH9 */ 204 opaPosSelAPORT2XCH11 = VDAC_OPA_MUX_POSSEL_APORT2XCH11, /**< APORT2XCH11 */ 205 opaPosSelAPORT2XCH13 = VDAC_OPA_MUX_POSSEL_APORT2XCH13, /**< APORT2XCH13 */ 206 opaPosSelAPORT2XCH15 = VDAC_OPA_MUX_POSSEL_APORT2XCH15, /**< APORT2XCH15 */ 207 opaPosSelAPORT2XCH17 = VDAC_OPA_MUX_POSSEL_APORT2XCH17, /**< APORT2XCH17 */ 208 opaPosSelAPORT2XCH19 = VDAC_OPA_MUX_POSSEL_APORT2XCH19, /**< APORT2XCH19 */ 209 opaPosSelAPORT2XCH21 = VDAC_OPA_MUX_POSSEL_APORT2XCH21, /**< APORT2XCH21 */ 210 opaPosSelAPORT2XCH23 = VDAC_OPA_MUX_POSSEL_APORT2XCH23, /**< APORT2XCH23 */ 211 opaPosSelAPORT2XCH25 = VDAC_OPA_MUX_POSSEL_APORT2XCH25, /**< APORT2XCH25 */ 212 opaPosSelAPORT2XCH27 = VDAC_OPA_MUX_POSSEL_APORT2XCH27, /**< APORT2XCH27 */ 213 opaPosSelAPORT2XCH29 = VDAC_OPA_MUX_POSSEL_APORT2XCH29, /**< APORT2XCH29 */ 214 opaPosSelAPORT2XCH31 = VDAC_OPA_MUX_POSSEL_APORT2XCH31, /**< APORT2XCH31 */ 215 opaPosSelAPORT3XCH0 = VDAC_OPA_MUX_POSSEL_APORT3XCH0, /**< APORT3XCH0 */ 216 opaPosSelAPORT3XCH2 = VDAC_OPA_MUX_POSSEL_APORT3XCH2, /**< APORT3XCH2 */ 217 opaPosSelAPORT3XCH4 = VDAC_OPA_MUX_POSSEL_APORT3XCH4, /**< APORT3XCH4 */ 218 opaPosSelAPORT3XCH6 = VDAC_OPA_MUX_POSSEL_APORT3XCH6, /**< APORT3XCH6 */ 219 opaPosSelAPORT3XCH8 = VDAC_OPA_MUX_POSSEL_APORT3XCH8, /**< APORT3XCH8 */ 220 opaPosSelAPORT3XCH10 = VDAC_OPA_MUX_POSSEL_APORT3XCH10, /**< APORT3XCH10 */ 221 opaPosSelAPORT3XCH12 = VDAC_OPA_MUX_POSSEL_APORT3XCH12, /**< APORT3XCH12 */ 222 opaPosSelAPORT3XCH14 = VDAC_OPA_MUX_POSSEL_APORT3XCH14, /**< APORT3XCH14 */ 223 opaPosSelAPORT3XCH16 = VDAC_OPA_MUX_POSSEL_APORT3XCH16, /**< APORT3XCH16 */ 224 opaPosSelAPORT3XCH18 = VDAC_OPA_MUX_POSSEL_APORT3XCH18, /**< APORT3XCH18 */ 225 opaPosSelAPORT3XCH20 = VDAC_OPA_MUX_POSSEL_APORT3XCH20, /**< APORT3XCH20 */ 226 opaPosSelAPORT3XCH22 = VDAC_OPA_MUX_POSSEL_APORT3XCH22, /**< APORT3XCH22 */ 227 opaPosSelAPORT3XCH24 = VDAC_OPA_MUX_POSSEL_APORT3XCH24, /**< APORT3XCH24 */ 228 opaPosSelAPORT3XCH26 = VDAC_OPA_MUX_POSSEL_APORT3XCH26, /**< APORT3XCH26 */ 229 opaPosSelAPORT3XCH28 = VDAC_OPA_MUX_POSSEL_APORT3XCH28, /**< APORT3XCH28 */ 230 opaPosSelAPORT3XCH30 = VDAC_OPA_MUX_POSSEL_APORT3XCH30, /**< APORT3XCH30 */ 231 opaPosSelAPORT4XCH1 = VDAC_OPA_MUX_POSSEL_APORT4XCH1, /**< APORT4XCH1 */ 232 opaPosSelAPORT4XCH3 = VDAC_OPA_MUX_POSSEL_APORT4XCH3, /**< APORT4XCH3 */ 233 opaPosSelAPORT4XCH5 = VDAC_OPA_MUX_POSSEL_APORT4XCH5, /**< APORT4XCH5 */ 234 opaPosSelAPORT4XCH7 = VDAC_OPA_MUX_POSSEL_APORT4XCH7, /**< APORT4XCH7 */ 235 opaPosSelAPORT4XCH9 = VDAC_OPA_MUX_POSSEL_APORT4XCH9, /**< APORT4XCH9 */ 236 opaPosSelAPORT4XCH11 = VDAC_OPA_MUX_POSSEL_APORT4XCH11, /**< APORT4XCH11 */ 237 opaPosSelAPORT4XCH13 = VDAC_OPA_MUX_POSSEL_APORT4XCH13, /**< APORT4XCH13 */ 238 opaPosSelAPORT4XCH15 = VDAC_OPA_MUX_POSSEL_APORT4XCH15, /**< APORT4XCH15 */ 239 opaPosSelAPORT4XCH17 = VDAC_OPA_MUX_POSSEL_APORT4XCH17, /**< APORT4XCH17 */ 240 opaPosSelAPORT4XCH19 = VDAC_OPA_MUX_POSSEL_APORT4XCH19, /**< APORT4XCH19 */ 241 opaPosSelAPORT4XCH21 = VDAC_OPA_MUX_POSSEL_APORT4XCH21, /**< APORT4XCH21 */ 242 opaPosSelAPORT4XCH23 = VDAC_OPA_MUX_POSSEL_APORT4XCH23, /**< APORT4XCH23 */ 243 opaPosSelAPORT4XCH25 = VDAC_OPA_MUX_POSSEL_APORT4XCH25, /**< APORT4XCH25 */ 244 opaPosSelAPORT4XCH27 = VDAC_OPA_MUX_POSSEL_APORT4XCH27, /**< APORT4XCH27 */ 245 opaPosSelAPORT4XCH29 = VDAC_OPA_MUX_POSSEL_APORT4XCH29, /**< APORT4XCH29 */ 246 opaPosSelAPORT4XCH31 = VDAC_OPA_MUX_POSSEL_APORT4XCH31, /**< APORT4XCH31 */ 247 opaPosSelDisable = VDAC_OPA_MUX_POSSEL_DISABLE, /**< Input disabled. */ 248 opaPosSelDac = VDAC_OPA_MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ 249 opaPosSelPosPad = VDAC_OPA_MUX_POSSEL_POSPAD, /**< Positive pad as input. */ 250 opaPosSelOpaIn = VDAC_OPA_MUX_POSSEL_OPANEXT, /**< Input from OPAx. */ 251 opaPosSelResTap = VDAC_OPA_MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap. */ 252 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ 253 } OPAMP_PosSel_TypeDef; 254 255 /** OPAMP output terminal selection values. */ 256 typedef enum { 257 #if defined(_SILICON_LABS_32B_SERIES_0) 258 opaOutModeDisable = DAC_OPA0MUX_OUTMODE_DISABLE, /**< OPA output disabled. */ 259 opaOutModeMain = DAC_OPA0MUX_OUTMODE_MAIN, /**< Main output to pin enabled. */ 260 opaOutModeAlt = DAC_OPA0MUX_OUTMODE_ALT, /**< Alternate output(s) enabled (not OPA2). */ 261 opaOutModeAll = DAC_OPA0MUX_OUTMODE_ALL /**< Both main and alternate enabled (not OPA2). */ 262 #elif defined(_SILICON_LABS_32B_SERIES_1) 263 opaOutModeDisable = 0, /**< OPA output disabled. */ 264 opaOutModeMain = VDAC_OPA_OUT_MAINOUTEN, /**< Main output to pin enabled. */ 265 opaOutModeAlt = VDAC_OPA_OUT_ALTOUTEN, /**< Alternate output(s) enabled (not OPA2). */ 266 opaOutModeAll = VDAC_OPA_OUT_SHORT, /**< Both main and alternate enabled (not OPA2). */ 267 opaOutModeAPORT1YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1), /**< APORT output to APORT1YCH1 pin enabled. */ 268 opaOutModeAPORT1YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3), /**< APORT output to APORT1YCH3 pin enabled. */ 269 opaOutModeAPORT1YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5), /**< APORT output to APORT1YCH5 pin enabled. */ 270 opaOutModeAPORT1YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7), /**< APORT output to APORT1YCH7 pin enabled. */ 271 opaOutModeAPORT1YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9), /**< APORT output to APORT1YCH9 pin enabled. */ 272 opaOutModeAPORT1YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11), /**< APORT output to APORT1YCH11 pin enabled. */ 273 opaOutModeAPORT1YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13), /**< APORT output to APORT1YCH13 pin enabled. */ 274 opaOutModeAPORT1YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15), /**< APORT output to APORT1YCH15 pin enabled. */ 275 opaOutModeAPORT1YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17), /**< APORT output to APORT1YCH17 pin enabled. */ 276 opaOutModeAPORT1YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19), /**< APORT output to APORT1YCH19 pin enabled. */ 277 opaOutModeAPORT1YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21), /**< APORT output to APORT1YCH21 pin enabled. */ 278 opaOutModeAPORT1YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23), /**< APORT output to APORT1YCH23 pin enabled. */ 279 opaOutModeAPORT1YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25), /**< APORT output to APORT1YCH25 pin enabled. */ 280 opaOutModeAPORT1YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27), /**< APORT output to APORT1YCH27 pin enabled. */ 281 opaOutModeAPORT1YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29), /**< APORT output to APORT1YCH29 pin enabled. */ 282 opaOutModeAPORT1YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31), /**< APORT output to APORT1YCH31 pin enabled. */ 283 opaOutModeAPORT2YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0), /**< APORT output to APORT2YCH0 pin enabled. */ 284 opaOutModeAPORT2YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2), /**< APORT output to APORT2YCH2 pin enabled. */ 285 opaOutModeAPORT2YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4), /**< APORT output to APORT2YCH4 pin enabled. */ 286 opaOutModeAPORT2YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6), /**< APORT output to APORT2YCH6 pin enabled. */ 287 opaOutModeAPORT2YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8), /**< APORT output to APORT2YCH8 pin enabled. */ 288 opaOutModeAPORT2YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10), /**< APORT output to APORT2YCH10 pin enabled. */ 289 opaOutModeAPORT2YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12), /**< APORT output to APORT2YCH12 pin enabled. */ 290 opaOutModeAPORT2YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14), /**< APORT output to APORT2YCH14 pin enabled. */ 291 opaOutModeAPORT2YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16), /**< APORT output to APORT2YCH16 pin enabled. */ 292 opaOutModeAPORT2YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18), /**< APORT output to APORT2YCH18 pin enabled. */ 293 opaOutModeAPORT2YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20), /**< APORT output to APORT2YCH20 pin enabled. */ 294 opaOutModeAPORT2YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22), /**< APORT output to APORT2YCH22 pin enabled. */ 295 opaOutModeAPORT2YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24), /**< APORT output to APORT2YCH24 pin enabled. */ 296 opaOutModeAPORT2YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26), /**< APORT output to APORT2YCH26 pin enabled. */ 297 opaOutModeAPORT2YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28), /**< APORT output to APORT2YCH28 pin enabled. */ 298 opaOutModeAPORT2YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30), /**< APORT output to APORT2YCH30 pin enabled. */ 299 opaOutModeAPORT3YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1), /**< APORT output to APORT3YCH1 pin enabled. */ 300 opaOutModeAPORT3YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3), /**< APORT output to APORT3YCH3 pin enabled. */ 301 opaOutModeAPORT3YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5), /**< APORT output to APORT3YCH5 pin enabled. */ 302 opaOutModeAPORT3YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7), /**< APORT output to APORT3YCH7 pin enabled. */ 303 opaOutModeAPORT3YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9), /**< APORT output to APORT3YCH9 pin enabled. */ 304 opaOutModeAPORT3YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11), /**< APORT output to APORT3YCH11 pin enabled. */ 305 opaOutModeAPORT3YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13), /**< APORT output to APORT3YCH13 pin enabled. */ 306 opaOutModeAPORT3YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15), /**< APORT output to APORT3YCH15 pin enabled. */ 307 opaOutModeAPORT3YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17), /**< APORT output to APORT3YCH17 pin enabled. */ 308 opaOutModeAPORT3YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19), /**< APORT output to APORT3YCH19 pin enabled. */ 309 opaOutModeAPORT3YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21), /**< APORT output to APORT3YCH21 pin enabled. */ 310 opaOutModeAPORT3YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23), /**< APORT output to APORT3YCH23 pin enabled. */ 311 opaOutModeAPORT3YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25), /**< APORT output to APORT3YCH25 pin enabled. */ 312 opaOutModeAPORT3YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27), /**< APORT output to APORT3YCH27 pin enabled. */ 313 opaOutModeAPORT3YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29), /**< APORT output to APORT3YCH29 pin enabled. */ 314 opaOutModeAPORT3YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31), /**< APORT output to APORT3YCH31 pin enabled. */ 315 opaOutModeAPORT4YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0), /**< APORT output to APORT4YCH0 pin enabled. */ 316 opaOutModeAPORT4YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2), /**< APORT output to APORT4YCH2 pin enabled. */ 317 opaOutModeAPORT4YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4), /**< APORT output to APORT4YCH4 pin enabled. */ 318 opaOutModeAPORT4YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6), /**< APORT output to APORT4YCH6 pin enabled. */ 319 opaOutModeAPORT4YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8), /**< APORT output to APORT4YCH8 pin enabled. */ 320 opaOutModeAPORT4YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10), /**< APORT output to APORT4YCH10 pin enabled. */ 321 opaOutModeAPORT4YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12), /**< APORT output to APORT4YCH12 pin enabled. */ 322 opaOutModeAPORT4YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14), /**< APORT output to APORT4YCH14 pin enabled. */ 323 opaOutModeAPORT4YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16), /**< APORT output to APORT4YCH16 pin enabled. */ 324 opaOutModeAPORT4YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18), /**< APORT output to APORT4YCH18 pin enabled. */ 325 opaOutModeAPORT4YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20), /**< APORT output to APORT4YCH20 pin enabled. */ 326 opaOutModeAPORT4YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22), /**< APORT output to APORT4YCH22 pin enabled. */ 327 opaOutModeAPORT4YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24), /**< APORT output to APORT4YCH24 pin enabled. */ 328 opaOutModeAPORT4YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26), /**< APORT output to APORT4YCH26 pin enabled. */ 329 opaOutModeAPORT4YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28), /**< APORT output to APORT4YCH28 pin enabled. */ 330 opaOutModeAPORT4YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30), /**< APORT output to APORT4YCH30 pin enabled. */ 331 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ 332 } OPAMP_OutMode_TypeDef; 333 334 /** OPAMP gain values. */ 335 typedef enum { 336 #if defined(_SILICON_LABS_32B_SERIES_0) 337 opaResSelDefault = DAC_OPA0MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ 338 opaResSelR2eq0_33R1 = DAC_OPA0MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ 339 opaResSelR2eqR1 = DAC_OPA0MUX_RESSEL_RES1, /**< R2 = R1 */ 340 opaResSelR1eq1_67R1 = DAC_OPA0MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */ 341 opaResSelR2eq2R1 = DAC_OPA0MUX_RESSEL_RES3, /**< R2 = 2 * R1 */ 342 opaResSelR2eq3R1 = DAC_OPA0MUX_RESSEL_RES4, /**< R2 = 3 * R1 */ 343 opaResSelR2eq4_33R1 = DAC_OPA0MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ 344 opaResSelR2eq7R1 = DAC_OPA0MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ 345 opaResSelR2eq15R1 = DAC_OPA0MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ 346 #elif defined(_SILICON_LABS_32B_SERIES_1) 347 opaResSelDefault = VDAC_OPA_MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ 348 opaResSelR2eq0_33R1 = VDAC_OPA_MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ 349 opaResSelR2eqR1 = VDAC_OPA_MUX_RESSEL_RES1, /**< R2 = R1 */ 350 opaResSelR1eq1_67R1 = VDAC_OPA_MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */ 351 opaResSelR2eq2_2R1 = VDAC_OPA_MUX_RESSEL_RES3, /**< R2 = 2.2 * R1 */ 352 opaResSelR2eq3R1 = VDAC_OPA_MUX_RESSEL_RES4, /**< R2 = 3 * R1 */ 353 opaResSelR2eq4_33R1 = VDAC_OPA_MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ 354 opaResSelR2eq7R1 = VDAC_OPA_MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ 355 opaResSelR2eq15R1 = VDAC_OPA_MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ 356 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ 357 } OPAMP_ResSel_TypeDef; 358 359 /** OPAMP resistor ladder input selector values. */ 360 typedef enum { 361 #if defined(_SILICON_LABS_32B_SERIES_0) 362 opaResInMuxDisable = DAC_OPA0MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ 363 opaResInMuxOpaIn = DAC_OPA0MUX_RESINMUX_OPA0INP, /**< Input from OPAx. */ 364 opaResInMuxNegPad = DAC_OPA0MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ 365 opaResInMuxPosPad = DAC_OPA0MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ 366 opaResInMuxVss = DAC_OPA0MUX_RESINMUX_VSS /**< Input connected to Vss. */ 367 #elif defined(_SILICON_LABS_32B_SERIES_1) 368 opaResInMuxDisable = VDAC_OPA_MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ 369 opaResInMuxOpaIn = VDAC_OPA_MUX_RESINMUX_OPANEXT, /**< Input from OPAx. */ 370 opaResInMuxNegPad = VDAC_OPA_MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ 371 opaResInMuxPosPad = VDAC_OPA_MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ 372 opaResInMuxComPad = VDAC_OPA_MUX_RESINMUX_COMPAD, /**< Input from negative pad of OPA0. 373 Direct input to support common reference. */ 374 opaResInMuxCenter = VDAC_OPA_MUX_RESINMUX_CENTER, /**< OPA0 and OPA1 Resmux connected to form fully 375 differential instrumentation amplifier. */ 376 opaResInMuxVss = VDAC_OPA_MUX_RESINMUX_VSS, /**< Input connected to Vss. */ 377 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ 378 } OPAMP_ResInMux_TypeDef; 379 380 #if defined(_SILICON_LABS_32B_SERIES_1) 381 /** OPAMP PRS Mode. */ 382 typedef enum { 383 opaPrsModeDefault = VDAC_OPA_CTRL_PRSMODE_DEFAULT, /**< Default value when PRS is not the trigger. */ 384 opaPrsModePulsed = VDAC_OPA_CTRL_PRSMODE_PULSED, /**< PRS trigger is a pulse that starts the OPAMP 385 warmup sequence. The end of the warmup sequence 386 is controlled by timeout settings in OPAxTIMER. */ 387 opaPrsModeTimed = VDAC_OPA_CTRL_PRSMODE_TIMED, /**< PRS trigger is a pulse long enough to provide the 388 OPAMP warmup sequence. The end of the warmup 389 sequence is controlled by the edge of the pulse. */ 390 } OPAMP_PrsMode_TypeDef; 391 392 /** OPAMP PRS Selection. */ 393 typedef enum { 394 opaPrsSelDefault = VDAC_OPA_CTRL_PRSSEL_DEFAULT, /**< Default value when PRS is not the trigger. */ 395 opaPrsSelCh0 = VDAC_OPA_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0 triggers OPAMP. */ 396 opaPrsSelCh1 = VDAC_OPA_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1 triggers OPAMP. */ 397 opaPrsSelCh2 = VDAC_OPA_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2 triggers OPAMP. */ 398 opaPrsSelCh3 = VDAC_OPA_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3 triggers OPAMP. */ 399 opaPrsSelCh4 = VDAC_OPA_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4 triggers OPAMP. */ 400 opaPrsSelCh5 = VDAC_OPA_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5 triggers OPAMP. */ 401 opaPrsSelCh6 = VDAC_OPA_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6 triggers OPAMP. */ 402 opaPrsSelCh7 = VDAC_OPA_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7 triggers OPAMP. */ 403 #if defined(VDAC_OPA_CTRL_PRSSEL_PRSCH8) 404 opaPrsSelCh8 = VDAC_OPA_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8 triggers OPAMP. */ 405 opaPrsSelCh9 = VDAC_OPA_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9 triggers OPAMP. */ 406 opaPrsSelCh10 = VDAC_OPA_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10 triggers OPAMP. */ 407 opaPrsSelCh11 = VDAC_OPA_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11 triggers OPAMP. */ 408 #endif 409 } OPAMP_PrsSel_TypeDef; 410 411 /** OPAMP PRS Output. */ 412 typedef enum { 413 opaPrsOutDefault = VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT, /**< Default value. */ 414 opaPrsOutWarm = VDAC_OPA_CTRL_PRSOUTMODE_WARM, /**< Warm status available on PRS. */ 415 opaPrsOutOutValid = VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID, /**< Outvalid status available on PRS. */ 416 } OPAMP_PrsOut_TypeDef; 417 418 /** OPAMP Output Scaling. */ 419 typedef enum { 420 opaOutScaleDefault = VDAC_OPA_CTRL_OUTSCALE_DEFAULT, /**< Default OPAM output drive strength. */ 421 opaOutScaleFull = VDAC_OPA_CTRL_OUTSCALE_FULL, /**< OPAMP uses full output drive strength. */ 422 opaOutSacleHalf = VDAC_OPA_CTRL_OUTSCALE_HALF, /**< OPAMP uses half output drive strength. */ 423 } OPAMP_OutScale_Typedef; 424 425 /** OPAMP Drive Strength. */ 426 typedef enum { 427 opaDrvStrDefault = VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT, /**< Default value. */ 428 opaDrvStrLowerAccLowStr = (0 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Lower accuracy with low drive strength. */ 429 opaDrvStrLowAccLowStr = (1 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Low accuracy with low drive strength. */ 430 opaDrvStrHighAccHighStr = (2 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< High accuracy with high drive strength. */ 431 opaDrvStrHigherAccHighStr = (3 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Higher accuracy with high drive strength. */ 432 } OPAMP_DrvStr_Typedef; 433 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ 434 435 /******************************************************************************* 436 ******************************* STRUCTS *********************************** 437 ******************************************************************************/ 438 439 /** OPAMP init structure. */ 440 typedef struct { 441 OPAMP_NegSel_TypeDef negSel; /**< Select input source for negative terminal. */ 442 OPAMP_PosSel_TypeDef posSel; /**< Select input source for positive terminal. */ 443 OPAMP_OutMode_TypeDef outMode; /**< Output terminal connection. */ 444 OPAMP_ResSel_TypeDef resSel; /**< Select R2/R1 resistor ratio. */ 445 OPAMP_ResInMux_TypeDef resInMux; /**< Select input source for resistor ladder. */ 446 uint32_t outPen; /**< Alternate output enable bit mask. This value 447 should consist one or more of the 448 @if DOXYDOC_P1_DEVICE 449 DAC_OPA[opa#]MUX_OUTPEN_OUT[output#] flags 450 (defined in \<part_name\>_dac.h) OR'ed together. 451 @n @n 452 For OPA0: 453 @li DAC_OPA0MUX_OUTPEN_OUT0 454 @li DAC_OPA0MUX_OUTPEN_OUT1 455 @li DAC_OPA0MUX_OUTPEN_OUT2 456 @li DAC_OPA0MUX_OUTPEN_OUT3 457 @li DAC_OPA0MUX_OUTPEN_OUT4 458 459 For OPA1: 460 @li DAC_OPA1MUX_OUTPEN_OUT0 461 @li DAC_OPA1MUX_OUTPEN_OUT1 462 @li DAC_OPA1MUX_OUTPEN_OUT2 463 @li DAC_OPA1MUX_OUTPEN_OUT3 464 @li DAC_OPA1MUX_OUTPEN_OUT4 465 466 For OPA2: 467 @li DAC_OPA2MUX_OUTPEN_OUT0 468 @li DAC_OPA2MUX_OUTPEN_OUT1 469 470 E.g: @n 471 init.outPen = DAC_OPA0MUX_OUTPEN_OUT0 | 472 DAC_OPA0MUX_OUTPEN_OUT2 | 473 DAC_OPA0MUX_OUTPEN_OUT4; 474 475 @elseif DOXYDOC_P2_DEVICE 476 VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags 477 (defined in \<part_name\>_vdac.h) OR'ed together. 478 @n @n 479 @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 480 @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 481 @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 482 @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 483 @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 484 485 E.g: @n 486 init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | 487 VDAC_OPA_OUT_ALTOUTPADEN_OUT2 | 488 VDAC_OPA_OUT_ALTOUTPADEN_OUT4; 489 @endif */ 490 #if defined(_SILICON_LABS_32B_SERIES_0) 491 uint32_t bias; /**< Set OPAMP bias current. */ 492 bool halfBias; /**< Divide OPAMP bias current by 2. */ 493 bool lpfPosPadDisable; /**< Disable low pass filter on positive pad. */ 494 bool lpfNegPadDisable; /**< Disable low pass filter on negative pad. */ 495 bool nextOut; /**< Enable NEXTOUT signal source. */ 496 bool npEn; /**< Enable positive pad. */ 497 bool ppEn; /**< Enable negative pad. */ 498 bool shortInputs; /**< Short OPAMP input terminals. */ 499 bool hcmDisable; /**< Disable input rail-to-rail capability. */ 500 bool defaultOffset; /**< Use factory calibrated opamp offset value. */ 501 uint32_t offset; /**< Opamp offset value when @ref defaultOffset is 502 false. */ 503 #elif defined(_SILICON_LABS_32B_SERIES_1) 504 OPAMP_DrvStr_Typedef drvStr; /**< OPAx operation mode. */ 505 bool gain3xEn; /**< Enable 3x gain resistor ladder. */ 506 bool halfDrvStr; /**< Half or full output drive strength. */ 507 bool ugBwScale; /**< Unity gain bandwidth scaled by factor of 2.5. */ 508 bool prsEn; /**< Enable PRS as OPAMP trigger. */ 509 OPAMP_PrsMode_TypeDef prsMode; /**< Selects PRS trigger mode. */ 510 OPAMP_PrsSel_TypeDef prsSel; /**< PRS channel trigger select. */ 511 OPAMP_PrsOut_TypeDef prsOutSel; /**< PRS output select. */ 512 bool aportYMasterDisable; /**< Disable bus master request on APORT Y. */ 513 bool aportXMasterDisable; /**< Disable bus master request on APORT X. */ 514 uint32_t settleTime; /**< Number of clock cycles to drive the output. */ 515 uint32_t startupDly; /**< OPAx startup delay in microseconds. */ 516 bool hcmDisable; /**< Disable input rail-to-rail capability. */ 517 bool defaultOffsetN; /**< Use factory calibrated opamp inverting input 518 offset value. */ 519 uint32_t offsetN; /**< Opamp inverting input offset value when 520 @ref defaultOffsetN is false. */ 521 bool defaultOffsetP; /**< Use factory calibrated opamp non-inverting 522 input offset value. */ 523 uint32_t offsetP; /**< Opamp non-inverting input offset value when 524 @ref defaultOffsetP is false. */ 525 #endif /* defined(_SILICON_LABS_32B_SERIES_1) */ 526 } OPAMP_Init_TypeDef; 527 528 #if defined(_SILICON_LABS_32B_SERIES_0) 529 /** Configuration of OPA0/1 in unity gain voltage follower mode. */ 530 #define OPA_INIT_UNITY_GAIN \ 531 { \ 532 opaNegSelUnityGain, /* Unity gain. */ \ 533 opaPosSelPosPad, /* Positive input from pad. */ \ 534 opaOutModeMain, /* Main output enabled. */ \ 535 opaResSelDefault, /* Resistor ladder is not used. */ \ 536 opaResInMuxDisable, /* Resistor ladder disabled. */ \ 537 0, /* No alternate outputs enabled. */ \ 538 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 539 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 540 false, /* No low pass filter on positive pad. */ \ 541 false, /* No low pass filter on negative pad. */ \ 542 false, /* No nextout output enabled. */ \ 543 false, /* Negative pad disabled. */ \ 544 true, /* Positive pad enabled, used as signal input. */ \ 545 false, /* No shorting of inputs. */ \ 546 false, /* Rail-to-rail input enabled. */ \ 547 true, /* Use factory calibrated opamp offset. */ \ 548 0 /* Opamp offset value (not used). */ \ 549 } 550 551 /** Configuration of OPA2 in unity gain voltage follower mode. */ 552 #define OPA_INIT_UNITY_GAIN_OPA2 \ 553 { \ 554 opaNegSelUnityGain, /* Unity gain. */ \ 555 opaPosSelPosPad, /* Positive input from pad. */ \ 556 opaOutModeMain, /* Main output enabled. */ \ 557 opaResSelDefault, /* Resistor ladder is not used. */ \ 558 opaResInMuxDisable, /* Resistor ladder disabled. */ \ 559 DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ 560 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 561 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 562 false, /* No low pass filter on positive pad. */ \ 563 false, /* No low pass filter on negative pad. */ \ 564 false, /* No nextout output enabled. */ \ 565 false, /* Negative pad disabled. */ \ 566 true, /* Positive pad enabled, used as signal input. */ \ 567 false, /* No shorting of inputs. */ \ 568 false, /* Rail-to-rail input enabled. */ \ 569 true, /* Use factory calibrated opamp offset. */ \ 570 0 /* Opamp offset value (not used). */ \ 571 } 572 573 /** Configuration of OPA0/1 in non-inverting amplifier mode. */ 574 #define OPA_INIT_NON_INVERTING \ 575 { \ 576 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 577 opaPosSelPosPad, /* Positive input from pad. */ \ 578 opaOutModeMain, /* Main output enabled. */ \ 579 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ 580 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 581 0, /* No alternate outputs enabled. */ \ 582 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 583 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 584 false, /* No low pass filter on positive pad. */ \ 585 false, /* No low pass filter on negative pad. */ \ 586 false, /* No nextout output enabled. */ \ 587 true, /* Negative pad enabled, used as signal ground. */ \ 588 true, /* Positive pad enabled, used as signal input. */ \ 589 false, /* No shorting of inputs. */ \ 590 false, /* Rail-to-rail input enabled. */ \ 591 true, /* Use factory calibrated opamp offset. */ \ 592 0 /* Opamp offset value (not used). */ \ 593 } 594 595 /** Configuration of OPA2 in non-inverting amplifier mode. */ 596 #define OPA_INIT_NON_INVERTING_OPA2 \ 597 { \ 598 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 599 opaPosSelPosPad, /* Positive input from pad. */ \ 600 opaOutModeMain, /* Main output enabled. */ \ 601 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ 602 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 603 DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ 604 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 605 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 606 false, /* No low pass filter on positive pad. */ \ 607 false, /* No low pass filter on negative pad. */ \ 608 false, /* No nextout output enabled. */ \ 609 true, /* Negative pad enabled, used as signal ground. */ \ 610 true, /* Positive pad enabled, used as signal input. */ \ 611 false, /* No shorting of inputs. */ \ 612 false, /* Rail-to-rail input enabled. */ \ 613 true, /* Use factory calibrated opamp offset. */ \ 614 0 /* Opamp offset value (not used). */ \ 615 } 616 617 /** Configuration of OPA0/1 in inverting amplifier mode. */ 618 #define OPA_INIT_INVERTING \ 619 { \ 620 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 621 opaPosSelPosPad, /* Positive input from pad. */ \ 622 opaOutModeMain, /* Main output enabled. */ \ 623 opaResSelR2eqR1, /* R2 = R1 */ \ 624 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 625 0, /* No alternate outputs enabled. */ \ 626 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 627 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 628 false, /* No low pass filter on positive pad. */ \ 629 false, /* No low pass filter on negative pad. */ \ 630 false, /* No nextout output enabled. */ \ 631 true, /* Negative pad enabled, used as signal input. */ \ 632 true, /* Positive pad enabled, used as signal ground. */ \ 633 false, /* No shorting of inputs. */ \ 634 false, /* Rail-to-rail input enabled. */ \ 635 true, /* Use factory calibrated opamp offset. */ \ 636 0 /* Opamp offset value (not used). */ \ 637 } 638 639 /** Configuration of OPA2 in inverting amplifier mode. */ 640 #define OPA_INIT_INVERTING_OPA2 \ 641 { \ 642 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 643 opaPosSelPosPad, /* Positive input from pad. */ \ 644 opaOutModeMain, /* Main output enabled. */ \ 645 opaResSelR2eqR1, /* R2 = R1 */ \ 646 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 647 DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ 648 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 649 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 650 false, /* No low pass filter on positive pad. */ \ 651 false, /* No low pass filter on negative pad. */ \ 652 false, /* No nextout output enabled. */ \ 653 true, /* Negative pad enabled, used as signal input. */ \ 654 true, /* Positive pad enabled, used as signal ground. */ \ 655 false, /* No shorting of inputs. */ \ 656 false, /* Rail-to-rail input enabled. */ \ 657 true, /* Use factory calibrated opamp offset. */ \ 658 0 /* Opamp offset value (not used). */ \ 659 } 660 661 /** Configuration of OPA0 in cascaded non-inverting amplifier mode. */ 662 #define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \ 663 { \ 664 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 665 opaPosSelPosPad, /* Positive input from pad. */ \ 666 opaOutModeAll, /* Both main and alternate outputs. */ \ 667 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ 668 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 669 0, /* No alternate outputs enabled. */ \ 670 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 671 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 672 false, /* No low pass filter on positive pad. */ \ 673 false, /* No low pass filter on negative pad. */ \ 674 true, /* Pass output to next stage (OPA1). */ \ 675 true, /* Negative pad enabled, used as signal ground. */ \ 676 true, /* Positive pad enabled, used as signal input. */ \ 677 false, /* No shorting of inputs. */ \ 678 false, /* Rail-to-rail input enabled. */ \ 679 true, /* Use factory calibrated opamp offset. */ \ 680 0 /* Opamp offset value (not used). */ \ 681 } 682 683 /** Configuration of OPA1 in cascaded non-inverting amplifier mode. */ 684 #define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \ 685 { \ 686 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 687 opaPosSelOpaIn, /* Positive input from OPA0 output. */ \ 688 opaOutModeAll, /* Both main and alternate outputs. */ \ 689 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ 690 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 691 0, /* No alternate outputs enabled. */ \ 692 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 693 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 694 false, /* No low pass filter on positive pad. */ \ 695 false, /* No low pass filter on negative pad. */ \ 696 true, /* Pass output to next stage (OPA2). */ \ 697 true, /* Negative pad enabled, used as signal ground. */ \ 698 false, /* Positive pad disabled. */ \ 699 false, /* No shorting of inputs. */ \ 700 false, /* Rail-to-rail input enabled. */ \ 701 true, /* Use factory calibrated opamp offset. */ \ 702 0 /* Opamp offset value (not used). */ \ 703 } 704 705 /** Configuration of OPA2 in cascaded non-inverting amplifier mode. */ 706 #define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \ 707 { \ 708 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 709 opaPosSelOpaIn, /* Positive input from OPA1 output. */ \ 710 opaOutModeMain, /* Main output enabled. */ \ 711 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ 712 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 713 DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ 714 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 715 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 716 false, /* No low pass filter on positive pad. */ \ 717 false, /* No low pass filter on negative pad. */ \ 718 false, /* No nextout output enabled. */ \ 719 true, /* Negative pad enabled, used as signal ground. */ \ 720 false, /* Positive pad disabled. */ \ 721 false, /* No shorting of inputs. */ \ 722 false, /* Rail-to-rail input enabled. */ \ 723 true, /* Use factory calibrated opamp offset. */ \ 724 0 /* Opamp offset value (not used). */ \ 725 } 726 727 /** Configuration of OPA0 in cascaded inverting amplifier mode. */ 728 #define OPA_INIT_CASCADED_INVERTING_OPA0 \ 729 { \ 730 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 731 opaPosSelPosPad, /* Positive input from pad. */ \ 732 opaOutModeAll, /* Both main and alternate outputs. */ \ 733 opaResSelR2eqR1, /* R2 = R1 */ \ 734 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 735 0, /* No alternate outputs enabled. */ \ 736 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 737 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 738 false, /* No low pass filter on positive pad. */ \ 739 false, /* No low pass filter on negative pad. */ \ 740 true, /* Pass output to next stage (OPA1). */ \ 741 true, /* Negative pad enabled, used as signal input. */ \ 742 true, /* Positive pad enabled, used as signal ground. */ \ 743 false, /* No shorting of inputs. */ \ 744 false, /* Rail-to-rail input enabled. */ \ 745 true, /* Use factory calibrated opamp offset. */ \ 746 0 /* Opamp offset value (not used). */ \ 747 } 748 749 /** Configuration of OPA1 in cascaded inverting amplifier mode. */ 750 #define OPA_INIT_CASCADED_INVERTING_OPA1 \ 751 { \ 752 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 753 opaPosSelPosPad, /* Positive input from pad. */ \ 754 opaOutModeAll, /* Both main and alternate outputs. */ \ 755 opaResSelR2eqR1, /* R2 = R1 */ \ 756 opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ 757 0, /* No alternate outputs enabled. */ \ 758 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 759 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 760 false, /* No low pass filter on positive pad. */ \ 761 false, /* No low pass filter on negative pad. */ \ 762 true, /* Pass output to next stage (OPA2). */ \ 763 false, /* Negative pad disabled. */ \ 764 true, /* Positive pad enabled, used as signal ground. */ \ 765 false, /* No shorting of inputs. */ \ 766 false, /* Rail-to-rail input enabled. */ \ 767 true, /* Use factory calibrated opamp offset. */ \ 768 0 /* Opamp offset value (not used). */ \ 769 } 770 771 /** Configuration of OPA2 in cascaded inverting amplifier mode. */ 772 #define OPA_INIT_CASCADED_INVERTING_OPA2 \ 773 { \ 774 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 775 opaPosSelPosPad, /* Positive input from pad. */ \ 776 opaOutModeMain, /* Main output enabled. */ \ 777 opaResSelR2eqR1, /* R2 = R1 */ \ 778 opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ 779 DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ 780 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 781 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 782 false, /* No low pass filter on positive pad. */ \ 783 false, /* No low pass filter on negative pad. */ \ 784 false, /* No nextout output enabled. */ \ 785 false, /* Negative pad disabled. */ \ 786 true, /* Positive pad enabled, used as signal ground. */ \ 787 false, /* No shorting of inputs. */ \ 788 false, /* Rail-to-rail input enabled. */ \ 789 true, /* Use factory calibrated opamp offset. */ \ 790 0 /* Opamp offset value (not used). */ \ 791 } 792 793 /** Configuration of OPA0 in two-opamp differential driver mode. */ 794 #define OPA_INIT_DIFF_DRIVER_OPA0 \ 795 { \ 796 opaNegSelUnityGain, /* Unity gain. */ \ 797 opaPosSelPosPad, /* Positive input from pad. */ \ 798 opaOutModeAll, /* Both main and alternate outputs. */ \ 799 opaResSelDefault, /* Resistor ladder is not used. */ \ 800 opaResInMuxDisable, /* Resistor ladder disabled. */ \ 801 0, /* No alternate outputs enabled. */ \ 802 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 803 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 804 false, /* No low pass filter on positive pad. */ \ 805 false, /* No low pass filter on negative pad. */ \ 806 true, /* Pass output to next stage (OPA1). */ \ 807 false, /* Negative pad disabled. */ \ 808 true, /* Positive pad enabled, used as signal input. */ \ 809 false, /* No shorting of inputs. */ \ 810 false, /* Rail-to-rail input enabled. */ \ 811 true, /* Use factory calibrated opamp offset. */ \ 812 0 /* Opamp offset value (not used). */ \ 813 } 814 815 /** Configuration of OPA1 in two-opamp differential driver mode. */ 816 #define OPA_INIT_DIFF_DRIVER_OPA1 \ 817 { \ 818 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 819 opaPosSelPosPad, /* Positive input from pad. */ \ 820 opaOutModeMain, /* Main output enabled. */ \ 821 opaResSelR2eqR1, /* R2 = R1 */ \ 822 opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ 823 0, /* No alternate outputs enabled. */ \ 824 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 825 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 826 false, /* No low pass filter on positive pad. */ \ 827 false, /* No low pass filter on negative pad. */ \ 828 false, /* No nextout output enabled. */ \ 829 false, /* Negative pad disabled. */ \ 830 true, /* Positive pad enabled, used as signal ground. */ \ 831 false, /* No shorting of inputs. */ \ 832 false, /* Rail-to-rail input enabled. */ \ 833 true, /* Use factory calibrated opamp offset. */ \ 834 0 /* Opamp offset value (not used). */ \ 835 } 836 837 /** Configuration of OPA0 in three-opamp differential receiver mode. */ 838 #define OPA_INIT_DIFF_RECEIVER_OPA0 \ 839 { \ 840 opaNegSelUnityGain, /* Unity gain. */ \ 841 opaPosSelPosPad, /* Positive input from pad. */ \ 842 opaOutModeAll, /* Both main and alternate outputs. */ \ 843 opaResSelR2eqR1, /* R2 = R1 */ \ 844 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 845 0, /* No alternate outputs enabled. */ \ 846 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 847 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 848 false, /* No low pass filter on positive pad. */ \ 849 false, /* No low pass filter on negative pad. */ \ 850 true, /* Pass output to next stage (OPA2). */ \ 851 true, /* Negative pad enabled, used as signal ground. */ \ 852 true, /* Positive pad enabled, used as signal input. */ \ 853 false, /* No shorting of inputs. */ \ 854 false, /* Rail-to-rail input enabled. */ \ 855 true, /* Use factory calibrated opamp offset. */ \ 856 0 /* Opamp offset value (not used). */ \ 857 } 858 859 /** Configuration of OPA1 in three-opamp differential receiver mode. */ 860 #define OPA_INIT_DIFF_RECEIVER_OPA1 \ 861 { \ 862 opaNegSelUnityGain, /* Unity gain. */ \ 863 opaPosSelPosPad, /* Positive input from pad. */ \ 864 opaOutModeAll, /* Both main and alternate outputs. */ \ 865 opaResSelDefault, /* Resistor ladder is not used. */ \ 866 opaResInMuxDisable, /* Disable resistor ladder. */ \ 867 0, /* No alternate outputs enabled. */ \ 868 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 869 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 870 false, /* No low pass filter on positive pad. */ \ 871 false, /* No low pass filter on negative pad. */ \ 872 true, /* Pass output to next stage (OPA2). */ \ 873 false, /* Negative pad disabled. */ \ 874 true, /* Positive pad enabled, used as signal input. */ \ 875 false, /* No shorting of inputs. */ \ 876 false, /* Rail-to-rail input enabled. */ \ 877 true, /* Use factory calibrated opamp offset. */ \ 878 0 /* Opamp offset value (not used). */ \ 879 } 880 881 /** Configuration of OPA2 in three-opamp differential receiver mode. */ 882 #define OPA_INIT_DIFF_RECEIVER_OPA2 \ 883 { \ 884 opaNegSelResTap, /* Input from resistor ladder tap. */ \ 885 opaPosSelResTapOpa0, /* Input from OPA0 resistor ladder tap. */ \ 886 opaOutModeMain, /* Main output enabled. */ \ 887 opaResSelR2eqR1, /* R2 = R1 */ \ 888 opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ 889 DAC_OPA0MUX_OUTPEN_OUT0, /* Enable alternate output 0. */ \ 890 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ 891 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ 892 false, /* No low pass filter on positive pad. */ \ 893 false, /* No low pass filter on negative pad. */ \ 894 false, /* No nextout output enabled. */ \ 895 false, /* Negative pad disabled. */ \ 896 false, /* Positive pad disabled. */ \ 897 false, /* No shorting of inputs. */ \ 898 false, /* Rail-to-rail input enabled. */ \ 899 true, /* Use factory calibrated opamp offset. */ \ 900 0 /* Opamp offset value (not used). */ \ 901 } 902 903 #elif defined(_SILICON_LABS_32B_SERIES_1) 904 /** Configuration of OPA in unity gain voltage follower mode. */ 905 #define OPA_INIT_UNITY_GAIN \ 906 { \ 907 opaNegSelUnityGain, /* Unity gain. */ \ 908 opaPosSelPosPad, /* Positive input from pad. */ \ 909 opaOutModeMain, /* Main output enabled. */ \ 910 opaResSelDefault, /* Resistor ladder is not used. */ \ 911 opaResInMuxDisable, /* Resistor ladder disabled. */ \ 912 0, /* No alternate outputs enabled. */ \ 913 opaDrvStrDefault, /* Default opamp operation mode. */ \ 914 false, /* Disable 3x gain setting. */ \ 915 false, /* Use full output drive strength. */ \ 916 false, /* Disable unity-gain bandwidth scaling. */ \ 917 false, /* Opamp triggered by OPAxEN. */ \ 918 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 919 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 920 opaPrsOutDefault, /* Default PRS output setting. */ \ 921 false, /* Bus mastering enabled on APORTX. */ \ 922 false, /* Bus mastering enabled on APORTY. */ \ 923 3, /* 3 us settle time with default DrvStr. */ \ 924 0, /* No startup delay. */ \ 925 false, /* Rail-to-rail input enabled. */ \ 926 true, /* Use calibrated inverting offset. */ \ 927 0, /* Opamp offset value (not used). */ \ 928 true, /* Use calibrated non-inverting offset. */ \ 929 0 /* Opamp offset value (not used). */ \ 930 } 931 932 /** Configuration of OPA in non-inverting amplifier mode. */ 933 #define OPA_INIT_NON_INVERTING \ 934 { \ 935 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 936 opaPosSelPosPad, /* Positive input from pad. */ \ 937 opaOutModeMain, /* Main output enabled. */ \ 938 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ 939 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 940 0, /* No alternate outputs enabled. */ \ 941 opaDrvStrDefault, /* Default opamp operation mode. */ \ 942 false, /* Disable 3x gain setting. */ \ 943 false, /* Use full output drive strength. */ \ 944 false, /* Disable unity-gain bandwidth scaling. */ \ 945 false, /* Opamp triggered by OPAxEN. */ \ 946 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 947 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 948 opaPrsOutDefault, /* Default PRS output setting. */ \ 949 false, /* Bus mastering enabled on APORTX. */ \ 950 false, /* Bus mastering enabled on APORTY. */ \ 951 3, /* 3 us settle time with default DrvStr. */ \ 952 0, /* No startup delay. */ \ 953 false, /* Rail-to-rail input enabled. */ \ 954 true, /* Use calibrated inverting offset. */ \ 955 0, /* Opamp offset value (not used). */ \ 956 true, /* Use calibrated non-inverting offset. */ \ 957 0 /* Opamp offset value (not used). */ \ 958 } 959 960 /** Configuration of OPA in inverting amplifier mode. */ 961 #define OPA_INIT_INVERTING \ 962 { \ 963 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 964 opaPosSelPosPad, /* Positive input from pad. */ \ 965 opaOutModeMain, /* Main output enabled. */ \ 966 opaResSelR2eqR1, /* R2 = R1 */ \ 967 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 968 0, /* No alternate outputs enabled. */ \ 969 opaDrvStrDefault, /* Default opamp operation mode. */ \ 970 false, /* Disable 3x gain setting. */ \ 971 false, /* Use full output drive strength. */ \ 972 false, /* Disable unity-gain bandwidth scaling. */ \ 973 false, /* Opamp triggered by OPAxEN. */ \ 974 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 975 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 976 opaPrsOutDefault, /* Default PRS output setting. */ \ 977 false, /* Bus mastering enabled on APORTX. */ \ 978 false, /* Bus mastering enabled on APORTY. */ \ 979 3, /* 3 us settle time with default DrvStr. */ \ 980 0, /* No startup delay. */ \ 981 false, /* Rail-to-rail input enabled. */ \ 982 true, /* Use calibrated inverting offset. */ \ 983 0, /* Opamp offset value (not used). */ \ 984 true, /* Use calibrated non-inverting offset. */ \ 985 0 /* Opamp offset value (not used). */ \ 986 } 987 988 /** Configuration of OPA0 in cascaded non-inverting amplifier mode. */ 989 #define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \ 990 { \ 991 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 992 opaPosSelPosPad, /* Positive input from pad. */ \ 993 opaOutModeMain, /* Main output enabled. */ \ 994 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ 995 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 996 0, /* No alternate outputs enabled. */ \ 997 opaDrvStrDefault, /* Default opamp operation mode. */ \ 998 false, /* Disable 3x gain setting. */ \ 999 false, /* Use full output drive strength. */ \ 1000 false, /* Disable unity-gain bandwidth scaling. */ \ 1001 false, /* Opamp triggered by OPAxEN. */ \ 1002 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1003 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1004 opaPrsOutDefault, /* Default PRS output setting. */ \ 1005 false, /* Bus mastering enabled on APORTX. */ \ 1006 false, /* Bus mastering enabled on APORTY. */ \ 1007 3, /* 3 us settle time with default DrvStr. */ \ 1008 0, /* No startup delay. */ \ 1009 false, /* Rail-to-rail input enabled. */ \ 1010 true, /* Use calibrated inverting offset. */ \ 1011 0, /* Opamp offset value (not used). */ \ 1012 true, /* Use calibrated non-inverting offset. */ \ 1013 0 /* Opamp offset value (not used). */ \ 1014 } 1015 1016 /** Configuration of OPA1 in cascaded non-inverting amplifier mode. */ 1017 #define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \ 1018 { \ 1019 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 1020 opaPosSelOpaIn, /* Positive input from OPA0 output. */ \ 1021 opaOutModeMain, /* Main output enabled. */ \ 1022 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ 1023 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 1024 0, /* No alternate outputs enabled. */ \ 1025 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1026 false, /* Disable 3x gain setting. */ \ 1027 false, /* Use full output drive strength. */ \ 1028 false, /* Disable unity-gain bandwidth scaling. */ \ 1029 false, /* Opamp triggered by OPAxEN. */ \ 1030 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1031 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1032 opaPrsOutDefault, /* Default PRS output setting. */ \ 1033 false, /* Bus mastering enabled on APORTX. */ \ 1034 false, /* Bus mastering enabled on APORTY. */ \ 1035 3, /* 3 us settle time with default DrvStr. */ \ 1036 0, /* No startup delay. */ \ 1037 false, /* Rail-to-rail input enabled. */ \ 1038 true, /* Use calibrated inverting offset. */ \ 1039 0, /* Opamp offset value (not used). */ \ 1040 true, /* Use calibrated non-inverting offset. */ \ 1041 0 /* Opamp offset value (not used). */ \ 1042 } 1043 1044 /** Configuration of OPA2 in cascaded non-inverting amplifier mode. */ 1045 #define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \ 1046 { \ 1047 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 1048 opaPosSelOpaIn, /* Positive input from OPA1 output. */ \ 1049 opaOutModeMain, /* Main output enabled. */ \ 1050 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ 1051 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 1052 0, /* No alternate outputs enabled. */ \ 1053 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1054 false, /* Disable 3x gain setting. */ \ 1055 false, /* Use full output drive strength. */ \ 1056 false, /* Disable unity-gain bandwidth scaling. */ \ 1057 false, /* Opamp triggered by OPAxEN. */ \ 1058 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1059 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1060 opaPrsOutDefault, /* Default PRS output setting. */ \ 1061 false, /* Bus mastering enabled on APORTX. */ \ 1062 false, /* Bus mastering enabled on APORTY. */ \ 1063 3, /* 3 us settle time with default DrvStr. */ \ 1064 0, /* No startup delay. */ \ 1065 false, /* Rail-to-rail input enabled. */ \ 1066 true, /* Use calibrated inverting offset. */ \ 1067 0, /* Opamp offset value (not used). */ \ 1068 true, /* Use calibrated non-inverting offset. */ \ 1069 0 /* Opamp offset value (not used). */ \ 1070 } 1071 1072 /** Configuration of OPA3 in cascaded non-inverting amplifier mode. */ 1073 #define OPA_INIT_CASCADED_NON_INVERTING_OPA3 \ 1074 { \ 1075 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 1076 opaPosSelOpaIn, /* Positive input from OPA2NEXT output. */ \ 1077 opaOutModeMain, /* Main output enabled. */ \ 1078 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ 1079 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 1080 0, /* No alternate outputs enabled. */ \ 1081 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1082 false, /* Disable 3x gain setting. */ \ 1083 false, /* Use full output drive strength. */ \ 1084 false, /* Disable unity-gain bandwidth scaling. */ \ 1085 false, /* Opamp triggered by OPAxEN. */ \ 1086 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1087 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1088 opaPrsOutDefault, /* Default PRS output setting. */ \ 1089 false, /* Bus mastering enabled on APORTX. */ \ 1090 false, /* Bus mastering enabled on APORTY. */ \ 1091 3, /* 3 us settle time with default DrvStr. */ \ 1092 0, /* No startup delay. */ \ 1093 false, /* Rail-to-rail input enabled. */ \ 1094 true, /* Use calibrated inverting offset. */ \ 1095 0, /* Opamp offset value (not used). */ \ 1096 true, /* Use calibrated non-inverting offset. */ \ 1097 0 /* Opamp offset value (not used). */ \ 1098 } 1099 1100 /** Configuration of OPA0 in cascaded inverting amplifier mode. */ 1101 #define OPA_INIT_CASCADED_INVERTING_OPA0 \ 1102 { \ 1103 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 1104 opaPosSelPosPad, /* Positive input from pad. */ \ 1105 opaOutModeMain, /* Main output enabled. */ \ 1106 opaResSelR2eqR1, /* R2 = R1 */ \ 1107 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 1108 0, /* No alternate outputs enabled. */ \ 1109 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1110 false, /* Disable 3x gain setting. */ \ 1111 false, /* Use full output drive strength. */ \ 1112 false, /* Disable unity-gain bandwidth scaling. */ \ 1113 false, /* Opamp triggered by OPAxEN. */ \ 1114 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1115 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1116 opaPrsOutDefault, /* Default PRS output setting. */ \ 1117 false, /* Bus mastering enabled on APORTX. */ \ 1118 false, /* Bus mastering enabled on APORTY. */ \ 1119 3, /* 3 us settle time with default DrvStr. */ \ 1120 0, /* No startup delay. */ \ 1121 false, /* Rail-to-rail input enabled. */ \ 1122 true, /* Use calibrated inverting offset. */ \ 1123 0, /* Opamp offset value (not used). */ \ 1124 true, /* Use calibrated non-inverting offset. */ \ 1125 0 /* Opamp offset value (not used). */ \ 1126 } 1127 1128 /** Configuration of OPA1 in cascaded inverting amplifier mode. */ 1129 #define OPA_INIT_CASCADED_INVERTING_OPA1 \ 1130 { \ 1131 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 1132 opaPosSelPosPad, /* Positive input from pad. */ \ 1133 opaOutModeMain, /* Main output enabled. */ \ 1134 opaResSelR2eqR1, /* R2 = R1 */ \ 1135 opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ 1136 0, /* No alternate outputs enabled. */ \ 1137 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1138 false, /* Disable 3x gain setting. */ \ 1139 false, /* Use full output drive strength. */ \ 1140 false, /* Disable unity-gain bandwidth scaling. */ \ 1141 false, /* Opamp triggered by OPAxEN. */ \ 1142 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1143 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1144 opaPrsOutDefault, /* Default PRS output setting. */ \ 1145 false, /* Bus mastering enabled on APORTX. */ \ 1146 false, /* Bus mastering enabled on APORTY. */ \ 1147 3, /* 3 us settle time with default DrvStr. */ \ 1148 0, /* No startup delay. */ \ 1149 false, /* Rail-to-rail input enabled. */ \ 1150 true, /* Use calibrated inverting offset. */ \ 1151 0, /* Opamp offset value (not used). */ \ 1152 true, /* Use calibrated non-inverting offset. */ \ 1153 0 /* Opamp offset value (not used). */ \ 1154 } 1155 1156 /** Configuration of OPA2 in cascaded inverting amplifier mode. */ 1157 #define OPA_INIT_CASCADED_INVERTING_OPA2 \ 1158 { \ 1159 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 1160 opaPosSelPosPad, /* Positive input from pad. */ \ 1161 opaOutModeMain, /* Main output enabled. */ \ 1162 opaResSelR2eqR1, /* R2 = R1 */ \ 1163 opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ 1164 0, /* No alternate outputs enabled. */ \ 1165 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1166 false, /* Disable 3x gain setting. */ \ 1167 false, /* Use full output drive strength. */ \ 1168 false, /* Disable unity-gain bandwidth scaling. */ \ 1169 false, /* Opamp triggered by OPAxEN. */ \ 1170 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1171 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1172 opaPrsOutDefault, /* Default PRS output setting. */ \ 1173 false, /* Bus mastering enabled on APORTX. */ \ 1174 false, /* Bus mastering enabled on APORTY. */ \ 1175 3, /* 3 us settle time with default DrvStr. */ \ 1176 0, /* No startup delay. */ \ 1177 false, /* Rail-to-rail input enabled. */ \ 1178 true, /* Use calibrated inverting offset. */ \ 1179 0, /* Opamp offset value (not used). */ \ 1180 true, /* Use calibrated non-inverting offset. */ \ 1181 0 /* Opamp offset value (not used). */ \ 1182 } 1183 1184 /** Configuration of OPA3 in cascaded inverting amplifier mode. */ 1185 #define OPA_INIT_CASCADED_INVERTING_OPA3 \ 1186 { \ 1187 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 1188 opaPosSelPosPad, /* Positive input from pad. */ \ 1189 opaOutModeMain, /* Main output enabled. */ \ 1190 opaResSelR2eqR1, /* R2 = R1 */ \ 1191 opaResInMuxOpaIn, /* Resistor ladder input from OPA2. */ \ 1192 0, /* No alternate outputs enabled. */ \ 1193 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1194 false, /* Disable 3x gain setting. */ \ 1195 false, /* Use full output drive strength. */ \ 1196 false, /* Disable unity-gain bandwidth scaling. */ \ 1197 false, /* Opamp triggered by OPAxEN. */ \ 1198 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1199 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1200 opaPrsOutDefault, /* Default PRS output setting. */ \ 1201 false, /* Bus mastering enabled on APORTX. */ \ 1202 false, /* Bus mastering enabled on APORTY. */ \ 1203 3, /* 3 us settle time with default DrvStr. */ \ 1204 0, /* No startup delay. */ \ 1205 false, /* Rail-to-rail input enabled. */ \ 1206 true, /* Use calibrated inverting offset. */ \ 1207 0, /* Opamp offset value (not used). */ \ 1208 true, /* Use calibrated non-inverting offset. */ \ 1209 0 /* Opamp offset value (not used). */ \ 1210 } 1211 1212 /** Configuration of OPA0 in two-opamp differential driver mode. */ 1213 #define OPA_INIT_DIFF_DRIVER_OPA0 \ 1214 { \ 1215 opaNegSelUnityGain, /* Unity gain. */ \ 1216 opaPosSelPosPad, /* Positive input from pad. */ \ 1217 opaOutModeMain, /* Main output enabled. */ \ 1218 opaResSelDefault, /* Resistor ladder is not used. */ \ 1219 opaResInMuxDisable, /* Resistor ladder disabled. */ \ 1220 0, /* No alternate outputs enabled. */ \ 1221 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1222 false, /* Disable 3x gain setting. */ \ 1223 false, /* Use full output drive strength. */ \ 1224 false, /* Disable unity-gain bandwidth scaling. */ \ 1225 false, /* Opamp triggered by OPAxEN. */ \ 1226 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1227 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1228 opaPrsOutDefault, /* Default PRS output setting. */ \ 1229 false, /* Bus mastering enabled on APORTX. */ \ 1230 false, /* Bus mastering enabled on APORTY. */ \ 1231 3, /* 3 us settle time with default DrvStr. */ \ 1232 0, /* No startup delay. */ \ 1233 false, /* Rail-to-rail input enabled. */ \ 1234 true, /* Use calibrated inverting offset. */ \ 1235 0, /* Opamp offset value (not used). */ \ 1236 true, /* Use calibrated non-inverting offset. */ \ 1237 0 /* Opamp offset value (not used). */ \ 1238 } 1239 1240 /** Configuration of OPA1 in two-opamp differential driver mode. */ 1241 #define OPA_INIT_DIFF_DRIVER_OPA1 \ 1242 { \ 1243 opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ 1244 opaPosSelPosPad, /* Positive input from pad. */ \ 1245 opaOutModeMain, /* Main output enabled. */ \ 1246 opaResSelR2eqR1, /* R2 = R1 */ \ 1247 opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ 1248 0, /* No alternate outputs enabled. */ \ 1249 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1250 false, /* Disable 3x gain setting. */ \ 1251 false, /* Use full output drive strength. */ \ 1252 false, /* Disable unity-gain bandwidth scaling. */ \ 1253 false, /* Opamp triggered by OPAxEN. */ \ 1254 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1255 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1256 opaPrsOutDefault, /* Default PRS output setting. */ \ 1257 false, /* Bus mastering enabled on APORTX. */ \ 1258 false, /* Bus mastering enabled on APORTY. */ \ 1259 3, /* 3 us settle time with default DrvStr. */ \ 1260 0, /* No startup delay. */ \ 1261 false, /* Rail-to-rail input enabled. */ \ 1262 true, /* Use calibrated inverting offset. */ \ 1263 0, /* Opamp offset value (not used). */ \ 1264 true, /* Use calibrated non-inverting offset. */ \ 1265 0 /* Opamp offset value (not used). */ \ 1266 } 1267 1268 /** Configuration of OPA0 in three-opamp differential receiver mode. */ 1269 #define OPA_INIT_DIFF_RECEIVER_OPA0 \ 1270 { \ 1271 opaNegSelUnityGain, /* Unity gain. */ \ 1272 opaPosSelPosPad, /* Positive input from pad. */ \ 1273 opaOutModeMain, /* Main output enabled. */ \ 1274 opaResSelR2eqR1, /* R2 = R1 */ \ 1275 opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ 1276 0, /* No alternate outputs enabled. */ \ 1277 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1278 false, /* Disable 3x gain setting. */ \ 1279 false, /* Use full output drive strength. */ \ 1280 false, /* Disable unity-gain bandwidth scaling. */ \ 1281 false, /* Opamp triggered by OPAxEN. */ \ 1282 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1283 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1284 opaPrsOutDefault, /* Default PRS output setting. */ \ 1285 false, /* Bus mastering enabled on APORTX. */ \ 1286 false, /* Bus mastering enabled on APORTY. */ \ 1287 3, /* 3 us settle time with default DrvStr. */ \ 1288 0, /* No startup delay. */ \ 1289 false, /* Rail-to-rail input enabled. */ \ 1290 true, /* Use calibrated inverting offset. */ \ 1291 0, /* Opamp offset value (not used). */ \ 1292 true, /* Use calibrated non-inverting offset. */ \ 1293 0 /* Opamp offset value (not used). */ \ 1294 } 1295 1296 /** Configuration of OPA1 in three-opamp differential receiver mode. */ 1297 #define OPA_INIT_DIFF_RECEIVER_OPA1 \ 1298 { \ 1299 opaNegSelUnityGain, /* Unity gain. */ \ 1300 opaPosSelPosPad, /* Positive input from pad. */ \ 1301 opaOutModeMain, /* Main output enabled. */ \ 1302 opaResSelDefault, /* Resistor ladder is not used. */ \ 1303 opaResInMuxDisable, /* Disable resistor ladder. */ \ 1304 0, /* No alternate outputs enabled. */ \ 1305 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1306 false, /* Disable 3x gain setting. */ \ 1307 false, /* Use full output drive strength. */ \ 1308 false, /* Disable unity-gain bandwidth scaling. */ \ 1309 false, /* Opamp triggered by OPAxEN. */ \ 1310 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1311 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1312 opaPrsOutDefault, /* Default PRS output setting. */ \ 1313 false, /* Bus mastering enabled on APORTX. */ \ 1314 false, /* Bus mastering enabled on APORTY. */ \ 1315 3, /* 3 us settle time with default DrvStr. */ \ 1316 0, /* No startup delay. */ \ 1317 false, /* Rail-to-rail input enabled. */ \ 1318 true, /* Use calibrated inverting offset. */ \ 1319 0, /* Opamp offset value (not used). */ \ 1320 true, /* Use calibrated non-inverting offset. */ \ 1321 0 /* Opamp offset value (not used). */ \ 1322 } 1323 1324 /** Configuration of OPA2 in three-opamp differential receiver mode. */ 1325 #define OPA_INIT_DIFF_RECEIVER_OPA2 \ 1326 { \ 1327 opaNegSelResTap, /* Input from resistor ladder tap. */ \ 1328 opaPosSelResTap, /* Input from OPA0 resistor ladder tap. */ \ 1329 opaOutModeMain, /* Main output enabled. */ \ 1330 opaResSelR2eqR1, /* R2 = R1 */ \ 1331 opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ 1332 0, /* No alternate outputs enabled. */ \ 1333 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1334 false, /* Disable 3x gain setting. */ \ 1335 false, /* Use full output drive strength. */ \ 1336 false, /* Disable unity-gain bandwidth scaling. */ \ 1337 false, /* Opamp triggered by OPAxEN. */ \ 1338 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1339 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1340 opaPrsOutDefault, /* Default PRS output setting. */ \ 1341 false, /* Bus mastering enabled on APORTX. */ \ 1342 false, /* Bus mastering enabled on APORTY. */ \ 1343 3, /* 3 us settle time with default DrvStr. */ \ 1344 0, /* No startup delay. */ \ 1345 false, /* Rail-to-rail input enabled. */ \ 1346 true, /* Use calibrated inverting offset. */ \ 1347 0, /* Opamp offset value (not used). */ \ 1348 true, /* Use calibrated non-inverting offset. */ \ 1349 0 /* Opamp offset value (not used). */ \ 1350 } 1351 1352 /** Configuration of OPA3 in three+one opamp differential receiver mode. In this 1353 configuration, OPA3 is a second single-ended output amplifier. */ 1354 #define OPA_INIT_DIFF_RECEIVER_OPA3 \ 1355 { \ 1356 opaNegSelResTap, /* Input from resistor ladder tap. */ \ 1357 opaPosSelResTap, /* Input from OPA2 resistor ladder tap. */ \ 1358 opaOutModeMain, /* Main output enabled. */ \ 1359 opaResSelR2eqR1, /* R2 = R1 */ \ 1360 opaResInMuxOpaIn, /* Resistor ladder input from OPA2. */ \ 1361 0, /* No alternate outputs enabled. */ \ 1362 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1363 false, /* Disable 3x gain setting. */ \ 1364 false, /* Use full output drive strength. */ \ 1365 false, /* Disable unity-gain bandwidth scaling. */ \ 1366 false, /* Opamp triggered by OPAxEN. */ \ 1367 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1368 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1369 opaPrsOutDefault, /* Default PRS output setting. */ \ 1370 false, /* Bus mastering enabled on APORTX. */ \ 1371 false, /* Bus mastering enabled on APORTY. */ \ 1372 3, /* 3 us settle time with default DrvStr. */ \ 1373 0, /* No startup delay. */ \ 1374 false, /* Rail-to-rail input enabled. */ \ 1375 true, /* Use calibrated inverting offset. */ \ 1376 0, /* Opamp offset value (not used). */ \ 1377 true, /* Use calibrated non-inverting offset. */ \ 1378 0 /* Opamp offset value (not used). */ \ 1379 } 1380 1381 /** Configuration of OPA0 in two-opamp instrumentation amplifier mode. */ 1382 #define OPA_INIT_INSTR_AMP_OPA0 \ 1383 { \ 1384 opaNegSelResTap, /* Input from resistor ladder tap. */ \ 1385 opaPosSelPosPad, /* Positive input from pad. */ \ 1386 opaOutModeMain, /* Main output enabled. */ \ 1387 opaResSelR2eqR1, /* R2 = R1 */ \ 1388 opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ 1389 0, /* No alternate outputs enabled. */ \ 1390 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1391 false, /* Disable 3x gain setting. */ \ 1392 false, /* Use full output drive strength. */ \ 1393 false, /* Disable unity-gain bandwidth scaling. */ \ 1394 false, /* Opamp triggered by OPAxEN. */ \ 1395 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1396 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1397 opaPrsOutDefault, /* Default PRS output setting. */ \ 1398 false, /* Bus mastering enabled on APORTX. */ \ 1399 false, /* Bus mastering enabled on APORTY. */ \ 1400 3, /* 3 us settle time with default DrvStr. */ \ 1401 0, /* No startup delay. */ \ 1402 false, /* Rail-to-rail input enabled. */ \ 1403 true, /* Use calibrated inverting offset. */ \ 1404 0, /* Opamp offset value (not used). */ \ 1405 true, /* Use calibrated non-inverting offset. */ \ 1406 0 /* Opamp offset value (not used). */ \ 1407 } 1408 1409 /** Configuration of OPA1 in two-opamp instrumentation amplifier mode. */ 1410 #define OPA_INIT_INSTR_AMP_OPA1 \ 1411 { \ 1412 opaNegSelNegPad, /* Negative input from pad. */ \ 1413 opaPosSelResTap, /* Input from resistor ladder tap. */ \ 1414 opaOutModeMain, /* Main output enabled. */ \ 1415 opaResSelR2eqR1, /* R2 = R1 */ \ 1416 opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ 1417 0, /* No alternate outputs enabled. */ \ 1418 opaDrvStrDefault, /* Default opamp operation mode. */ \ 1419 false, /* Disable 3x gain setting. */ \ 1420 false, /* Use full output drive strength. */ \ 1421 false, /* Disable unity-gain bandwidth scaling. */ \ 1422 false, /* Opamp triggered by OPAxEN. */ \ 1423 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ 1424 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ 1425 opaPrsOutDefault, /* Default PRS output setting. */ \ 1426 false, /* Bus mastering enabled on APORTX. */ \ 1427 false, /* Bus mastering enabled on APORTY. */ \ 1428 3, /* 3 us settle time with default DrvStr. */ \ 1429 0, /* No startup delay. */ \ 1430 false, /* Rail-to-rail input enabled. */ \ 1431 true, /* Use calibrated inverting offset. */ \ 1432 0, /* Opamp offset value (not used). */ \ 1433 true, /* Use calibrated non-inverting offset. */ \ 1434 0 /* Opamp offset value (not used). */ \ 1435 } 1436 1437 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ 1438 1439 /******************************************************************************* 1440 ***************************** PROTOTYPES ********************************** 1441 ******************************************************************************/ 1442 1443 #if defined(_SILICON_LABS_32B_SERIES_0) 1444 void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa); 1445 void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); 1446 #elif defined(_SILICON_LABS_32B_SERIES_1) 1447 void OPAMP_Disable(VDAC_TypeDef *dac, OPAMP_TypeDef opa); 1448 void OPAMP_Enable(VDAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); 1449 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */ 1450 1451 /** @} (end addtogroup opamp) */ 1452 1453 #ifdef __cplusplus 1454 } 1455 #endif 1456 1457 #endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) 1458 || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ 1459 #endif /* EM_OPAMP_H */ 1460
