1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG24 MPAHBRAM register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG24_MPAHBRAM_H 31 #define EFR32MG24_MPAHBRAM_H 32 #define MPAHBRAM_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG24_MPAHBRAM MPAHBRAM 40 * @{ 41 * @brief EFR32MG24 MPAHBRAM Register Declaration. 42 *****************************************************************************/ 43 44 /** MPAHBRAM Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP version ID */ 47 __IOM uint32_t CMD; /**< Command register */ 48 __IOM uint32_t CTRL; /**< Control register */ 49 __IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */ 50 __IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */ 51 __IM uint32_t ECCERRADDR2; /**< ECC Error Address 2 */ 52 __IM uint32_t ECCERRADDR3; /**< ECC Error Address 3 */ 53 __IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */ 54 __IOM uint32_t IF; /**< Interrupt Flags */ 55 __IOM uint32_t IEN; /**< Interrupt Enable */ 56 uint32_t RESERVED0[7U]; /**< Reserved for future use */ 57 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 58 uint32_t RESERVED2[1006U]; /**< Reserved for future use */ 59 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 60 __IOM uint32_t CMD_SET; /**< Command register */ 61 __IOM uint32_t CTRL_SET; /**< Control register */ 62 __IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */ 63 __IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */ 64 __IM uint32_t ECCERRADDR2_SET; /**< ECC Error Address 2 */ 65 __IM uint32_t ECCERRADDR3_SET; /**< ECC Error Address 3 */ 66 __IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */ 67 __IOM uint32_t IF_SET; /**< Interrupt Flags */ 68 __IOM uint32_t IEN_SET; /**< Interrupt Enable */ 69 uint32_t RESERVED3[7U]; /**< Reserved for future use */ 70 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 71 uint32_t RESERVED5[1006U]; /**< Reserved for future use */ 72 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 73 __IOM uint32_t CMD_CLR; /**< Command register */ 74 __IOM uint32_t CTRL_CLR; /**< Control register */ 75 __IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */ 76 __IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */ 77 __IM uint32_t ECCERRADDR2_CLR; /**< ECC Error Address 2 */ 78 __IM uint32_t ECCERRADDR3_CLR; /**< ECC Error Address 3 */ 79 __IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */ 80 __IOM uint32_t IF_CLR; /**< Interrupt Flags */ 81 __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ 82 uint32_t RESERVED6[7U]; /**< Reserved for future use */ 83 uint32_t RESERVED7[1U]; /**< Reserved for future use */ 84 uint32_t RESERVED8[1006U]; /**< Reserved for future use */ 85 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 86 __IOM uint32_t CMD_TGL; /**< Command register */ 87 __IOM uint32_t CTRL_TGL; /**< Control register */ 88 __IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */ 89 __IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */ 90 __IM uint32_t ECCERRADDR2_TGL; /**< ECC Error Address 2 */ 91 __IM uint32_t ECCERRADDR3_TGL; /**< ECC Error Address 3 */ 92 __IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */ 93 __IOM uint32_t IF_TGL; /**< Interrupt Flags */ 94 __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ 95 uint32_t RESERVED9[7U]; /**< Reserved for future use */ 96 uint32_t RESERVED10[1U]; /**< Reserved for future use */ 97 } MPAHBRAM_TypeDef; 98 /** @} End of group EFR32MG24_MPAHBRAM */ 99 100 /**************************************************************************//** 101 * @addtogroup EFR32MG24_MPAHBRAM 102 * @{ 103 * @defgroup EFR32MG24_MPAHBRAM_BitFields MPAHBRAM Bit Fields 104 * @{ 105 *****************************************************************************/ 106 107 /* Bit fields for MPAHBRAM IPVERSION */ 108 #define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for MPAHBRAM_IPVERSION */ 109 #define _MPAHBRAM_IPVERSION_MASK 0x00000003UL /**< Mask for MPAHBRAM_IPVERSION */ 110 #define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */ 111 #define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x3UL /**< Bit mask for MPAHBRAM_IPVERSION */ 112 #define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */ 113 #define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */ 114 115 /* Bit fields for MPAHBRAM CMD */ 116 #define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */ 117 #define _MPAHBRAM_CMD_MASK 0x0000000FUL /**< Mask for MPAHBRAM_CMD */ 118 #define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */ 119 #define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */ 120 #define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */ 121 #define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ 122 #define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ 123 #define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */ 124 #define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */ 125 #define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */ 126 #define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ 127 #define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ 128 #define MPAHBRAM_CMD_CLEARECCADDR2 (0x1UL << 2) /**< Clear ECCERRADDR2 */ 129 #define _MPAHBRAM_CMD_CLEARECCADDR2_SHIFT 2 /**< Shift value for MPAHBRAM_CLEARECCADDR2 */ 130 #define _MPAHBRAM_CMD_CLEARECCADDR2_MASK 0x4UL /**< Bit mask for MPAHBRAM_CLEARECCADDR2 */ 131 #define _MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ 132 #define MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ 133 #define MPAHBRAM_CMD_CLEARECCADDR3 (0x1UL << 3) /**< Clear ECCERRADDR3 */ 134 #define _MPAHBRAM_CMD_CLEARECCADDR3_SHIFT 3 /**< Shift value for MPAHBRAM_CLEARECCADDR3 */ 135 #define _MPAHBRAM_CMD_CLEARECCADDR3_MASK 0x8UL /**< Bit mask for MPAHBRAM_CLEARECCADDR3 */ 136 #define _MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ 137 #define MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ 138 139 /* Bit fields for MPAHBRAM CTRL */ 140 #define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */ 141 #define _MPAHBRAM_CTRL_MASK 0x000000FFUL /**< Mask for MPAHBRAM_CTRL */ 142 #define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */ 143 #define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */ 144 #define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */ 145 #define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 146 #define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 147 #define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */ 148 #define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */ 149 #define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */ 150 #define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 151 #define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 152 #define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */ 153 #define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */ 154 #define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */ 155 #define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 156 #define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 157 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */ 158 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */ 159 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 160 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */ 161 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */ 162 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */ 163 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 0x00000003UL /**< Mode PORT2 for MPAHBRAM_CTRL */ 164 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 0x00000004UL /**< Mode PORT3 for MPAHBRAM_CTRL */ 165 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 166 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */ 167 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */ 168 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */ 169 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 << 3) /**< Shifted mode PORT2 for MPAHBRAM_CTRL */ 170 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 << 3) /**< Shifted mode PORT3 for MPAHBRAM_CTRL */ 171 #define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */ 172 #define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */ 173 #define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */ 174 #define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 175 #define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 176 #define MPAHBRAM_CTRL_WAITSTATES (0x1UL << 7) /**< RAM read wait states */ 177 #define _MPAHBRAM_CTRL_WAITSTATES_SHIFT 7 /**< Shift value for MPAHBRAM_WAITSTATES */ 178 #define _MPAHBRAM_CTRL_WAITSTATES_MASK 0x80UL /**< Bit mask for MPAHBRAM_WAITSTATES */ 179 #define _MPAHBRAM_CTRL_WAITSTATES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 180 #define MPAHBRAM_CTRL_WAITSTATES_DEFAULT (_MPAHBRAM_CTRL_WAITSTATES_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 181 182 /* Bit fields for MPAHBRAM ECCERRADDR0 */ 183 #define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */ 184 #define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */ 185 #define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ 186 #define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ 187 #define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */ 188 #define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/ 189 190 /* Bit fields for MPAHBRAM ECCERRADDR1 */ 191 #define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */ 192 #define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */ 193 #define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ 194 #define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ 195 #define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */ 196 #define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/ 197 198 /* Bit fields for MPAHBRAM ECCERRADDR2 */ 199 #define _MPAHBRAM_ECCERRADDR2_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR2 */ 200 #define _MPAHBRAM_ECCERRADDR2_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR2 */ 201 #define _MPAHBRAM_ECCERRADDR2_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ 202 #define _MPAHBRAM_ECCERRADDR2_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ 203 #define _MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR2 */ 204 #define MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR2*/ 205 206 /* Bit fields for MPAHBRAM ECCERRADDR3 */ 207 #define _MPAHBRAM_ECCERRADDR3_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR3 */ 208 #define _MPAHBRAM_ECCERRADDR3_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR3 */ 209 #define _MPAHBRAM_ECCERRADDR3_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ 210 #define _MPAHBRAM_ECCERRADDR3_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ 211 #define _MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR3 */ 212 #define MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR3*/ 213 214 /* Bit fields for MPAHBRAM ECCMERRIND */ 215 #define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */ 216 #define _MPAHBRAM_ECCMERRIND_MASK 0x0000000FUL /**< Mask for MPAHBRAM_ECCMERRIND */ 217 #define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */ 218 #define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */ 219 #define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */ 220 #define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ 221 #define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ 222 #define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */ 223 #define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */ 224 #define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */ 225 #define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ 226 #define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ 227 #define MPAHBRAM_ECCMERRIND_P2 (0x1UL << 2) /**< Multiple ECC errors on AHB port 2 */ 228 #define _MPAHBRAM_ECCMERRIND_P2_SHIFT 2 /**< Shift value for MPAHBRAM_P2 */ 229 #define _MPAHBRAM_ECCMERRIND_P2_MASK 0x4UL /**< Bit mask for MPAHBRAM_P2 */ 230 #define _MPAHBRAM_ECCMERRIND_P2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ 231 #define MPAHBRAM_ECCMERRIND_P2_DEFAULT (_MPAHBRAM_ECCMERRIND_P2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ 232 #define MPAHBRAM_ECCMERRIND_P3 (0x1UL << 3) /**< Multiple ECC errors on AHB port 2 */ 233 #define _MPAHBRAM_ECCMERRIND_P3_SHIFT 3 /**< Shift value for MPAHBRAM_P3 */ 234 #define _MPAHBRAM_ECCMERRIND_P3_MASK 0x8UL /**< Bit mask for MPAHBRAM_P3 */ 235 #define _MPAHBRAM_ECCMERRIND_P3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ 236 #define MPAHBRAM_ECCMERRIND_P3_DEFAULT (_MPAHBRAM_ECCMERRIND_P3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ 237 238 /* Bit fields for MPAHBRAM IF */ 239 #define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */ 240 #define _MPAHBRAM_IF_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IF */ 241 #define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */ 242 #define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ 243 #define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ 244 #define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 245 #define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 246 #define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */ 247 #define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ 248 #define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ 249 #define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 250 #define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 251 #define MPAHBRAM_IF_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Flag */ 252 #define _MPAHBRAM_IF_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */ 253 #define _MPAHBRAM_IF_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */ 254 #define _MPAHBRAM_IF_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 255 #define MPAHBRAM_IF_AHB2ERR1B_DEFAULT (_MPAHBRAM_IF_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 256 #define MPAHBRAM_IF_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Flag */ 257 #define _MPAHBRAM_IF_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */ 258 #define _MPAHBRAM_IF_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */ 259 #define _MPAHBRAM_IF_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 260 #define MPAHBRAM_IF_AHB3ERR1B_DEFAULT (_MPAHBRAM_IF_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 261 #define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */ 262 #define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ 263 #define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ 264 #define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 265 #define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 266 #define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */ 267 #define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ 268 #define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ 269 #define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 270 #define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 271 #define MPAHBRAM_IF_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Flag */ 272 #define _MPAHBRAM_IF_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */ 273 #define _MPAHBRAM_IF_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */ 274 #define _MPAHBRAM_IF_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 275 #define MPAHBRAM_IF_AHB2ERR2B_DEFAULT (_MPAHBRAM_IF_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 276 #define MPAHBRAM_IF_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Flag */ 277 #define _MPAHBRAM_IF_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */ 278 #define _MPAHBRAM_IF_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */ 279 #define _MPAHBRAM_IF_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 280 #define MPAHBRAM_IF_AHB3ERR2B_DEFAULT (_MPAHBRAM_IF_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 281 282 /* Bit fields for MPAHBRAM IEN */ 283 #define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */ 284 #define _MPAHBRAM_IEN_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IEN */ 285 #define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */ 286 #define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ 287 #define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ 288 #define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 289 #define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 290 #define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */ 291 #define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ 292 #define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ 293 #define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 294 #define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 295 #define MPAHBRAM_IEN_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Enable */ 296 #define _MPAHBRAM_IEN_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */ 297 #define _MPAHBRAM_IEN_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */ 298 #define _MPAHBRAM_IEN_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 299 #define MPAHBRAM_IEN_AHB2ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 300 #define MPAHBRAM_IEN_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Enable */ 301 #define _MPAHBRAM_IEN_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */ 302 #define _MPAHBRAM_IEN_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */ 303 #define _MPAHBRAM_IEN_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 304 #define MPAHBRAM_IEN_AHB3ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 305 #define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */ 306 #define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ 307 #define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ 308 #define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 309 #define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 310 #define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */ 311 #define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ 312 #define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ 313 #define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 314 #define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 315 #define MPAHBRAM_IEN_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Enable */ 316 #define _MPAHBRAM_IEN_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */ 317 #define _MPAHBRAM_IEN_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */ 318 #define _MPAHBRAM_IEN_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 319 #define MPAHBRAM_IEN_AHB2ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 320 #define MPAHBRAM_IEN_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Enable */ 321 #define _MPAHBRAM_IEN_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */ 322 #define _MPAHBRAM_IEN_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */ 323 #define _MPAHBRAM_IEN_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 324 #define MPAHBRAM_IEN_AHB3ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 325 326 /** @} End of group EFR32MG24_MPAHBRAM_BitFields */ 327 /** @} End of group EFR32MG24_MPAHBRAM */ 328 /** @} End of group Parts */ 329 330 #endif // EFR32MG24_MPAHBRAM_H 331
