1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG24 IADC register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG24_IADC_H 31 #define EFR32MG24_IADC_H 32 #define IADC_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG24_IADC IADC 40 * @{ 41 * @brief EFR32MG24 IADC Register Declaration. 42 *****************************************************************************/ 43 44 /** IADC CFG Register Group Declaration. */ 45 typedef struct { 46 __IOM uint32_t CFG; /**< Configuration */ 47 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 48 __IOM uint32_t SCALE; /**< Scaling */ 49 __IOM uint32_t SCHED; /**< Scheduling */ 50 } IADC_CFG_TypeDef; 51 52 /** IADC SCANTABLE Register Group Declaration. */ 53 typedef struct { 54 __IOM uint32_t SCAN; /**< SCAN Entry */ 55 } IADC_SCANTABLE_TypeDef; 56 57 /** IADC Register Declaration. */ 58 typedef struct { 59 __IM uint32_t IPVERSION; /**< IPVERSION */ 60 __IOM uint32_t EN; /**< Enable */ 61 __IOM uint32_t CTRL; /**< Control */ 62 __IOM uint32_t CMD; /**< Command */ 63 __IOM uint32_t TIMER; /**< Timer */ 64 __IM uint32_t STATUS; /**< Status */ 65 __IOM uint32_t MASKREQ; /**< Mask Request */ 66 __IM uint32_t STMASK; /**< Scan Table Mask */ 67 __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ 68 __IOM uint32_t IF; /**< Interrupt Flags */ 69 __IOM uint32_t IEN; /**< Interrupt Enable */ 70 __IOM uint32_t TRIGGER; /**< Trigger */ 71 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 72 uint32_t RESERVED1[5U]; /**< Reserved for future use */ 73 IADC_CFG_TypeDef CFG[2U]; /**< CFG */ 74 uint32_t RESERVED2[2U]; /**< Reserved for future use */ 75 __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ 76 __IM uint32_t SINGLEFIFODATA; /**< Single FIFO DATA */ 77 __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ 78 __IM uint32_t SINGLEDATA; /**< Single Data */ 79 __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ 80 __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ 81 __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ 82 __IM uint32_t SCANDATA; /**< Scan Data */ 83 uint32_t RESERVED3[1U]; /**< Reserved for future use */ 84 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 85 __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ 86 uint32_t RESERVED5[1U]; /**< Reserved for future use */ 87 IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ 88 uint32_t RESERVED6[4U]; /**< Reserved for future use */ 89 uint32_t RESERVED7[1U]; /**< Reserved for future use */ 90 uint32_t RESERVED8[963U]; /**< Reserved for future use */ 91 __IM uint32_t IPVERSION_SET; /**< IPVERSION */ 92 __IOM uint32_t EN_SET; /**< Enable */ 93 __IOM uint32_t CTRL_SET; /**< Control */ 94 __IOM uint32_t CMD_SET; /**< Command */ 95 __IOM uint32_t TIMER_SET; /**< Timer */ 96 __IM uint32_t STATUS_SET; /**< Status */ 97 __IOM uint32_t MASKREQ_SET; /**< Mask Request */ 98 __IM uint32_t STMASK_SET; /**< Scan Table Mask */ 99 __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ 100 __IOM uint32_t IF_SET; /**< Interrupt Flags */ 101 __IOM uint32_t IEN_SET; /**< Interrupt Enable */ 102 __IOM uint32_t TRIGGER_SET; /**< Trigger */ 103 uint32_t RESERVED9[1U]; /**< Reserved for future use */ 104 uint32_t RESERVED10[5U]; /**< Reserved for future use */ 105 IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ 106 uint32_t RESERVED11[2U]; /**< Reserved for future use */ 107 __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ 108 __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO DATA */ 109 __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ 110 __IM uint32_t SINGLEDATA_SET; /**< Single Data */ 111 __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ 112 __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ 113 __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ 114 __IM uint32_t SCANDATA_SET; /**< Scan Data */ 115 uint32_t RESERVED12[1U]; /**< Reserved for future use */ 116 uint32_t RESERVED13[1U]; /**< Reserved for future use */ 117 __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ 118 uint32_t RESERVED14[1U]; /**< Reserved for future use */ 119 IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U]; /**< SCANTABLE */ 120 uint32_t RESERVED15[4U]; /**< Reserved for future use */ 121 uint32_t RESERVED16[1U]; /**< Reserved for future use */ 122 uint32_t RESERVED17[963U]; /**< Reserved for future use */ 123 __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ 124 __IOM uint32_t EN_CLR; /**< Enable */ 125 __IOM uint32_t CTRL_CLR; /**< Control */ 126 __IOM uint32_t CMD_CLR; /**< Command */ 127 __IOM uint32_t TIMER_CLR; /**< Timer */ 128 __IM uint32_t STATUS_CLR; /**< Status */ 129 __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ 130 __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ 131 __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ 132 __IOM uint32_t IF_CLR; /**< Interrupt Flags */ 133 __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ 134 __IOM uint32_t TRIGGER_CLR; /**< Trigger */ 135 uint32_t RESERVED18[1U]; /**< Reserved for future use */ 136 uint32_t RESERVED19[5U]; /**< Reserved for future use */ 137 IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ 138 uint32_t RESERVED20[2U]; /**< Reserved for future use */ 139 __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ 140 __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO DATA */ 141 __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ 142 __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ 143 __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ 144 __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ 145 __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ 146 __IM uint32_t SCANDATA_CLR; /**< Scan Data */ 147 uint32_t RESERVED21[1U]; /**< Reserved for future use */ 148 uint32_t RESERVED22[1U]; /**< Reserved for future use */ 149 __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ 150 uint32_t RESERVED23[1U]; /**< Reserved for future use */ 151 IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U]; /**< SCANTABLE */ 152 uint32_t RESERVED24[4U]; /**< Reserved for future use */ 153 uint32_t RESERVED25[1U]; /**< Reserved for future use */ 154 uint32_t RESERVED26[963U]; /**< Reserved for future use */ 155 __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ 156 __IOM uint32_t EN_TGL; /**< Enable */ 157 __IOM uint32_t CTRL_TGL; /**< Control */ 158 __IOM uint32_t CMD_TGL; /**< Command */ 159 __IOM uint32_t TIMER_TGL; /**< Timer */ 160 __IM uint32_t STATUS_TGL; /**< Status */ 161 __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ 162 __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ 163 __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ 164 __IOM uint32_t IF_TGL; /**< Interrupt Flags */ 165 __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ 166 __IOM uint32_t TRIGGER_TGL; /**< Trigger */ 167 uint32_t RESERVED27[1U]; /**< Reserved for future use */ 168 uint32_t RESERVED28[5U]; /**< Reserved for future use */ 169 IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ 170 uint32_t RESERVED29[2U]; /**< Reserved for future use */ 171 __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ 172 __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO DATA */ 173 __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ 174 __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ 175 __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ 176 __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ 177 __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ 178 __IM uint32_t SCANDATA_TGL; /**< Scan Data */ 179 uint32_t RESERVED30[1U]; /**< Reserved for future use */ 180 uint32_t RESERVED31[1U]; /**< Reserved for future use */ 181 __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ 182 uint32_t RESERVED32[1U]; /**< Reserved for future use */ 183 IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U]; /**< SCANTABLE */ 184 uint32_t RESERVED33[4U]; /**< Reserved for future use */ 185 uint32_t RESERVED34[1U]; /**< Reserved for future use */ 186 } IADC_TypeDef; 187 /** @} End of group EFR32MG24_IADC */ 188 189 /**************************************************************************//** 190 * @addtogroup EFR32MG24_IADC 191 * @{ 192 * @defgroup EFR32MG24_IADC_BitFields IADC Bit Fields 193 * @{ 194 *****************************************************************************/ 195 196 /* Bit fields for IADC IPVERSION */ 197 #define _IADC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for IADC_IPVERSION */ 198 #define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ 199 #define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ 200 #define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ 201 #define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_IPVERSION */ 202 #define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ 203 204 /* Bit fields for IADC EN */ 205 #define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ 206 #define _IADC_EN_MASK 0x00000003UL /**< Mask for IADC_EN */ 207 #define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ 208 #define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ 209 #define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ 210 #define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ 211 #define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ 212 #define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ 213 #define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ 214 #define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ 215 #define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ 216 #define IADC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ 217 #define _IADC_EN_DISABLING_SHIFT 1 /**< Shift value for IADC_DISABLING */ 218 #define _IADC_EN_DISABLING_MASK 0x2UL /**< Bit mask for IADC_DISABLING */ 219 #define _IADC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ 220 #define IADC_EN_DISABLING_DEFAULT (_IADC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_EN */ 221 222 /* Bit fields for IADC CTRL */ 223 #define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ 224 #define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ 225 #define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ 226 #define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ 227 #define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ 228 #define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ 229 #define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ 230 #define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ 231 #define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ 232 #define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ 233 #define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ 234 #define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ 235 #define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ 236 #define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ 237 #define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ 238 #define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ 239 #define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ 240 #define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ 241 #define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ 242 #define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ 243 #define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ 244 #define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ 245 #define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ 246 #define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ 247 #define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ 248 #define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ 249 #define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ 250 #define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ 251 #define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ 252 #define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ 253 #define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ 254 #define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ 255 #define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ 256 #define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ 257 #define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ 258 #define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ 259 #define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ 260 #define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ 261 #define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ 262 #define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ 263 #define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ 264 #define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ 265 #define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ 266 #define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ 267 #define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ 268 #define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ 269 #define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ 270 #define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ 271 #define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ 272 #define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ 273 #define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ 274 #define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ 275 #define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ 276 #define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ 277 #define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ 278 #define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ 279 #define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ 280 #define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ 281 #define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ 282 #define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ 283 #define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ 284 #define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ 285 #define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ 286 #define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ 287 288 /* Bit fields for IADC CMD */ 289 #define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ 290 #define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ 291 #define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ 292 #define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ 293 #define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ 294 #define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ 295 #define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ 296 #define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ 297 #define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ 298 #define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ 299 #define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ 300 #define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ 301 #define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ 302 #define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ 303 #define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ 304 #define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ 305 #define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ 306 #define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ 307 #define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ 308 #define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ 309 #define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ 310 #define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ 311 #define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ 312 #define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ 313 #define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ 314 #define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ 315 #define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ 316 #define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ 317 #define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ 318 #define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ 319 #define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ 320 #define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ 321 #define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ 322 #define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ 323 #define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ 324 #define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ 325 #define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ 326 #define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ 327 #define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ 328 #define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ 329 #define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ 330 #define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ 331 332 /* Bit fields for IADC TIMER */ 333 #define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ 334 #define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ 335 #define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ 336 #define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ 337 #define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ 338 #define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ 339 340 /* Bit fields for IADC STATUS */ 341 #define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ 342 #define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ 343 #define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ 344 #define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ 345 #define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ 346 #define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 347 #define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ 348 #define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ 349 #define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ 350 #define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ 351 #define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 352 #define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ 353 #define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ 354 #define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ 355 #define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ 356 #define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 357 #define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ 358 #define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ 359 #define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ 360 #define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ 361 #define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 362 #define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ 363 #define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ 364 #define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ 365 #define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ 366 #define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 367 #define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ 368 #define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ 369 #define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ 370 #define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ 371 #define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 372 #define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ 373 #define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ 374 #define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ 375 #define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ 376 #define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 377 #define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ 378 #define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ 379 #define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ 380 #define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ 381 #define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 382 #define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ 383 #define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ 384 #define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ 385 #define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ 386 #define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 387 #define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ 388 #define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ 389 #define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ 390 #define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ 391 #define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 392 #define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ 393 #define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ 394 #define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ 395 #define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ 396 #define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 397 #define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ 398 #define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ 399 #define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ 400 #define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ 401 #define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 402 #define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ 403 #define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ 404 #define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ 405 #define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ 406 #define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 407 #define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ 408 #define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ 409 #define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ 410 #define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ 411 #define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ 412 #define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ 413 414 /* Bit fields for IADC MASKREQ */ 415 #define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ 416 #define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ 417 #define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ 418 #define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ 419 #define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ 420 #define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ 421 422 /* Bit fields for IADC STMASK */ 423 #define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ 424 #define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ 425 #define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ 426 #define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ 427 #define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ 428 #define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ 429 430 /* Bit fields for IADC CMPTHR */ 431 #define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ 432 #define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ 433 #define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ 434 #define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ 435 #define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ 436 #define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ 437 #define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ 438 #define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ 439 #define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ 440 #define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ 441 442 /* Bit fields for IADC IF */ 443 #define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ 444 #define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ 445 #define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ 446 #define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ 447 #define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ 448 #define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 449 #define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ 450 #define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ 451 #define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ 452 #define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ 453 #define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 454 #define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ 455 #define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ 456 #define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ 457 #define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ 458 #define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 459 #define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ 460 #define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ 461 #define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ 462 #define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ 463 #define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 464 #define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ 465 #define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ 466 #define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ 467 #define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ 468 #define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 469 #define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ 470 #define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ 471 #define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ 472 #define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ 473 #define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 474 #define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ 475 #define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ 476 #define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ 477 #define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ 478 #define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 479 #define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ 480 #define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ 481 #define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ 482 #define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ 483 #define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 484 #define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ 485 #define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ 486 #define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ 487 #define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ 488 #define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 489 #define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ 490 #define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ 491 #define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ 492 #define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ 493 #define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 494 #define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ 495 #define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ 496 #define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ 497 #define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ 498 #define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 499 #define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ 500 #define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ 501 #define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ 502 #define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ 503 #define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 504 #define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ 505 #define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ 506 #define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ 507 #define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ 508 #define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 509 #define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ 510 #define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ 511 #define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ 512 #define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ 513 #define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ 514 #define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ 515 516 /* Bit fields for IADC IEN */ 517 #define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ 518 #define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ 519 #define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ 520 #define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ 521 #define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ 522 #define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 523 #define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ 524 #define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ 525 #define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ 526 #define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ 527 #define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 528 #define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ 529 #define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ 530 #define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ 531 #define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ 532 #define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 533 #define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ 534 #define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ 535 #define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ 536 #define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ 537 #define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 538 #define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ 539 #define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ 540 #define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ 541 #define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ 542 #define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 543 #define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ 544 #define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ 545 #define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ 546 #define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ 547 #define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 548 #define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ 549 #define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ 550 #define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ 551 #define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ 552 #define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 553 #define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ 554 #define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ 555 #define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ 556 #define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ 557 #define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 558 #define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ 559 #define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ 560 #define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ 561 #define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ 562 #define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 563 #define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ 564 #define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ 565 #define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ 566 #define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ 567 #define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 568 #define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ 569 #define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ 570 #define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ 571 #define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ 572 #define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 573 #define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ 574 #define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ 575 #define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ 576 #define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ 577 #define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 578 #define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ 579 #define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ 580 #define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ 581 #define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ 582 #define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 583 #define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ 584 #define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ 585 #define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ 586 #define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ 587 #define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ 588 #define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ 589 590 /* Bit fields for IADC TRIGGER */ 591 #define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ 592 #define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ 593 #define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ 594 #define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ 595 #define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ 596 #define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ 597 #define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ 598 #define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ 599 #define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ 600 #define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ 601 #define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ 602 #define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ 603 #define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ 604 #define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ 605 #define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ 606 #define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ 607 #define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ 608 #define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ 609 #define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ 610 #define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ 611 #define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ 612 #define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ 613 #define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ 614 #define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ 615 #define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ 616 #define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ 617 #define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ 618 #define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ 619 #define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ 620 #define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ 621 #define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ 622 #define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ 623 #define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ 624 #define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ 625 #define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ 626 #define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ 627 #define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ 628 #define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ 629 #define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ 630 #define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ 631 #define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ 632 #define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ 633 #define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ 634 #define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ 635 #define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ 636 #define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ 637 #define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ 638 #define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ 639 #define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ 640 #define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ 641 #define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ 642 #define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ 643 #define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ 644 #define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ 645 #define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ 646 #define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ 647 #define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ 648 649 /* Bit fields for IADC CFG */ 650 #define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ 651 #define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ 652 #define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ 653 #define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ 654 #define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ 655 #define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ 656 #define _IADC_CFG_ADCMODE_HIGHSPEED 0x00000001UL /**< Mode HIGHSPEED for IADC_CFG */ 657 #define _IADC_CFG_ADCMODE_HIGHACCURACY 0x00000002UL /**< Mode HIGHACCURACY for IADC_CFG */ 658 #define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ 659 #define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ 660 #define IADC_CFG_ADCMODE_HIGHSPEED (_IADC_CFG_ADCMODE_HIGHSPEED << 0) /**< Shifted mode HIGHSPEED for IADC_CFG */ 661 #define IADC_CFG_ADCMODE_HIGHACCURACY (_IADC_CFG_ADCMODE_HIGHACCURACY << 0) /**< Shifted mode HIGHACCURACY for IADC_CFG */ 662 #define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ 663 #define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ 664 #define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ 665 #define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ 666 #define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ 667 #define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ 668 #define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ 669 #define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ 670 #define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ 671 #define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ 672 #define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ 673 #define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ 674 #define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ 675 #define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ 676 #define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ 677 #define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ 678 #define _IADC_CFG_OSRHA_SHIFT 5 /**< Shift value for IADC_OSRHA */ 679 #define _IADC_CFG_OSRHA_MASK 0xE0UL /**< Bit mask for IADC_OSRHA */ 680 #define _IADC_CFG_OSRHA_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_CFG */ 681 #define _IADC_CFG_OSRHA_HIACC16 0x00000000UL /**< Mode HIACC16 for IADC_CFG */ 682 #define _IADC_CFG_OSRHA_HIACC32 0x00000001UL /**< Mode HIACC32 for IADC_CFG */ 683 #define _IADC_CFG_OSRHA_HIACC64 0x00000002UL /**< Mode HIACC64 for IADC_CFG */ 684 #define _IADC_CFG_OSRHA_HIACC92 0x00000003UL /**< Mode HIACC92 for IADC_CFG */ 685 #define _IADC_CFG_OSRHA_HIACC128 0x00000004UL /**< Mode HIACC128 for IADC_CFG */ 686 #define _IADC_CFG_OSRHA_HIACC256 0x00000005UL /**< Mode HIACC256 for IADC_CFG */ 687 #define IADC_CFG_OSRHA_DEFAULT (_IADC_CFG_OSRHA_DEFAULT << 5) /**< Shifted mode DEFAULT for IADC_CFG */ 688 #define IADC_CFG_OSRHA_HIACC16 (_IADC_CFG_OSRHA_HIACC16 << 5) /**< Shifted mode HIACC16 for IADC_CFG */ 689 #define IADC_CFG_OSRHA_HIACC32 (_IADC_CFG_OSRHA_HIACC32 << 5) /**< Shifted mode HIACC32 for IADC_CFG */ 690 #define IADC_CFG_OSRHA_HIACC64 (_IADC_CFG_OSRHA_HIACC64 << 5) /**< Shifted mode HIACC64 for IADC_CFG */ 691 #define IADC_CFG_OSRHA_HIACC92 (_IADC_CFG_OSRHA_HIACC92 << 5) /**< Shifted mode HIACC92 for IADC_CFG */ 692 #define IADC_CFG_OSRHA_HIACC128 (_IADC_CFG_OSRHA_HIACC128 << 5) /**< Shifted mode HIACC128 for IADC_CFG */ 693 #define IADC_CFG_OSRHA_HIACC256 (_IADC_CFG_OSRHA_HIACC256 << 5) /**< Shifted mode HIACC256 for IADC_CFG */ 694 #define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ 695 #define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ 696 #define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ 697 #define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ 698 #define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ 699 #define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ 700 #define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ 701 #define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ 702 #define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ 703 #define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ 704 #define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ 705 #define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ 706 #define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ 707 #define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ 708 #define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ 709 #define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ 710 #define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ 711 #define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ 712 #define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ 713 #define _IADC_CFG_REFSEL_VREF2P5 0x00000002UL /**< Mode VREF2P5 for IADC_CFG */ 714 #define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ 715 #define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ 716 #define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ 717 #define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ 718 #define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ 719 #define IADC_CFG_REFSEL_VREF2P5 (_IADC_CFG_REFSEL_VREF2P5 << 16) /**< Shifted mode VREF2P5 for IADC_CFG */ 720 #define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ 721 #define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ 722 #define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ 723 #define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ 724 #define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ 725 #define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ 726 #define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ 727 #define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ 728 #define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ 729 #define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ 730 #define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ 731 #define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ 732 #define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ 733 #define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ 734 #define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ 735 #define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ 736 #define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ 737 #define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ 738 #define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ 739 #define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ 740 #define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ 741 #define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ 742 #define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ 743 #define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ 744 #define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ 745 #define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ 746 747 /* Bit fields for IADC SCALE */ 748 #define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ 749 #define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ 750 #define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ 751 #define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ 752 #define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ 753 #define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ 754 #define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ 755 #define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ 756 #define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ 757 #define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ 758 #define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ 759 #define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ 760 #define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ 761 #define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ 762 #define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ 763 #define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ 764 #define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ 765 #define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ 766 #define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ 767 768 /* Bit fields for IADC SCHED */ 769 #define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ 770 #define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ 771 #define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ 772 #define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ 773 #define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ 774 #define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ 775 776 /* Bit fields for IADC SINGLEFIFOCFG */ 777 #define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ 778 #define _IADC_SINGLEFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SINGLEFIFOCFG */ 779 #define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ 780 #define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ 781 #define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ 782 #define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ 783 #define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ 784 #define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ 785 #define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ 786 #define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ 787 #define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ 788 #define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ 789 #define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ 790 #define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ 791 #define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ 792 #define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ 793 #define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ 794 #define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ 795 #define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ 796 #define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ 797 #define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ 798 #define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ 799 #define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ 800 #define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ 801 #define _IADC_SINGLEFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ 802 #define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ 803 #define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ 804 #define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ 805 #define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ 806 #define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ 807 #define _IADC_SINGLEFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SINGLEFIFOCFG */ 808 #define _IADC_SINGLEFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SINGLEFIFOCFG */ 809 #define _IADC_SINGLEFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SINGLEFIFOCFG */ 810 #define _IADC_SINGLEFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SINGLEFIFOCFG */ 811 #define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ 812 #define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ 813 #define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ 814 #define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ 815 #define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ 816 #define IADC_SINGLEFIFOCFG_DVL_VALID5 (_IADC_SINGLEFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SINGLEFIFOCFG */ 817 #define IADC_SINGLEFIFOCFG_DVL_VALID6 (_IADC_SINGLEFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SINGLEFIFOCFG */ 818 #define IADC_SINGLEFIFOCFG_DVL_VALID7 (_IADC_SINGLEFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SINGLEFIFOCFG */ 819 #define IADC_SINGLEFIFOCFG_DVL_VALID8 (_IADC_SINGLEFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SINGLEFIFOCFG */ 820 #define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ 821 #define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ 822 #define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ 823 #define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ 824 #define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ 825 #define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ 826 #define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ 827 #define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ 828 #define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ 829 830 /* Bit fields for IADC SINGLEFIFODATA */ 831 #define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ 832 #define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ 833 #define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ 834 #define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ 835 #define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ 836 #define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ 837 838 /* Bit fields for IADC SINGLEFIFOSTAT */ 839 #define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ 840 #define _IADC_SINGLEFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SINGLEFIFOSTAT */ 841 #define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ 842 #define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ 843 #define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ 844 #define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ 845 846 /* Bit fields for IADC SINGLEDATA */ 847 #define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ 848 #define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ 849 #define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ 850 #define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ 851 #define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ 852 #define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ 853 854 /* Bit fields for IADC SCANFIFOCFG */ 855 #define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ 856 #define _IADC_SCANFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SCANFIFOCFG */ 857 #define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ 858 #define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ 859 #define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ 860 #define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ 861 #define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ 862 #define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ 863 #define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ 864 #define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ 865 #define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ 866 #define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ 867 #define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ 868 #define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ 869 #define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ 870 #define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ 871 #define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ 872 #define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ 873 #define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ 874 #define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ 875 #define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ 876 #define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ 877 #define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ 878 #define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ 879 #define _IADC_SCANFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ 880 #define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ 881 #define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ 882 #define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ 883 #define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ 884 #define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ 885 #define _IADC_SCANFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SCANFIFOCFG */ 886 #define _IADC_SCANFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SCANFIFOCFG */ 887 #define _IADC_SCANFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SCANFIFOCFG */ 888 #define _IADC_SCANFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SCANFIFOCFG */ 889 #define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ 890 #define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ 891 #define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ 892 #define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ 893 #define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ 894 #define IADC_SCANFIFOCFG_DVL_VALID5 (_IADC_SCANFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SCANFIFOCFG */ 895 #define IADC_SCANFIFOCFG_DVL_VALID6 (_IADC_SCANFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SCANFIFOCFG */ 896 #define IADC_SCANFIFOCFG_DVL_VALID7 (_IADC_SCANFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SCANFIFOCFG */ 897 #define IADC_SCANFIFOCFG_DVL_VALID8 (_IADC_SCANFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SCANFIFOCFG */ 898 #define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ 899 #define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ 900 #define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ 901 #define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ 902 #define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ 903 #define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ 904 #define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ 905 #define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ 906 #define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ 907 908 /* Bit fields for IADC SCANFIFODATA */ 909 #define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ 910 #define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ 911 #define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ 912 #define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ 913 #define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ 914 #define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ 915 916 /* Bit fields for IADC SCANFIFOSTAT */ 917 #define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ 918 #define _IADC_SCANFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SCANFIFOSTAT */ 919 #define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ 920 #define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ 921 #define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ 922 #define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ 923 924 /* Bit fields for IADC SCANDATA */ 925 #define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ 926 #define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ 927 #define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ 928 #define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ 929 #define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ 930 #define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ 931 932 /* Bit fields for IADC SINGLE */ 933 #define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ 934 #define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ 935 #define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ 936 #define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ 937 #define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ 938 #define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ 939 #define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ 940 #define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ 941 #define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ 942 #define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ 943 #define _IADC_SINGLE_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SINGLE */ 944 #define _IADC_SINGLE_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SINGLE */ 945 #define _IADC_SINGLE_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SINGLE */ 946 #define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ 947 #define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ 948 #define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ 949 #define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ 950 #define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ 951 #define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ 952 #define IADC_SINGLE_PORTNEG_DAC1 (_IADC_SINGLE_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SINGLE */ 953 #define IADC_SINGLE_PORTNEG_PADANA1 (_IADC_SINGLE_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SINGLE */ 954 #define IADC_SINGLE_PORTNEG_PADANA3 (_IADC_SINGLE_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SINGLE */ 955 #define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ 956 #define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ 957 #define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ 958 #define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ 959 #define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ 960 #define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ 961 #define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ 962 #define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ 963 #define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ 964 #define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ 965 #define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ 966 #define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ 967 #define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ 968 #define _IADC_SINGLE_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SINGLE */ 969 #define _IADC_SINGLE_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SINGLE */ 970 #define _IADC_SINGLE_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SINGLE */ 971 #define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ 972 #define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ 973 #define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ 974 #define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ 975 #define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ 976 #define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ 977 #define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ 978 #define IADC_SINGLE_PORTPOS_DAC0 (_IADC_SINGLE_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SINGLE */ 979 #define IADC_SINGLE_PORTPOS_PADANA0 (_IADC_SINGLE_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SINGLE */ 980 #define IADC_SINGLE_PORTPOS_PADANA2 (_IADC_SINGLE_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SINGLE */ 981 #define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ 982 #define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ 983 #define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ 984 #define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ 985 #define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ 986 #define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ 987 #define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ 988 #define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ 989 #define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ 990 #define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ 991 #define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ 992 #define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ 993 #define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ 994 #define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ 995 #define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ 996 #define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ 997 #define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ 998 #define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ 999 1000 /* Bit fields for IADC SCAN */ 1001 #define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ 1002 #define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ 1003 #define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ 1004 #define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ 1005 #define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ 1006 #define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ 1007 #define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ 1008 #define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ 1009 #define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ 1010 #define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ 1011 #define _IADC_SCAN_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SCAN */ 1012 #define _IADC_SCAN_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SCAN */ 1013 #define _IADC_SCAN_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SCAN */ 1014 #define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ 1015 #define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ 1016 #define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ 1017 #define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ 1018 #define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ 1019 #define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ 1020 #define IADC_SCAN_PORTNEG_DAC1 (_IADC_SCAN_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SCAN */ 1021 #define IADC_SCAN_PORTNEG_PADANA1 (_IADC_SCAN_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SCAN */ 1022 #define IADC_SCAN_PORTNEG_PADANA3 (_IADC_SCAN_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SCAN */ 1023 #define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ 1024 #define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ 1025 #define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ 1026 #define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ 1027 #define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ 1028 #define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ 1029 #define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ 1030 #define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ 1031 #define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ 1032 #define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ 1033 #define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ 1034 #define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ 1035 #define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ 1036 #define _IADC_SCAN_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SCAN */ 1037 #define _IADC_SCAN_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SCAN */ 1038 #define _IADC_SCAN_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SCAN */ 1039 #define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ 1040 #define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ 1041 #define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ 1042 #define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ 1043 #define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ 1044 #define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ 1045 #define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ 1046 #define IADC_SCAN_PORTPOS_DAC0 (_IADC_SCAN_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SCAN */ 1047 #define IADC_SCAN_PORTPOS_PADANA0 (_IADC_SCAN_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SCAN */ 1048 #define IADC_SCAN_PORTPOS_PADANA2 (_IADC_SCAN_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SCAN */ 1049 #define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ 1050 #define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ 1051 #define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ 1052 #define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ 1053 #define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ 1054 #define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ 1055 #define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ 1056 #define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ 1057 #define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ 1058 #define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ 1059 #define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ 1060 #define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ 1061 #define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ 1062 #define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ 1063 #define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ 1064 #define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ 1065 #define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ 1066 #define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ 1067 1068 /** @} End of group EFR32MG24_IADC_BitFields */ 1069 /** @} End of group EFR32MG24_IADC */ 1070 /** @} End of group Parts */ 1071 1072 #endif /* EFR32MG24_IADC_H */ 1073
